; $Id$: ; constants that will be used directly in the assembler, but will come from the .tcs files #def NSAMPLES = 30; // was before in c13 #def TRACKLETS_3Q_MODE = 3 ; normal tracklets mode, with 3 charge integration windows #def TRACKLETS_DIS_MODE = 2 ; tracklets are disabled #def TRACKLETS_TPT_MODE = 1 ; test pattern mode #def TRACKLETS_COS_MODE = 0 ; cosmic mode #def TRACKLETS_MODE = TRACKLETS_3Q_MODE ; select the tracklet mode ; in _DIS_, _3Q_, _TPT_ mode: send MCM headers when not tracklets? #def DONT_SEND_EMPTY_HDR_TR = 0 ; in _3Q_: ; - parameters of the 3-rd charge window Q2: left margin and width #def Q2_LEFT_MRG_VAL = 7; #def Q2_WIN_WIDTH_VAL = 7; ; - use floating point representation of the charges? ; otherwise scaling by a fixed factor #def DYN_FP_Q = 1; ; floating point mode for Q enabled ;#def ADD_CONST_TO_HCID = 0x80 ; either 0 or not defined, OR 0x80 #def RAW_RDOUT_FULL = 0 ; no zero suppression #def RAW_RDOUT_ZS = 1 ; with zero suppression ; related options #def DONT_SEND_EMPTY_HDR_ZS = 0 ; suppress sending MCM header when no ADC data #def ZS_FULL_NO = 0; #def ZS_FULL_128 = 1; #def ZS_FULL_256 = 2; #def ZS_FULL_1024 = 3; #def ZS_FULL_MOD = ZS_FULL_NO ; 0 for always ZS, 1, 2, 3 for full readout each 128, 256, 1024 event #def RAW_RDOUT_TP = 2 ; test pattern mode ; related options #def RAW_RDOUT_TP_TYPE = 0 ; test pattern type, from 0 to 7 of them 1, 2, 3, 6 recommended #def RAW_RDOUT_MODE = RAW_RDOUT_FULL ; select the tracklet mode #ifeq RAW_RDOUT_MODE, RAW_RDOUT_FULL ; enable/disable related options #def FULL_WITH_STAT = 1 ; with accumulating RMS statistics or not #else #def FULL_WITH_STAT = 0 ; no statistics otherwise: don't change this value! #endif ; TRAP register values, most of them identical in all MCMs, some values are specific to BM, HCM ; some trivial values will be generated internally, a list will come later here. #def TPFE_VAL = 24; #def TPQS0_VAL = 0; #def TPQE0_VAL = 6; #def TPQS1_VAL = 14; #def TPQE1_VAL = 20; #def EBAQA_VAL = 0; #def ARBTIM_VAL = b1101; #def DMDELA_VAL = 2; // Nominal:2 used in DMDELA #def DMDELS_VAL = 15; // Nominal:15 used in DMDELS #def MEMCOR_VAL = 0x11F; // all hamming corrections on #def IRQHW_VAL = 0x017; // IRQ_ACQ, IRQ_CLR, IRQ_RAW, IRQ_TST #def IRQHL_VAL = 0x017; // IRQ_ACQ, IRQ_CLR, IRQ_RAW, IRQ_TST #def CPUxCLK_VAL = 0x1F; // 4x ; end signature #def NSIG_TR_VAL = 0x1000; #def NSIG_RR_VAL = 0x0000; #def NDLY_VAL = 0x12492492; // 29-bit #def NDLY_HCM_VAL = 0x12492492; // 29-bit #def NITM0_VAL = 0x019a; // normally = nsamples*12+50 and up to 12 bit #def NIP4D_VAL = 0x3; #def NICLK_VAL = 0x1F; #def FILCLK_VAL= 0x07; #def PRECLK_VAL= 0x07; ; for normal MCMs and BM, no HCM #def NIODE_VAL = 0x1B; #def NIOCE_VAL = 0x1F; #def NIIDE_VAL = 0x02; #def NIICE_VAL = 0x1F; // but later in asm program was overwritten with 1? #def ADCEN_VAL = 0x07; ; not ready ; HCM only #def NIODE_HCM_VAL = 0x02; #def NIOCE_HCM_VAL = 0x01; #def NIIDE_HCM_VAL = 0x07; #def NIICE_HCM_VAL = 0x07; ; ADC ; bit 8 in ADCPAR must be set for VHDL simulation! #def ADCPAR_VAL = 0x189a5; // bit 8 must be set for simulation! #def ADCINB_VAL = b10; #def ADCDAC_VAL = b00000; // 5 bit ; ; note, ADCMSK could be patched, therefore will be removed from here ;#def ADCMSK_A_BND = 0x07FFFF; // 0,4,8,12 & A-side ;#def ADCMSK_B_BND = 0x1FFFF8; // 3,7,11,15 & B-side ;#def ADCMSK_VAL = 0x1FFFFF; // all others ; and will be stored in DMEM: