/**************************************/ /* ALICE TRD */ /* Read-out board */ /* SCSN Configuration File */ /* */ /* 2004-03-08 */ /* Jan de Cuveland, Venelin Angelov */ /**************************************/ // // Svn $Id$: // // Readout tree (logical view) // // 00 01 -0> 02 <3- 03 // `--------1/ \----------, // | // 04 05 -0> 06 <3- 07 2 // `--------1/ \--------0,| // || // 16 --> // 08 09 -0> 10 <3- 11 || // `--------1/ \--------1�| // | // 12 13 -0> 14 <3- 15 3 // `--------1/ \----------� // ************************************* // Common parameters // ************************************* // SCSN transactions // Event Buffer write EBD , EBD_VAL write EBSF , EBSF_VAL write EBAQA, EBAQA_VAL // TPP write TPFS , TPFS_VAL write TPFE , TPFE_VAL write TPQS0, TPQS0_VAL write TPQE0, TPQE0_VAL write TPQS1, TPQS1_VAL write TPQE1, TPQE1_VAL write TPFP , TPFP_VAL write TPHT , TPHT_VAL write TPVT , TPVT_VAL write TPVBY, TPVBY_VAL write TPCT , TPCT_VAL write TPCL , TPCL_VAL write TPPT0, TPPT0_VAL; // Common Timer Delay write TPPGR, TPPGR_VAL; // Response Time to GSM write TPPAE, TPPAE_VAL; // Event Buffer Data Acquisition End // Tail Cancellation // Bypass write FTBY, FTBY_VAL; restrict EnableTailCancellation; // Long Decay Weight write FTAL, FTAL_VAL; // Long Decay Parameter write FTLL, FTLL_VAL; // Short Decay Parameter write FTLS, FTLS_VAL; restrict 1 // Pedestal filter // ----- pedestal filter ----- // Bypass write FPBY, FPBY_VAL; restrict FPBY_VAL; // only when not bypassed! // Time Constant write FPTC, FPTC_VAL; // Additive write FPNP, FPNP_VAL; restrict 1; // Gain Filter // X-talk Filer write FCBY, FCBY_VAL write FCWn+0, XtalkM0 write FCWn+1, XtalkM1 write FCWn+2, XtalkM2 write FCWn+3, XtalkM3 write FCWn+4, XtalkM4 // Position // some timing settings // EXPORT LATER to run_parameters.tcs! // w/r // 11 - fastest, 00 - slowest write ARBTIM, ARBTIM_VAL write DMDELA, DMDELA_VAL write DMDELS, DMDELS_VAL write MEMCOR, MEMCOR_VAL write SCALE_Y_DM_SCSN, SCALE_Y write OFFS_Y_DM_SCSN, OFFS_Y write SCALE_D_DM_SCSN, SCALE_D write SCALE_Q_DM_SCSN, SCALE_Q ; // not used in fp mode write DEFL_CR_DM_SCSN, DEFL_CR ; // not used now //write TPCBY, 0 // ------------------------ // set constant registers // ------------------------ // Event Counter, con12, not necessary //write C12CPUA_DB,1; // the counting starts from 1 // Number of Samples, c13, not necessary //write C13CPUA_DB, NSAMPLES // Tracklet & Raw Data End Marker write NES, (NSIG_RR_VAL << 16) | NSIG_TR_VAL // ------------------------- // set int entry addresses // ------------------------- write IA0+IRQ_CLR, lbl_CLR_cpu0; // set int_clr start addr for cpu0 write IA1+IRQ_CLR, lbl_CLR_cpu1; // set int_clr start addr for cpu1 write IA2+IRQ_CLR, lbl_CLR_cpu2; // set int_clr start addr for cpu2 write IA3+IRQ_CLR, lbl_CLR_cpu3; // set int_clr start addr for cpu3 write IA0+IRQ_ACQ, lbl_INIT_cpu0; // set int_acq start addr for cpu0 write IA1+IRQ_ACQ, lbl_INIT_cpu1; // set int_acq start addr for cpu1 write IA2+IRQ_ACQ, lbl_INIT_cpu2; // set int_acq start addr for cpu2 write IA3+IRQ_ACQ, lbl_INIT_cpu3; // set int_acq start addr for cpu3 write IA0+IRQ_RAW, lbl_RAW_cpu0; // set int_raw start addr for cpu0 write IA1+IRQ_RAW, lbl_RAW_cpu1; // set int_raw start addr for cpu1 write IA2+IRQ_RAW, lbl_RAW_cpu2; // set int_raw start addr for cpu2 write IA3+IRQ_RAW, lbl_RAW_cpu3; // set int_raw start addr for cpu3 write IA0+IRQ_TST, lbl_LPW_cpu0; // set int_clr start addr for cpu0 write IA1+IRQ_TST, lbl_LPW_cpu1; // set int_clr start addr for cpu0 write IA2+IRQ_TST, lbl_LPW_cpu2; // set int_clr start addr for cpu0 write IA3+IRQ_TST, lbl_LPW_cpu3; // set int_clr start addr for cpu0 // --------------- // set int masks // --------------- write IRQHW0, IRQHW_VAL; // set irq_hw mask for cpu0 write IRQHL0, IRQHL_VAL; // set irq_hl mask cor cpu0 write IRQHW1, IRQHW_VAL; // set irq_hw mask for cpu1 write IRQHL1, IRQHL_VAL; // set irq_hl mask cor cpu1 write IRQHW2, IRQHW_VAL; // set irq_hw mask for cpu2 write IRQHL2, IRQHL_VAL; // set irq_hl mask cor cpu2 write IRQHW3, IRQHW_VAL; // set irq_hw mask for cpu3 write IRQHL3, IRQHL_VAL; // set irq_hl mask cor cpu3 // -------------------------------- // NI transmission delay // -------------------------------- // for 50:50 here the number of 32 bit words send by each CPU. // delay between ni_ctrl and end marker, this is c8 of cpu3, set to 0 for no delay //write C08CPU3, delay_ni; // const8 //write IA3+IRQ_NI+2, lbl_NIFIFOE_cpu3; // start address irq_ni for fifo empty //write IA3+IRQ_TM, lbl_LOCALTM_cpu3; // start address counter/timer // -------------------------------- // configure global state machine // -------------------------------- write SML0, SML0_VAL; // the time for L0 accept write SML2, SML2_VAL; // the actual L1 time write SML1, SML1_VAL; // the time to start the raw data readout, a little bit later write ADCPAR, ADCPAR_VAL; write ADCINB, ADCINB_VAL; // invert bits write ADCDAC, ADCDAC_VAL; // ADC DAC 5-bit // ------------------------- // configure clock control // ------------------------- write CPU0CLK, CPUxCLK_VAL; write CPU1CLK, CPUxCLK_VAL; write CPU2CLK, CPUxCLK_VAL; write CPU3CLK, CPUxCLK_VAL; write FILCLK, FILCLK_VAL; write PRECLK, PRECLK_VAL; // ----------------------------- // configure network interface // ----------------------------- // NI output excludes and ctrl delay write NED , NED_VAL ; // but this can be modified by the patch maker! write NED_DB , NED_VAL ; // but this can be modified by the patch maker! write NDLY, NDLY_VAL; write NDLY_DB, NDLY_VAL; NP_PAR_SPR = (t_parit_bit << 4) | t_false_bit; write NP0, (NP_PAR_SPR << 3) | 4; write NP1, (NP_PAR_SPR << 3) | 4; write NP2, (NP_PAR_SPR << 3) | 4; write NP3, (NP_PAR_SPR << 3) | 4; // this one 32-bit word will be split to NP0..3 in the assembler program // as this can be modified by the patch maker, it will be stored to DBANK write NP0_3_DB, NP_PAR_SPR | (NP_PAR_SPR << 8) | (NP_PAR_SPR << 16) | (NP_PAR_SPR << 24); // set NI trigger readout order write NTRO, NIRO_NM; write NRRO, NIRO_NM; write NITM0, NITM0_VAL; write NIP4D, NIP4D_VAL; // delays write NICLK, NICLK_VAL; write NIODE, NIODE_VAL; write NIOCE, NIOCE_VAL; write NIIDE, NIIDE_VAL; write NIICE, NIICE_VAL; write NMOD, NMOD_RST_VAL; write NBND, NBND_VAL; // normally the reset value write NCUT, NCUT_SINGLE_P_VAL | (NCUT_SINGLE_P_VAL << 8) | (NCUT_SINGLE_P_VAL << 16) | (NCUT_SINGLE_P_VAL << 24); restrict ONEMCM write NED , NED_VAL | (1 << 14); restrict 1 // ************************************* // Specific configuration // ************************************* // ************************************* // Normal chips, no merger // ************************************* // switching the unused pre & clk & ni ports off of the normal chips restrict (1-ONEMCM) write chip0 , SMMODE, SMMODE_VAL_NM; write chip1 , SMMODE, SMMODE_VAL_NM; write chip3 , SMMODE, SMMODE_VAL_NM; write chip4 , SMMODE, SMMODE_VAL_NM; write chip5 , SMMODE, SMMODE_VAL_NM; write chip7 , SMMODE, SMMODE_VAL_NM; write chip8 , SMMODE, SMMODE_VAL_NM; write chip9 , SMMODE, SMMODE_VAL_NM; write chip11, SMMODE, SMMODE_VAL_NM; write chip12, SMMODE, SMMODE_VAL_NM; write chip13, SMMODE, SMMODE_VAL_NM; write chip15, SMMODE, SMMODE_VAL_NM; restrict 1 restrict ONEMCM write SMMODE, SMMODE_VAL_NM; restrict 1 // write only the default values here, can be modified by the patch maker //write ADCMSK_DM_SCSN, ADCMSK_VAL; write ADCMSK_DB , ADCMSK_VAL; // Boundary chips, mask unused ADC channels (and edge pads with high noise) restrict MASK_BOUNDARY_ADCS write chip_a_side | chip0 , ADCMSK_DB , ADCMSK_A_BND write chip_a_side | chip4 , ADCMSK_DB , ADCMSK_A_BND write chip_a_side | chip8 , ADCMSK_DB , ADCMSK_A_BND write chip_a_side | chip12 , ADCMSK_DB , ADCMSK_A_BND write chip_b_side | chip3 , ADCMSK_DB , ADCMSK_B_BND write chip_b_side | chip7 , ADCMSK_DB , ADCMSK_B_BND write chip_b_side | chip11 , ADCMSK_DB , ADCMSK_B_BND write chip_b_side | chip15 , ADCMSK_DB , ADCMSK_B_BND restrict (SINGLEROB==1) && (MASK_BOUNDARY_ADCS) write chip3 , ADCMSK_DB , ADCMSK_B_BND write chip7 , ADCMSK_DB , ADCMSK_B_BND write chip11, ADCMSK_DB , ADCMSK_B_BND write chip15, ADCMSK_DB , ADCMSK_B_BND write chip0 , ADCMSK_DB , ADCMSK_A_BND write chip4 , ADCMSK_DB , ADCMSK_A_BND write chip8 , ADCMSK_DB , ADCMSK_A_BND write chip12 , ADCMSK_DB , ADCMSK_A_BND restrict 1 //write C10CPU0, 0x700; // configure local counter of CPU0 to count L0A // Chip Position (ROB specific soon) // hc header field, some of them used in the normal chips! hc_0_SM_sector_nr = 8; // 5 bits, 0..17 hc_0_plane_nr = 2; // 3 bits, 0..5 hc_0_chamber_nr = 1; // 3 bits, 0..4 hc_0_side_chamber = 1; // 1 bits, 0..1 restrict (1-ONEMCM) // ************************************* // Column mergers readout order // ************************************* write chip2, NTRO, NIRO_CM; write chip6, NTRO, NIRO_CM; write chip10, NTRO, NIRO_CM; write chip14, NTRO, NIRO_CM; write chip2, NRRO, NIRO_CM; write chip6, NRRO, NIRO_CM; write chip10, NRRO, NIRO_CM; write chip14, NRRO, NIRO_CM; // can be modified by the patch maker! write chip2 , SMMODE, SMMODE_VAL_CM; write chip6 , SMMODE, SMMODE_VAL_CM; write chip10, SMMODE, SMMODE_VAL_CM; write chip14, SMMODE, SMMODE_VAL_CM; // ************************************* // Board mergers // ************************************* // Tracklet readout order write chip_bm, NTRO, NIRO_BM; // set NI raw data readout order write chip_bm, NRRO, NIRO_BM; //write chip_bm, ADCMSK_DM_SCSN, 0; write chip_bm, SMMODE, SMMODE_VAL_BM; // write chip_bm, C08CPU3, 0; // const8, delay ni not necessary if no data // ************************************* // Half-chamber mergers // ************************************* write chip_hm, NED, NED_HCM_VAL; write chip_hm, NED_DB, NED_HCM_VAL; write chip_hm, NDLY, NDLY_HCM_VAL; write chip_hm, NDLY_DB,NDLY_HCM_VAL; write chip_hm4, NTRO, NIRO_HM4; write chip_hm4, NRRO, NIRO_HM4; write chip_hm3, NTRO, NIRO_HM3; write chip_hm3, NRRO, NIRO_HM3; write chip_hm, NIODE, NIODE_HCM_VAL; write chip_hm, NIOCE, NIOCE_HCM_VAL; write chip_hm, NIIDE, NIIDE_HCM_VAL; write chip_hm, NIICE, NIICE_HCM_VAL; // write again to the DBANK write NTRO_DB, NIRO_NM; write chip2, NTRO_DB, NIRO_CM; write chip6, NTRO_DB, NIRO_CM; write chip10, NTRO_DB, NIRO_CM; write chip14, NTRO_DB, NIRO_CM; write chip_bm , NTRO_DB, NIRO_BM; write chip_hm3, NTRO_DB, NIRO_HM3; write chip_hm4, NTRO_DB, NIRO_HM4; write NRRO_DB, NIRO_NM; write chip2, NRRO_DB, NIRO_CM; write chip6, NRRO_DB, NIRO_CM; write chip10, NRRO_DB, NIRO_CM; write chip14, NRRO_DB, NIRO_CM; write chip_bm , NRRO_DB, NIRO_BM; write chip_hm3, NRRO_DB, NIRO_HM3; write chip_hm4, NRRO_DB, NIRO_HM4; // ADC off write ADCEN, ADCEN_VAL; write chip_hm, ADCEN, 0; write chip_bm, ADCEN, 0; //write chip_hm, ADCMSK_DM_SCSN, 0; write chip_hm, SMMODE, SMMODE_VAL_HM4; // here we can use broadcast, as we write to the DBANK and not to the register directly write SMMODE_DB, SMMODE_VAL_NM; write chip2 , SMMODE_DB, SMMODE_VAL_CM; write chip6 , SMMODE_DB, SMMODE_VAL_CM; write chip10, SMMODE_DB, SMMODE_VAL_CM; write chip14, SMMODE_DB, SMMODE_VAL_CM; write chip_bm, SMMODE_DB, SMMODE_VAL_BM; write chip_hm, SMMODE_DB, SMMODE_VAL_HM4; // Event Buffer Indicators // Event Buffer Single Indicator Threshold write EBIS, EBSingleIndicatorThreshold; // Event Buffer Sum Indicator Threshold write EBIT, EBSumIndicatorThreshold; // Event Buffer Indicator Look-up Table write EBIL, EBIndicatorLookupTable; // 0xF0; // Event Buffer Indicator Neighbor Sensitivity write EBIN, EBmarkIgnoreNeighbour; // timebin mask for zs, normally global write ZS_SMSK_DM_SCSN , EBmask_0_31_VAL; write ZS_SMSK_DM_SCSN+1, EBmask_32_63_VAL; // ADC channel OR-mask, normally individuall //restrict ZS_ADCMSK_OR==1 restrict RAW_RDOUT_MODE==RAW_RDOUT_ZS; write ZS_ADC_ORM_DM_SCSN, ZS_ADC_OR_Mask; restrict 1; // this is the former readout flag, 11b << 16 means both scsn and NI readout mcm_id_common = (3 << 16) | (DATA_FORMAT_VAL << 20); board_no = 0; chip_rob = chip_rob0; include src/common/write_mcmid.tcs board_no = 1; chip_rob = chip_rob1; include src/common/write_mcmid.tcs board_no = 2; chip_rob = chip_rob2; include src/common/write_mcmid.tcs board_no = 3; chip_rob = chip_rob3; include src/common/write_mcmid.tcs board_no = 4; chip_rob = chip_rob4; include src/common/write_mcmid.tcs board_no = 5; chip_rob = chip_rob5; include src/common/write_mcmid.tcs board_no = 6; chip_rob = chip_rob6; include src/common/write_mcmid.tcs board_no = 7; chip_rob = chip_rob7; include src/common/write_mcmid.tcs write chip_bm, ChipPOS_DB, (DATA_FORMAT_VAL << 20); // send nothing write chip_hm, ChipPOS_DB, (1100b << 16) | (DATA_FORMAT_VAL << 20); // send hc headers restrict 1 // the position independent part of the HC_0 can be used directly in the asm program: //asm HC_0_CNF = (1 << 17) | (FUNC_CODE << 10) | (HC_0_RAW_VER_MIN_NR << 3) | HC_0_ADD_HD_WORDS ; // reverse ingeneering: < not needed at all> //asm RAW_VER_MAJ_VER = (HC_0_CNF >> 10) & 0x7F; // 7-bits //asm RAW_VER_MIN_VER = (HC_0_CNF >> 3) & 0x7F; // 7-bits //asm RAW_ADD_HDR_WRD = HC_0_CNF & 0x07; // 3-bits // the full HC_0 is position dependent: // | 5 bits 0..17 | 3 bits 0..5 | 3 bits 0..4 | 1 bit 0..1 const HC_0 = (HC_0_CNF << 12) | (hc_0_SM_sector_nr << 7) | (hc_0_plane_nr << 4) | (hc_0_chamber_nr << 1) | hc_0_side_chamber; write h_0_DB, HC_0; // for all MCMs hcid HC_0_CNF; // the complete HC_0 sent is HC_0 << 2 | "01" //asm HC_0_TEST = HC_0 restrict ONEMCM mcm_id_common = (3 << 16); write ChipPOS_DB, mcm_id_common restrict 1 // clear the low power counters, beginning of IMEM write 0xF0E8, 0 write 0xF0EA, 0 write 0xF0EC, 0 write 0xF0EE, 0 // clear the low power counters, end of IMEM write 0xF0E9, 0 write 0xF0EB, 0 write 0xF0ED, 0 write 0xF0EF, 0 // Configure Global Counter write CTGCTRL, CTGCTRL_VAL // clear the start value write CTGDINI, 0; LP_REP = 0xF0E4 write LP_REP , 0xDEAD0 write LP_REP+1, 0xDEAD1 write LP_REP+2, 0xDEAD2 write LP_REP+3, 0xDEAD3 ADC2CPU = 0; restrict ADC2CPU one_adc_one_mcm_dec = 1; one_adc_one_mcm = 0; two_adcs_two_mcms = 0; two_adcs_one_mcm = 0; include src/common/adc2cpu.tcs restrict 1; // for cosmic trigger: set the thresholds: // the new program uses the 3 constants directly and probably doesn't need the C10CPU3! restrict TRACKLETS_MODE == TRACKLETS_COS_MODE //write C10CPU3, (COSMIC_Q_SHR & 0x0007) | ((COSMIC_MIN_HITS & 0x001F) << 3) | ((COSMIC_Q_THR & 0xFFFF) << 8); restrict 1; // in the ASM progam there is an option to count L0A: for this C11 of CPU0 must be initialised with 1