simdelay = 15;
write chip_mode, SEBDOU, mode_jtag;

// Activate the IRQ TST with the J2C function
write chip_jtag,      IA0+IRQ_TST, lbl_TST_cpu0;   // set int_clr start addr for cpu0

//cmd = 1000b;            // write at address 0
//data = (14 << 4) | 1;   // single bits, turning off the analog power on ORI
//write chip_jtag,      srv_command, cmd | (data << 4);
//expect chip_jtag,      srv_command, cmd | (data << 4);
//write chip_jtag,      SMCMD, CMD_CHK_TST;     // start
//wait simdelay
//expect chip_jtag,      SMCMD, lp_state
//
//wait 2000000

cmd = 1000b;            // write at address 0
data = reg_j2c;         // sel_p/s
write chip_jtag,      srv_command, cmd | (data << 4);
expect chip_jtag,      srv_command, cmd | (data << 4);
write chip_jtag,      SMCMD, CMD_CHK_TST;     // start
wait simdelay
expect chip_jtag,      SMCMD, lp_state

//wait 1000000

cmd = 0000b;            // read at address 0
write chip_jtag,      srv_command, cmd;      // read 0
write chip_jtag,      SMCMD, CMD_CHK_TST;     // start
wait simdelay
wait -100, 0, chip_jtag
expect chip_jtag,      SMCMD, lp_state
expect chip_jtag,      srv_outdata, 0x00

cmd = 0100b;            // read at address 4
write chip_jtag,      srv_command, cmd;      // read 1
write chip_jtag,      SMCMD, CMD_CHK_TST;     // start
wait simdelay
wait -100, 0, chip_jtag
expect chip_jtag,      SMCMD, lp_state
expect chip_jtag,      srv_outdata, reg_j2c

cmd = 0110b;            // read at address 6
write chip_jtag,      srv_command, cmd;      // read 1
write chip_jtag,      SMCMD, CMD_CHK_TST;     // start
wait simdelay
wait -100, 0, chip_jtag
expect chip_jtag,      SMCMD, lp_state
expect chip_jtag,      srv_outdata, ver_cpld

cmd = 0010b;            // read at address 2
write chip_jtag, srv_command, cmd;      // read 0
write chip_jtag, SMCMD, CMD_CHK_TST;     // start
wait simdelay
wait -100, 0, chip_jtag
expect chip_jtag, srv_outdata, (fault_ltc << 7)
expect chip_jtag, SMCMD, lp_state

write chip_jtag, IA0+IRQ_TST, lbl_LPW_cpu0;
restrict 1