; acq program in case of disabled tracklets or tracklets with test pattern

; $Id$:

; CPU0 makes refresh and when ready unblocks the others CPUs
; CPU1..3 prepare the up to 3 tracklets

acq:

    sem b0000_0000_0100_0000            ; g6 is adc_ch_msk_2, cpu1,2 will wait later on CPU0
    #ifeq TRACKLETS_MODE, TRACKLETS_TPT_MODE
    #ifdef cpu1
    ; read the pseudorandom counter, used to decide how many tracklets to produce
    lpio CTPDOUT, r1
    mov r1, scale_d
    #endif
    #endif

    ; refresh the interrupt vectors, all CPUs
    mvpcr +2, rstack
    jmp cc_uncond, load_irq_vec

    ; refresh the rest, only CPU0, the others wait in sync mode or prepare test pattern tracklets and then wait
#ifdef cpu3
    mvpcr +2, rstack
    jmp cc_uncond, load_direct_first_m
    mvpcr +2, rstack
    ; refresh 4 parameters from DMEM and 4 common constants from DBANK (as needed even on the HCM)
    jmp cc_uncond, load_dm_par
    mvpcr +2, rstack
    jmp cc_uncond, load_patchm_par
    mvpcr +2, rstack
    jmp cc_uncond, load_direct_all
    mvpcr +2, rstack
    jmp cc_uncond, load_direct_adc
    mvpcr +2, rstack
    jmp cc_uncond, load_direct_bm_m

    iext 0x100001
    mov  0x100001, r1
    shl 8, r1, adc_ch_msk_3             ; load 0x1000_0100, used as invert mask when sending tracklets
    nop

#else     ; 0, 1, 2

    ; cpu0,1,2 prepare some 'tracklets' in case of testpattern
    ; initialize the charges with 0xFFFFFF, which means no tracklet

    mov 0xFF, charge_i                  ; FF remains at bits 7..0
    mov 0, trackl_i

    #ifdef cpu1
    shl 8, charge_1, charge_1           ; put the FF to bits 15..8
    #endif

    #ifdef cpu2

    lgio 0, ADCMSK_DB

    swp charge_2, charge_2              ; put the FF to bits 23..16

    ; refresh ADCMSK, as it will be normally refreshed in the tracklet program
    ; not actually necessary for the test pattern program
    jmpr cc_busy, 0
    lpio GBUSR0, r1

    jmpr cc_busy, 0
    iext ADCMSK                         ; and write to the register
    sgio r1, ADCMSK                     ;
    #endif

    #ifeq TRACKLETS_MODE, TRACKLETS_TPT_MODE

    ; prepare the test pattern
    #ifdef cpu0

    jmpr cc_busy, 0
    lgio 0, EvtCtr_DB                   ; start reading the event counter
    jmpr cc_busy, 0
    lpio GBUSR0, r3                     ; Event Counter is in r3
    add r3, 1, r4
    iext EvtCtr_DB
    sgio r4, EvtCtr_DB                  ; update the event counter in DB

    ; scale_y contains the 3 thresholds
    mov scale_y, adc_ch_msk_0           ; CPU1 will use bits  9..0
    slr 10, scale_y, adc_ch_msk_1       ; bits 19..10
    slr 10, adc_ch_msk_1, adc_ch_msk_2  ; bits 29..20
    #else  ; 1, 2
    syn
    #endif

    mov TEST_PAT_MASK, r4
    and r4, scale_d, r5                 ; the n-bit number that will be used to generate the tracklets

    and r4, adc_ch_msk, r6              ; the n-bit threshold for 1,2,3 tracklet(s)

    cmp r5, r6                          ; the "random" number and the threshold
    jmp cc_geu, _acq_no_tr              ; skip the rest, in this case no tracklet will be send

    mov 0xF1, r7
    add r7, CPU_ID, r7                  ; this is charge_i

    #ifdef cpu0
    mov r7, charge_0
    #endif

    #ifdef cpu1
    sll 8, r7, charge_1
    #endif

    #ifdef cpu2
    swp r7, charge_2
    #endif

    ; < pad_position within the MCM (11 bit) | LPID (12 bit) | slope (8 bit) | 0 >
    mov 1, r7
    add r7, CPU_ID, r7
    sll 8, r7, r7                       ; this is the position of the tracklet: (CPU_ID+1)*256
    sll 10, r6, r6                      ; 20 bit LPID & slope are threshold << 10 | random
    or r6, r5, r6                       ; r6 is 20 bit
    sll 12, r7, r5                      ; LPID is 12 bit long
    sll 8, r5, r5                       ; slope is 8 bit long
    or r5, r6, r6

    sll 1, r6, trackl_i                 ; last bit is 0

    #endif    ; tp mode?
_acq_no_tr:
    sem b1000_0000                      ; will wait on writing to g7
    syn                                 ; wait until cpu3 writes to g7
#endif    ; 0,1,2


; now build the data to be send
#ifdef cpu0
    ; CPU0 sends the MCM tracklet header, if no tracklets only when enabled!
    ; build first ( ( (charge_2[19..12] << 8) | charge_1[19..12]) << 8 ) | charge_0[19..12]
    ; if 0xFFFFFF, then we don't have any tracklets
    ; in this case depending on DONT_SEND_EMPTY_HDR_TR load the end marker or continue with the header
    mov charge_2, r4                    ; charge_2 is HPID2 (FF 00 00 when no tracklets)
    or r4, charge_1, r4                 ; charge_1 is HPID1 (00 FF 00 when no tracklets)
    or r4, charge_0, r4                 ; charge_0 is HPID0 (00 00 FF when no tracklets)
    ; at this point all 3 charges (bits 19..12 of each charge word) are put together in bits 23..0
  #ifeq DONT_SEND_EMPTY_HDR_TR, 1
    iext 0xFFFFFF
    mov  0xFFFFFF, r5                   ; needed to compare with the HPID2..0

    cmp r4, r5                          ; and if the 24-bit word with HPIDs is 0xFFFFFF, we don't have
                                        ; to send anything except for end markers
    jmp cc_eq, _acq_wr_em2ni            ; jump to: write end marker only
  #endif

    lgio 0, H_PAD_ROW_COL_DB

    shl 1, r4, r6                       ; otherwise put one '0' at the right side (prepared in pad_row_col)

    jmpr cc_busy, 0
    lpio GBUSR0, r5

    or r6, r5, r6                       ; and add the position information, already prepared in boot program

    iext H_PAD_ROW_COL_DB
    sgio r5, H_PAD_ROW_COL_DB
    ; here CPU0 is ready

#endif

#ifdef cpu1                             ; send the tracklet of CPU0, if any, otherwise just end marker
    mov charge_0, r6
    cmp r6, 0xFF                        ; - test the same part =? 0xFF as used in the header
    jmp cc_eq, _acq_wr_em2ni            ; if = 0xFF we don't have a tracklet and write end marker
    mov trackl_0, r6                    ; load the 32-bit word to be send to r6
    xor r6, adc_ch_msk_3, r6            ; invert two bits in the tracklet, adc_ch_msk_3 initialised before by CPU3
#endif

#ifdef cpu2                             ; send the tracklet of CPU1, if any, otherwise just end marker
    slr 8, charge_1, r6                 ; HPID1 >> 8, so the 8 bits are at 7..0

    cmp r6, 0xFF                        ; test the same part =? 0xFF as used in the header
    jmp cc_eq, _acq_wr_em2ni            ; if = 0xFF we don't have a tracklet and write end marker
    mov trackl_1, r6                    ; load the 32-bit word to be send to r6
    xor r6, adc_ch_msk_3, r6            ; invert two bits in the tracklet, adc_ch_msk_3 initialised before by CPU3
#endif

#ifdef cpu3                             ; send the tracklet of CPU2, if any, otherwise just end marker
    slr 16, charge_2, r6                ; HPID2 >> 16, so the 8 bits are at 7..0

    cmp r6, 0xFF                        ; - test the same part =? 0xFF as used in the header
    jmp cc_eq, _acq_wr_em2ni            ; if = 0xFF we don't have a tracklet and write end marker
    mov trackl_2, r6                    ; load the 32-bit word to be send to r6
    xor r6, adc_ch_msk_3, r6            ; invert two bits in the tracklet, adc_ch_msk_3 initialised before by CPU3
#endif

    ; all CPUs send the prepared 32-bit word.
_acq_write2ni:
    spio r6, NODP
    sra r6, TrcklDMEMa                  ; store the tracklet in DMEM for debugging and as info for ZS readout
    jmp cc_uncond, clr_endloop

_acq_wr_em2ni:
    iext NSIG_TR_VAL
    mov  NSIG_TR_VAL, r6
    #ifdef cpu3                         ; cpu3 will refresh the NES register
    mova NSIG_RR_VAL, r2
    swp r2, r2
    or r6, r2, r1                       ; the full NES register has RR in bits 31..16 and TR in bits 15..0
    jmpr cc_busy, 0
    sgio r1, NES
    #endif
    jmp cc_uncond, _acq_write2ni