; $Id$:

acq_hcm_bm:
#ifndef cpu3     ; cpu0,1,2
    #ifdef cpu1
    ; prepare the BC counter, 15-bits
    lpio CTPDOUT, r0
    iext 0x7FFF
    mov  0x7FFF, r1
    and  r0, r1, g5
    #endif

    #ifdef cpu0
    sem b0000_0000_0000_0110            ; cpu0    will wait until cpu3 writes something to g1,2
                                        ; so it will start before cpu1,2
    #else
    sem b0000_0000_0000_0001            ; cpu1..2 will wait until cpu3 writes something to g0
    #endif
    syn                                 ; stop cpu0..2 until cpu3 is ready to save power
 #else      ; cpu3

    #ifeq DYN_L1A, 1                    ; dynamical control of the full readout
    lgio 1, CTGDOUT                     ; request reading of the global counter - special pulse for full readout
    mova SML2_VALnoA, r5                ; prepare to write the SML2, load it without L1A/R bit
    jmpr cc_busy, 0                     ; wait for the global bus
    lpio GBUSR1, r0                     ; get the global counter, requested before - was a special pulse for full readout?
    and r0, c1, r0                      ; we expect 0 or 1
    sll 14, r0, r0                      ; shift to position 14 -> ignore_L1R
    or r0, r5, r5                       ; merge with the SML2 value
    sgio r5, SML2                       ; write the complete SML2 with ignore_L1R set (when the counter=1 was) or cleared (when counter=0 was)
    mov 0, r0                           ; prepare to clear the counter
    jmpr cc_busy, 0
    sgio r0, CTGDINI                    ; clear the counter
    #endif
;_acq_mrg_no_reserv:
    ; CPU3 makes a refresh of several registers
    mvpcr +2, rstack                    ; the most important parameters in hcm bm
    jmp cc_uncond, load_direct_first_hcm_bm

    mvpcr +2, rstack
    jmp cc_uncond, load_patchm_par

    mvpcr +2, rstack                    ; the common parameters, to all MCMs
    jmp cc_uncond, load_direct_all

    jmpr cc_busy, 0
    lgio 0, h_0_DB                      ; read the h_0 from DBANK, bits 11..0 are (hc_0_SM_sector_nr <<  7) | (hc_0_plane_nr <<  4) | (hc_0_chamber_nr <<  1) | hc_0_side_chamber
                                        ; the upper bits define the HCM header in raw data readout: (hc_0_raw_ver_spec_nr << 29) | (hc_0_raw_ver_maj_nr << 22) | (hc_0_raw_ver_min_nr << 15) | (hc_0_add_hd_words << 12)
    jmpr cc_busy, 0
    lpio GBUSR0, r1

    #ifdef XOR_CONST_TO_HCID
      #ifeq XOR_CONST_TO_HCID, 0xFFF
        not r1, r1                      ; will be used by another CPU to prepare the header
      #else
      #ifneq XOR_CONST_TO_HCID, 0
        mov XOR_CONST_TO_HCID, r2
        xor r1, r2, r1
      #endif
      #endif
    #endif
    mov 0xFFF, r2
    and r2, r1, g1

    ;jmpr cc_busy, 0
    lgio 0, ChipPOS_DB                  ; read the ChipPos from the DBANK
    jmpr cc_busy, 0
    lpio GBUSR0, r9
    ;sgio r9, ChipPOS_ConIO              ; write to the constant 14, may ne not very needed
    mov r9, g2                          ; used by another CPU to prepare the header

    swp r9, r2                          ; readout flags in bits 19..16 => 3..0
    slr 2, r2, r2                       ; HCM flags in 0..1
    mvpcr +4, rstack                    ; rstack is r8
    andt r2, 3                          ; test if 00 (BM)
    jmp cc_zero, load_direct_bm_m       ; BM
    jmp cc_uncond, load_direct_hcm      ; HCM

    slr  16, r9, g0                     ; the flags are in the upper 16 bits, now in the lower 16 bits
#endif

#ifdef cpu0
    ; g1 is HCID in h_0 bits 11..0, eventually some bits inverted
    ; g2 is ChipPos, LATER: g0 is bits 31..16 of ChipPOS

    slr 10, g2, r3                      ; bits 23..20 contain the format
    slr 10, r3, r3                      ;
    sll 15, r3, r3                      ; make free space of 15-bits for the MCLK
    or r3, g5, r3                       ; g5 was prepared before by CPU1, the BC counter, running at 120 MHz
    sll 1, r3, r3                       ; one bit with const 1
    or r3, 1, r3                        ; set bit 0
    sll 12, r3, r3                      ; make free space for the HCID - 12 bits
    or r3, g1, g3                       ; the final header word in g3
    sem b0000_0000_0000_0001            ; cpu1..2 will wait until cpu3 writes something to g0
    syn
#endif

    ; load the end markers
    mova NSIG_TR_VAL, r6

    #ifdef cpu0
    ; some refresh here
    mov NIICE_VAL, r2
    jmpr cc_busy, 0
    sgio r2, NIICE

    mova NSIG_RR_VAL, r2
    swp r2, r2
    or r6, r2, r1       ; the full NES register has RR in bits 31..16 and TR in bits 15..0
    jmpr cc_busy, 0
    sgio r1, NES
    #endif

    ; g1 is h_0, g2 is ChipPos, g0 is ChipPos >> 16, g3 is the HCM header
    slr 2, g0, r13                      ; now the two bits indicating HCM are in 0 and 1
    jmp cc_carry, _acq_hcm_bm_nrm       ; when carry ERROR! this might be a normal MCM?

    ; refresh the interrupt vectors, this must be done by ALL CPUs!
    ; the interrupt vectors are independent and if omitting the ORGs, the start addresses for each CPU could be
    ; different!
    mvpcr +2, rstack
    jmp cc_uncond, load_irq_vec_hcm_bm

#ifdef cpu3
    andt r13, 3
    jmp cc_zero, _acq_hcm_bm_wr         ; when 0, this is a BM

    ; here prepare to send the HCM header in tracklet mode!
    mov g3, r6                          ; g3 is the MCM header prepared by CPU0
#endif

_acq_hcm_bm_wr:
    spio r6, NODP
    jmp cc_uncond, clr_endloop

_acq_hcm_bm_nrm:                        ; a normal MCM landed here? We trust to the ChipPOS read from DBANK and correct the IRQ addresses

    mvpcr +2, rstack                    ; load the normal interrupt vectors
    jmp cc_uncond, load_irq_vec

    jmpr cc_busy, 0                     ; finish the refresh for sure

    spio r6, NODP                       ; send the end marker loaded before
    jmp cc_uncond, clr_endloop          ; quit