; $Id$: #ifeq RAW_RDOUT_TP_TYPE, 1 #def TOGGLE_LSBITS=1; #else #ifeq RAW_RDOUT_TP_TYPE, 6 #def TOGGLE_LSBITS=1; #else #def TOGGLE_LSBITS=0; #endif #endif #REP Compiling Test Pattern Mode Raw Data Readout ; report invalid patterns 4,5,7 #ifeq RAW_RDOUT_TP_TYPE, 4 #ERR Unsupported test pattern mode 4! #endif #ifeq RAW_RDOUT_TP_TYPE, 5 #ERR Unsupported test pattern mode 5! #endif #ifeq RAW_RDOUT_TP_TYPE, 7 #ERR Unsupported test pattern mode 7! #endif #ifneq RAW_SCSN, RAW_SCSN_DIS mov AddrDMdata, r15 #endif #ifdef cpu0 spio r11, NODP ; NI transfer chip header, prepared before #ifneq RAW_SCSN, RAW_SCSN_DIS sra+ r11 ; and to DMEM if not disabled #endif #endif ; cpu0 ; prepare and send various test patterns in raw data readout ; only types 0, 1, 2, 3, 6 defined, 0 not recommended #ifeq RAW_RDOUT_TP_TYPE, 0 mov 0xFF, r9 #endif #ifeq RAW_RDOUT_TP_TYPE, 1 ; init the local counter mov b101001, r6 ; inc after read, 10 bit, psrg spio r6, CTPCTRL sll 7, 1, r6 ; 1000 0000b add r6, ChipPOS, r6 ; 1rrr mmmmb rrr ROB#, mmmm MCM# sll 2, r6, r6 ; 1r rrmm mm00b or r6, CPU_ID, r6 ; 1r rrmm mmccb cc CPU# spio r6, CTPDINI mov 0x3FF, r9 ; mask for 10 bit psrg #endif #ifgt RAW_RDOUT_TP_TYPE, 1 ; patterns 2,3,6 only ; h_0 contains: ; 5 bits 0..17 3 bits 0..5 3 bits 0..4 1 bit 0..1 ; (sector_nr << 7) | (plane_nr << 4) | (chamber_nr << 1) | side_chamber slr 1, h_0, r13 ; sector/plane/chamber in 11 bits ; (sector_nr << 6) | (plane_nr << 3) | chamber_nr mov 0x7FF, r3 ; load an 11 bit mask and r3, r13, r13 ; and clear the rest bits mov b100_1001, r3 add r3, r13, r13 ; add 1 to sector, plane and chamber to avoid 0000 mov ChipPos, r3 ; we use here: MCM_POS (0..15) | (board_no << 4) mov 0x7F, r7 ; load a 7-bit mask and r3, r7, r3 ; clear the rest bits sll 7, r13, r13 ; sector+1/plane+1/chamber+1 in 11 bits << 7 or r13, r3, r13 ; sector+1(5)/plane+1(3)/chamber+1(3)/rob(3)/mcm(4) : 11+7=18 bits sll 2, r13, r13 ; << 2 or r13, CPU_ID, r13 ; sector+1(5)/plane+1(3)/chamber+1(3)/rob(3)/mcm(4)/cpu(2) : 20 bits mov 0, r3 ; used in testpattern mode 2 as counter #endif ; patterns 2,3,6 only ; once for all 5 or 6 transmitted channels #ifeq TOGGLE_LSBITS, 1 mov RAW_END_BITS, r7 #endif #ifeq RAW_RDOUT_TP_TYPE, 0 mov EBR0, rio #endif mvpcr +2, rstack jmp cc_uncond, raw_ChTML #ifeq RAW_RDOUT_TP_TYPE, 0 mov EBR1, rio #endif mvpcr +2, rstack jmp cc_uncond, raw_ChTML #ifeq RAW_RDOUT_TP_TYPE, 0 mov EBR2, rio #endif mvpcr +2, rstack jmp cc_uncond, raw_ChTML #ifeq RAW_RDOUT_TP_TYPE, 0 mov EBR3, rio #endif mvpcr +2, rstack jmp cc_uncond, raw_ChTML #ifeq RAW_RDOUT_TP_TYPE, 0 mov EBR4, rio #endif mvpcr +2, rstack jmp cc_uncond, raw_ChTML #ifdef cpu3 #ifeq RAW_RDOUT_TP_TYPE, 0 mov EBR5, rio #endif mvpcr +2, rstack jmp cc_uncond, raw_ChTML #endif jmp cc_uncond, raw_end_ni_tmsn raw_ChTML: mov NSAMPLES, r1 ; init the loop counter raw_ChTML_loop: ; entry point for all kinds of test patterns! ; only test patterns 0, 1, 2, 3, 6 exist now ; ; type 0 uses the local I/O address initialized in r14 (rio) in the calling code ; modifies r14, r3, r5 #ifeq RAW_RDOUT_TP_TYPE, 0 ; (0x0800+i+0x40*cpu_ch) << 16 | 0rrr mmmm 0000 0ccc ; cpu_ch is from 0..4 (cpu0..2), from 0..5 (cpu3) ; rrr - ROB#, mmmm - MCM#, ccc - CPU#+1 ; r9 contains 0xFF and r9, ChipPOS, r3 ; for mode 0 sll 8, rio, r5 or r3, r5, r5 sll 8, r5, r5 or r5, CPU_ID, r5 add r5, 1, r5 add rio, 1, rio ; prepare for the next word #endif ; type 1 uses r7 for the two LSBits and the local counter as PSRGenerator ; modifies r3, r4, r5 #ifeq RAW_RDOUT_TP_TYPE, 1 ; ADCs replaced by 10 bit pseudorandom generator ; the pseudorandom data are generated so, that result=0 is impossible lpio CTPDOUT, r3 ; r9 contains 0x3FF and r3, r9, r3 sll 2, r3, r3 or r3, r7, r3 lpio CTPDOUT, r4 and r4, r9, r4 ; mask again sll 12, r4, r4 or r4, r3, r4 lpio CTPDOUT, r5 sll 11, r5, r5 ; here we don't need to mask, the higher bits flow away sll 11, r5, r5 ; here we don't need to mask, the higher bits flow away or r5, r4, r5 ; appand the middle "sample" #endif ; type 2 uses r13 initialized before and the event counter ; modifies r3, r5 #ifeq RAW_RDOUT_TP_TYPE, 2 sll 10, EventCounter, r5 sll 10, r5, r5 or r5, r13, r5 ; evncnt(6)/sector(5)/plane(3)/chamber(3)/rob(3)/mcm(4)/cpu(2) sll 6, r5, r5 add r3, 1, r3 ; counter++, for 1 CPU 6 bit counter is enough! or r5, r3, r5 ; ... counter(6) #endif #ifeq RAW_RDOUT_TP_TYPE, 3 sll 10, EventCounter, r5 sll 10, r5, r5 or r5, r13, r5 ; evncnt(12)/sector(5)/plane(3)/chamber(3)/rob(3)/mcm(4)/cpu(2) #endif #ifeq RAW_RDOUT_TP_TYPE, 6 ; r7 used for the two LSBits sll 10, EventCounter, r5 sll 10, r5, r5 or r5, r13, r5 ; evncnt(6)/sector(5)/plane(3)/chamber(3)/rob(3)/mcm(4)/cpu(2) sll 6, r5, r5 add r3, 1, r3 ; counter++, for 1 CPU 6 bit counter is enough! or r5, r3, r5 ; ... counter(6) sll 2, r5, r5 ; add the two LSB as in case of normal ADC data or r5, r7, r5 #endif ; this part needed always! spio r5, NODP ; write to NI #ifneq RAW_SCSN, RAW_SCSN_DIS sra+ r5 ; store the ADC data to DMEM, note that the pointer is initialized before! #endif sub r1, 3, r1 ; decrease the remaining number of samples to read by 3, as we send 3 samples at once jmp cc_gtu, raw_ChTML_loop ; close the loop ; no more data in this ADC channel #ifeq TOGGLE_LSBITS, 1 xor r7, 1, r7 ; toggle the LSB, prepare for the next channel, used only in TP1 and 6 #endif jmp cc_uncond, rstack ; return from subroutine