; $Id$: #REP Compiling Raw Data Readout in HCM/BM ; RAW data readout for HCM and BM only ; it is simple, BM doesn't send anything, HCM sends headers (1 in ACQ and up to 3 in RAW) ; already checked if normal MCM - not ; g0 contains the swapped ChipPos ; bits 3..0: hh mm - hh - set when HCM (1100), mm - set when normal MCM (0011) ; so when 00 00 - BM ; now check if BM or HCM raw_hcm_bm: slr 2, g0, r0 ; g0 contains in bits 3..2 the readout flags for HCM, now bits 1..0 are the readout flags andt r0, 3 ; test bits 1..0 jmp cc_zero, raw_bm ; when 0 => BM ; send the headers ;############################################## ;# HCM headers[0..3], stored always in DBANK for scsn readout ;############################################## ; CPU1,2,3 assist to CPU0 preparing the HCM headers #ifdef cpu1 ; read the BC counter, put the 16 LSBits to g5 lpio CTPDOUT, r0 swp r0, r0 ; the bits 15..0 are now in 31..16 slr 16, r0, g5 ; shifted to the right again to pos. 15..0, the upper 16 bits are now cleared! #ifdef OVERWR_UPPER_HC0 iext h_0_DB sgio r3, h_0_DB ; refresh the h_0 with upper bits (31..12) from the ASM constant H_0_CNF #endif ; iext 0xFFFF ; mov 0xFFFF, r1 ; and r0, r1, g5 ; some refresh mvpcr +2, rstack jmp cc_uncond, load_direct_first_hcm_bm #endif #ifdef cpu2 ; read the pretrigger phase, put the 4 LSBits to g6 lpio CTPDOUT, r0 mov 0xF, r1 and r0, r1, g6 ; some refresh mvpcr +2, rstack jmp cc_uncond, load_direct_all #endif #ifdef cpu3 ; read the pretrigger counter, put the 4 LSBits to g7 lpio CTPDOUT, r0 mov 0xF, r1 and r0, r1, g7 ; some refresh mvpcr +2, rstack jmp cc_uncond, load_direct_hcm ; HCM #endif #ifdef cpu0 iext DBANK_ADDR_HC_HDR mov DBANK_ADDR_HC_HDR, rio ; the HC headers are stored always in DBANK, as DMEM is not garanteed to be ok sll 2, h_0, r0 ; the header itself is in bits 30..2 or r0, 1, r4 ; last two bits "01" #ifdef ConfigEvent mov EventCounter, r0 #ifdef ConfEvMask mova ConfEvMask, r1 and r0, r1, r0 #endif cmp r0, ConfigEvent jmp cc_neq, raw_hc0_cont ; skip the header modification sll 15, r4, r4 slr 15, r4, r4 ; now the upper 15 bits are cleared ; iext 0x1FFFF ; mov 0x1FFFF, r2 ; 17 bits mask, bits 0..16 should remain unchanged, the upper cleared... ; and r2, r4, r4 ; clear the upper 15 bits in h[0], prepared in r4 iext 0xC700 mov 0xC700, r0 ; MSBit=1, TP=1, pattern=7, min ver. 0, the LSBit here must be 0 as it belongs to another field in the header! swp r0, r0 ; now we have 0xC700 0000 or r0, r4, r4 ; new header, TP=1, pattern=7, min ver. 0, the rest bits 16..0 are unchanged raw_hc0_cont: #endif sgio+ r4 ; store in DBANK for debugging or SCSN readout ; r4 contains the h[0], postpone sending, WHY? ; now prepare h[1]: mov NSAMPLES, r0 ; h[1] = nsamples << 26 | BC << 10 | PreCnt << 6 | PrePhase swp r0, r0 ; nsamples << 16, shift left has max distance 15! or r0, g5, r0 ; timebins & BC(16 bits), g5 contains BC cnt sll 4, r0, r0 or r0, g7, r0 ; timebins & BC & pre_cnt(4bits), g7 contains the pretrigger cnt sll 4, r0, r0 or r0, g6, r0 ; timebins & BC & pre_cnt(4bits) & pre_phase(4bits), g6 contains the pretr. phase sll 2, r0, r5 ; originally was 10 at the end of the comment, in code was 01. 10 makes more sense? or r5, c1, r5 ; timebins & BC & pre_cnt(4bits) & pre_phase(4bits) & "01" sgio+ r5 ; store h[1] in DBANK ; SVN revisions header h[3] = svn_rev_fitred << 19 | svn_rev_asm << 6 | 11 0001 iext FIT_SVN_REV mov FIT_SVN_REV, r0 sll 13, r0, r0 iext ASM_SVN_REV mov ASM_SVN_REV, r1 or r0, r1, r0 sll 6, r0, r0 mov b11_0101, r1 or r0, r1, r6 sgio+ r6 ; h[3] ready, store to DBANK for SCSN readout and debugging ; h[0] is in r4 ; h[1] is in r5 ; h[3] is in r6 ; now wait until CPU0 of the first MCM with ADC data has stored all in FIFO (WHY was this important?) ; delay_hcm was NOT defined may be? But it was 350, this means delay about 110 us, this is a lot! #ifdef delay_hcm mov delay_hcm, r0 sub r0, c1, r0 jmpr cc_nzero, -1 #endif ; slr 12, h_0, r0 ; the number of add. header words, 3 bits, but we use only 2 bits, from 0 to 3 mov HC_0_ADD_HD_WORDS, r0 ; load it directly from the ASM constant spio r4, NODP ; NI transfer header h[0] and r0, c3, r1 ; implemented are only h[1] and h[3]. We can make the 3 bits as mask? jmp cc_zero, raw_no_add_header spio r5, NODP ; NI transfer header h[1] cmp r1, 2 jmp cc_ltu, raw_no_add_header spio r6, NODP ; NI transfer header h[3] #endif ; cpu0 raw_no_add_header: #ifdef cpu3 ; now increment the event counter in DBANK jmpr cc_busy, 0 lgio 0, EvtCtr_DB jmpr cc_busy, 0 lpio GBUSR0, r0 add r0, c1, r0 iext EvtCtr_DB sgio r0, EvtCtr_DB #endif ; IRQ vector refresh, must be done by ALL CPUs, as each CPU has its own IRQ addresses! mvpcr +2, rstack jmp cc_uncond, load_irq_vec_hcm_bm raw_exit: mov NSIG_RR_VAL, r0 ; load the endmaker rr, <= 12 bits spio r0, NODP mov 0, r0 jmpr cc_busy, 0 sgio r0, clk_onoff jmp cc_uncond, clr_endloop raw_bm: ; configuration refresh #ifdef cpu0 mvpcr +2, rstack jmp cc_uncond, load_direct_first_hcm_bm #endif #ifdef cpu1 ; mvpcr +2, rstack ; jmp cc_uncond, load_direct_all nop #endif #ifdef cpu2 mvpcr +2, rstack jmp cc_uncond, load_direct_bm_m ; HCM #endif #ifdef cpu3 nop #endif jmp cc_uncond, raw_no_add_header nop