; $Id$: ; ; this is include file for the main fit program ; integrate in a window defined as constants Q2_LEFT_MRG and Q2_WIN_WIDTH_VAL (2..9) ; read from the event buffer, accumulate and store to RAM ; it takes (2*WIDTH+9)*Nch+10 CPU Clocks, for CPU0..2 from about 10 to about 55+10*WIDTH, for CPU3 from about 10 to about 64+12*WIDTH ; this means, depending on the distribution of the marked channels, the CPUs will need very different number of clocks to finish this part! Not good! ; inputs: r1 contains EBR0+Q2_LEFT_MRG ; r15 contains the start address in RAM to store the sums (with offest +ch) ; adc_ch_msk_3 is g7 and contains the ADC mask with the channels, used in the tracklets ; ; constants used: ; EBR_CH_INI is the start channel # for each CPU: 0, 5, 10, 15 ; EBR_CH_MSK contains 1 1111 for CPU0..2 and 11 1111 for CPU3 ; Q2_WIN_WIDTH_VAL contains the width of the window ; ; modified: almost all reg, except for r12 and r13 ; no global regs modified ; no constants modified ; move before the syn ; mov 0x40, r2 ; the increment in the event buffer, 64 samples/channel ; sub r15, c4, r15 ; r15-=4, as the loop begins with increment, 4 as we have 4 bytes/dword ; mov EBR_CH_MSK, r4 ; 0..4 or 5 bit set, rest 0 slr EBR_CH_INI, adc_ch_msk_3, r0 ; shift logical right the mask, the distance is for cpu0,1,2,3 : 0, 5, 10, 15 ; r0 contains now in bits 0..4 (cpu0..2) and 0..5 (cpu3) the mask with the channels to be integrated and r4, r0, r0 ; clear the other bits ; here: r1 is the start address in LIO to read the ADC samples, already at the beginning of the integration window ; r1 will be copied to r14 for read with address autoincrement ; r2 contains 0x40, used as increment of r1 when going to the next channel ; r0 contains in bits 4..0 (cpu0..2) and 5..0 the channels marked for integration (local counting) ; now loop until all bits in mask in r0 becomes 0 jmp cc_zero, _acq_no_intgr ; skip the (rest of the) charge integration of Q2 when no bits set more _acq_intgr_loop: add r15, c4, r15 ; r15+=4, the address in DMEM where to store the result of the integration mov r1, rio ; the start address in LIO of the event buffer with offset - the left margin add r1, r2, r1 ; += 0x40 : the next start address of the next channel slr 1, r0, r0 ; shift right, bit 0 is now in carry jmp cc_ncarry, _acq_intgr_loop ; bit 0 was 0 - this channel will be not integrated, go to the next #iflt Q2_WIN_WIDTH_VAL, 2 #err Unsupported width of the third charge integration window < 2! #endif ; here we can use all registers r3..r11 for temp results, r12/r13 initialised and needed by cpu0..2, but cpu3 can use them? ; the result is always in r11 ; 2 #ifeq Q2_WIN_WIDTH_VAL, 2 lpio+ r3 ; read twice because of pipelining lpio+ r3 lpio+ r4 add r3, r4, r11 ; r11 is the result #endif ; 3 #ifeq Q2_WIN_WIDTH_VAL, 3 lpio+ r3 ; read twice because of pipelining lpio+ r3 lpio+ r4 lpio+ r5 add r3, r4, r4 add r4, r5, r11 ; r11 is the result #endif ; 4 #ifeq Q2_WIN_WIDTH_VAL, 4 lpio+ r3 ; read twice because of pipelining lpio+ r3 lpio+ r4 lpio+ r5 lpio+ r6 add r3, r4, r4 add r4, r5, r5 add r5, r6, r11 ; r11 is the result #endif ; 5 #ifeq Q2_WIN_WIDTH_VAL, 5 lpio+ r3 ; read twice because of pipelining lpio+ r3 lpio+ r4 lpio+ r5 lpio+ r6 lpio+ r7 add r3, r4, r4 add r4, r5, r5 add r5, r6, r6 add r6, r7, r11 ; r11 is the result #endif ; 6 #ifeq Q2_WIN_WIDTH_VAL, 6 lpio+ r3 ; read twice because of pipelining lpio+ r3 lpio+ r4 lpio+ r5 lpio+ r6 lpio+ r7 lpio+ r8 add r3, r4, r4 add r4, r5, r5 add r5, r6, r6 add r6, r7, r7 add r7, r8, r11 ; r11 is the result #endif ; 7 #ifeq Q2_WIN_WIDTH_VAL, 7 lpio+ r3 ; read twice because of pipelining lpio+ r3 lpio+ r4 lpio+ r5 lpio+ r6 lpio+ r7 lpio+ r8 lpio+ r9 add r3, r4, r4 add r4, r5, r5 add r5, r6, r6 add r6, r7, r7 add r7, r8, r8 add r8, r9, r11 ; r11 is the result #endif ; 8 #ifeq Q2_WIN_WIDTH_VAL, 8 lpio+ r3 ; read twice because of pipelining lpio+ r3 lpio+ r4 lpio+ r5 lpio+ r6 lpio+ r7 lpio+ r8 lpio+ r9 lpio+ r10 add r3, r4, r4 add r4, r5, r5 add r5, r6, r6 add r6, r7, r7 add r7, r8, r8 add r8, r9, r9 add r9, r10, r11 ; r11 is the result #endif ; 9, when more are clipped to 9 #ifeq Q2_WIN_WIDTH_VAL, 9 lpio+ r3 ; read twice because of pipelining lpio+ r3 lpio+ r4 lpio+ r5 lpio+ r6 lpio+ r7 lpio+ r8 lpio+ r9 lpio+ r10 lpio+ r11 add r3, r4, r4 add r4, r5, r5 add r5, r6, r6 add r6, r7, r7 add r7, r8, r8 add r8, r9, r9 add r9, r10, r10 add r10, r11, r11 ; r11 is the result #endif #ifgt Q2_WIN_WIDTH_VAL, 9 #err Unsupported width of the third charge integration window > 9! #endif sra r11, r15 ; store the result in RAM _acq_no_intgr: cmp r0, 0 ; check if the mask with the still remaining channels is 0 jmp cc_nzero _acq_intgr_loop ; not finished with the charged integration => loop again