;   #def EBI_CP0            = 0x0160        ; event buffer indicators for the channels accessible by CPU0
;   #def EBI_CP1            = 0x0174        ; event buffer indicators for the channels accessible by CPU0
;   #def EBI_CP2            = 0x0188        ; event buffer indicators for the channels accessible by CPU0
;   #def EBI_CP3            = 0x019C        ; event buffer indicators for the channels accessible by CPU0

; the part of main program, using the include file is below:

_acq_cp_ebi:

        ; copy the event buffer indicators to RAM, start address specified by the constant EBI_CP or by some initialisation of r15
        mov EBI_CP, r15                     ; where to copy in RAM, the start address depends on the CPU# and is defined

        ; input: r15 contains the start address in RAM
        ; modified registers: r1, r14
        ; output: stored in RAM
        #inc "fit_cp_eb_ind.asm"



        ; at this point cpu0 is first, 1..2 are about 10 clocks later and almost synchronous, cpu3 has a delay of 10+10+4 clocks
        ; cpu0..2 have about 40 clocks more than before?

        ; now we can check if adc_ch_msk3 is 0, in this case we don't have any tracklets and should exit

        shlt 0, adc_ch_msk3                 ; if no channels are marked, then no
        jmp cc_zero, acq_no_tr              ; check here if this exit point is ok for the delayed timing!!!

        ; here we have at least one tracklet, this means all CPUs have to integrate the ADC data in the third Q window
        ; the marked channels are in adc_ch_msk3


; now is cut from the main program!



; this is include file for the main fit program

        ; read the event buffer indicators (EBI) and store them into RAM, each CPU can read only its own ADC channels!

        ; input: r15 contains the start address in RAM
        ; modified registers: r1, r14
        ; output: stored in RAM

    ;#ifeq RUN_MODE, RUN_CALC_QCH0_QCH1
        ; all CPUs copy the event buffer indicators to RAM
        mov EBI0, rio                       ; cpu0..2 have 5 channels, cpu3 has 6 channels to read, each channel has 2 x 32 bit words
                                            ; we need only the first word for timebins 0..31
        ; + 2 clocks to prepare the loop

        ; own channel 0
        lpio+ r1                            ; reading here is pipelined
        lpio+ r1                            ; and we want to read only at the even offsets
        sra+ r1                             ; write to RAM with address++

        ; own channel 1
        lpio+ r1                            ; reading here is pipelined
        lpio+ r1                            ; and we want to read only at the even offsets
        sra+ r1                             ; write to RAM with address++

        ; own channel 2
        lpio+ r1                            ; reading here is pipelined
        lpio+ r1                            ; and we want to read only at the even offsets
        sra+ r1                             ; write to RAM with address++

        ; own channel 3
        lpio+ r1                            ; reading here is pipelined
        lpio+ r1                            ; and we want to read only at the even offsets
        sra+ r1                             ; write to RAM with address++

        ; own channel 4
        lpio+ r1                            ; reading here is pipelined
        lpio+ r1                            ; and we want to read only at the even offsets
        sra+ r1                             ; write to RAM with address++
        ; up to here 19 clocks, with loop was about 35

        #ifdef cpu3
        ; own channel 5 - only cpu3
        lpio+ r1                            ; reading here is pipelined
        lpio+ r1                            ; and we want to read only at the even offsets
        sra+ r1                             ; write to RAM with address++
        ; up to here 23 clocks (cpu3 only), with loop was about 42
        #endif





        ;   in RAM at address EBI_CP0 an array with the event buffer indicators of all channels


        ; cpu3 will OR the EBI (event buffer indicators) for each tracklet and will count the 1s in the charge windows Q0 and Q1