; $Id$: ; -------------------- ; Ressources in TRAP: const registers, DBANK and DMEM ; -------------------- ; -------------------- ; Constants - better avoid using them for constants, as they are not hamming protected! ; the table is may be not up to date! ; -------------------- ; CPU0 ; 8 : the start address in GIO of the packed configuration, used in unpack ; 9 : counter for L0A without tracklet, CPU0 ; 10 : - ; 11 : temporary store pad_row_n for verification ; -------------------- ; CPU1 ; 8 : HCM only, used to detect the first irq_clr ; 9 : counter for L0A without tracklet, CPU1 ; 10 : - ; 11 : temporary store yoffs for verification ; -------------------- ; CPU2 ; 8 : - ; 9 : counter for L0A without tracklet, CPU2 ; 10 : - ; 11 : temporary store scale_y for verification ; -------------------- ; CPU3 ; 8 : programmable network interface readout delay ; 9 : counter for L0A without tracklet, CPU3 ; 10 : for cosmic trigger: contains the thresholds ; 11 : temporary used to store scale_d ; -------------------- ; CPU-all ; 12 : event counter, incremented by CPU3 after raw data readout ; 13 : number of samples, used for raw data readout ; 14 : Chip Position for MCM Header (bits 0..6) and readout flags (bits 16..) ; 15 : half-chamber header 0 ; Constant & Regs #def EvtCtr_ConIO = C12CPUA ; Address of Event Counter in GIO, temporary used only! #def ChipPOS_ConIO = C14CPUA ; Chip Position for Header: the address of c14 in IO #def h_0_ConIO = C15CPUA ; half-chamber header 0 in DBANK #ifdef cpu0 #def clk_onoff = CPU0SS ; own clock #def IA_CLR = 0xB00; #def IA_TST = 0xB01; #def IA_ACQ = 0xB02; #def IA_RAW = 0xB04; #def TPCI = TPCI0 ; #endif #ifdef cpu1 #def clk_onoff = CPU1SS ; own clock #def IA_CLR = 0xB20; #def IA_TST = 0xB21; #def IA_ACQ = 0xB22; #def IA_RAW = 0xB24; #def TPCI = TPCI1 ; #endif #ifdef cpu2 #def clk_onoff = CPU2SS ; own clock #def IA_CLR = 0xB40; #def IA_TST = 0xB41; #def IA_ACQ = 0xB42; #def IA_RAW = 0xB44; #def TPCI = TPCI2 ; #endif #ifdef cpu3 #def clk_onoff = CPU3SS ; own clock ; 0 clr, 1 tst, 2 acq, 3 err, 4 raw #def IA_CLR = 0xB60; #def IA_TST = 0xB61; #def IA_ACQ = 0xB62; #def IA_RAW = 0xB64; #def TPCI = TPCI3 ; used in cosmic mode #endif ; -------------------- ; DBANK ; -------------------- ; Address Used for ; ; 0xF000..0xF0DF packed configuration, used for refreshing, probably will be not used so any more! ; 0xF0E0..0xF0FF packed configuration and single GIO instructions used for init, can be destroyed later, but ; probably will be not used so! ; 0xF0E0..0xF0FF MCM3,7,11,15: mailbox, used for service routines, like i2c, j2c and more ; these functions are used in special configurations only, not together with normal runs! ; 0xF0F0..0xF0F3 HCM only: headers for SCSN readout ; 0xF0F4..0xF0F7 Important constants, former C12..15 #ifdef cpu0 #def AddrSCdata = 0xF000 ; Address in GIO to store the ADC data for SCSN readout #def lpcount0 = 0xF0E8 ; counts the number of starts at address 0 #def lpcount1 = 0xF0E9 ; counts the number of starts at address 0xFFE #endif #ifdef cpu1 #def AddrSCdata = 0xF040 ; Address in GIO to store the ADC data for SCSN readout #def lpcount0 = 0xF0EA ; counts the number of starts at address 0 #def lpcount1 = 0xF0EB ; counts the number of starts at address 0xFFE #endif #ifdef cpu2 #def AddrSCdata = 0xF080 ; Address in GIO to store the ADC data for SCSN readout #def lpcount0 = 0xF0EC ; counts the number of starts at address 0 #def lpcount1 = 0xF0ED ; counts the number of starts at address 0xFFE #endif #ifdef cpu3 #def AddrSCdata = 0xF0C0 ; Address in GIO to store the ADC data for SCSN readout #def lpcount0 = 0xF0EE ; counts the number of starts at address 0 #def lpcount1 = 0xF0EF ; counts the number of starts at address 0xFFE #endif ; for I2C and JTAG, only ROB3B, MCM 7? #def srv_command = 0xF0E0 ; probably will be not supported in the new version #def srv_indata = 0xF0E1 ; and the old proven configurations will be used #def srv_outdata = 0xF0F0 ; for ORI programming ; HCM only #def DBANK_ADDR_HC_HDR = 0xF0F0 ; up to 4 header words, used for scsn readout or debugging ; all MCMs, but may be will be not used to fill the 4 common CPU constants ; #def DBANK_ADDR_CONST = 0xF0F4 ; Const 12..15 prime source location ; #def EvtCtr_DB = 0xF0F4 ; Address of Event Counter in DBANK, c12 before ; #def ChipPOS_DB = 0xF0F6 ; Chip Position for Header in DBANK, c14 before ; #def h_0_DB = 0xF0F7 ; half-chamber header 0 in DBANK, c15 before ; #def SMMODE_DB = 0xF0F8 ; the config register SMMODE ; #def NTRO_DB = 0xF0F9 ; the config register NTRO ; #def NRRO_DB = 0xF0FA ; the config register NRRO ; #def NED_DB = 0xF0FB ; the config register NED ; #def NDLY_DB = 0xF0FC ; the config register NDLY ; LP_REP+cpu# is used to report the event# where the CPU went to LP #def LP_REP = 0xF0E4 ; #def DBANKscsn = 1 ; store the ADC data to DBANK for scsn readout ; otherwise use the DMEM ; #def TPLm2 = 0x31FE; ; DMEM (without BM/HCM chips) ; ; ; byte addresses in DMEM here, as used by the CPUs #def IdN_TABL_DM = 0x000 ; from 0 to 31*4: 2**31/N, do we need it still? ; #def DEFL_RNG_T_DM= 0x080 ; ; #def POS_LUT_DM = 0x120 ; position LUT, 22 x 6 x 5 bits (128 enties), beginning of the first 1/3 ; #def POS_LUT_DM_E = 0x174 ; the last address of the position LUT, used for the last 2 entries + flags + refresh counter ; #def ADCMSK_DM = 0x180 ; ; #def SCALE_Y_DM = 0x184 ; ; #def SCALE_D_DM = 0x188 ; ; #def SCALE_Q_DM = 0x18C ; ; #def DEFL_CR_DM = 0x190 ; ; #def ZS_SMSK_DM = 0x1A0 ; address of the sample mask (64 bit) ; #def ZS_ADC_ORM_DM= 0x1A8 ; address of the ADC OR mask (21 bit) ; here come may be other parameters! ; working and output data: ; ADC statistics will be used only in special cases ; #def AddrDMstat_DM= 0x200 ; .. 0x2FB, all channels statistics (sum ADC (32-bit), ; #def AddrDMstat_0 = 0x200 ; sum ADC**2, (2 dwords/channel) ; #def AddrDMstat_1 = 0x23C ; ; #def AddrDMstat_2 = 0x278 ; ; #def AddrDMstat_3 = 0x2B4 ; .. 0x2FB ; Note: the pad_row can be calculated from the ROB# and MCM# as: ; pad_row = ((ROB# >> 1) << 2) | (MCM# >> 2) ; MCM# = c14 & 0xF ; ROB# = (c14 >> 4) & 0x07 #def H_PAD_ROW_COL_DM = 0x2FC; pad row & column, prepared in the boot.asm #def TrcklDMEMa_0 = 0x300 ; store the tracklet for scsn readout #def TrcklDMEMa_1 = 0x304 ; and for ZS readout #def TrcklDMEMa_2 = 0x308 ; #def TrcklDMEMa_3 = 0x30C ; #def FIT2DM_DM = 0x310 ; start address to store the fitregister in DMEM, each ; CPU needs 16 regs * 4 bytes, the last address is 0x40F #def AddrDMdata_0 = 0xC00 ; Address in DM to store the ADC data for SCSN readout #def AddrDMdata_1 = 0xD00 ; #def AddrDMdata_2 = 0xE00 ; #def AddrDMdata_3 = 0xF00 ; ; Address in DM to store the integrated ADC data, one word per channel #def ADC_Q2_0_4 = 0x410 ; CPU0, ch 0..4 #def ADC_Q2_5_9 = 0x424 ; CPU1, ch 5..9 #def ADC_Q2_10_14 = 0x438 ; CPU2, ch 10..14 #def ADC_Q2_15_20 = 0x44C ; CPU3, ch 15..20 ; only in ZS with >30 samples: #def ZSL_SMSK0 = 0x4B0 ; channel 0..4, copy of EBI and ZS_SMSK, 64 bit => 2 dwords/channel #def ZSL_SMSK1 = 0x4D8 ; channel 5..9, copy of EBI and ZS_SMSK, 64 bit => 2 dwords/channel #def ZSL_SMSK2 = 0x500 ; channel 10..14, copy of EBI and ZS_SMSK, 64 bit => 2 dwords/channel #def ZSL_SMSK3 = 0x528 ; channel 15..20, copy of EBI and ZS_SMSK, 64 bit => 2 dwords/channel ; 21 channels * 2 => 42 ; ... next free address is 0x558 ; Gain Table with Factors, 7 x 3 x 9-bit, 1 empty word ; Gain Table with Additives, 5 x 5 x 6-bit ; ... next free address is 0x4A4 #ifdef cpu0 #def AddrDMdata = AddrDMdata_0 ; Address in DM to store the ADC data for SCSN readout #def ADC_Q2 = ADC_Q2_0_4 ; Address in DM to store the integrated ADC data of ch 0..4, one word per channel #def AddrDMstat = AddrDMstat_0 ; Address in DM to store the ADC statistics #def TrcklDMEMa = TrcklDMEMa_0 ; store the tracklet word sent for scsn readout #def TrcklDMEMz = TrcklDMEMa_1 ; read the own tracklet in ZS (was sent by CPU1) #def ZSL_SMSK_C = ZSL_SMSK0 ; sample mask AND-ed with ZS_SMSK, 64-bit/channel #endif #ifdef cpu1 #def AddrDMdata = AddrDMdata_1 ; Address in DM to store the ADC data for SCSN readout #def ADC_Q2 = ADC_Q2_5_9 ; Address in DM to store the integrated ADC data of ch 5..9, one word per channel #def AddrDMstat = AddrDMstat_1 ; Address in DM to store the ADC statistics #def TrcklDMEMa = TrcklDMEMa_1 ; store the tracklet word sent for scsn readout #def TrcklDMEMz = TrcklDMEMa_2 ; read the own tracklet in ZS (was sent by CPU2) #def ZSL_SMSK_C = ZSL_SMSK1 ; sample mask AND-ed with ZS_SMSK, 64-bit/channel #endif #ifdef cpu2 #def AddrDMdata = AddrDMdata_2 ; Address in DM to store the ADC data for SCSN readout #def ADC_Q2 = ADC_Q2_10_14 ; Address in DM to store the integrated ADC data of ch 10..14, one word per channel #def AddrDMstat = AddrDMstat_2 ; Address in DM to store the ADC statistics #def TrcklDMEMa = TrcklDMEMa_2 ; store the tracklet word sent for scsn readout #def TrcklDMEMz = TrcklDMEMa_3 ; read the own tracklet in ZS (was sent by CPU3) #def ZSL_SMSK_C = ZSL_SMSK2 ; sample mask AND-ed with ZS_SMSK, 64-bit/channel #endif #ifdef cpu3 #def AddrDMdata = AddrDMdata_3 ; Address in DM to store the ADC data for SCSN readout #def ADC_Q2 = ADC_Q2_15_20 ; Address in DM to store the integrated ADC data of ch 15..20, one word per channel #def AddrDMstat = AddrDMstat_3 ; Address in DM to store the ADC statistics #def TrcklDMEMa = TrcklDMEMa_3 ; store the tracklet word sent for scsn readout #def ZSL_SMSK_C = ZSL_SMSK3 ; sample mask AND-ed with ZS_SMSK, 64-bit/channel #def AddrDM_Cos = ADC_Q2_0_4 ; to store debug info in cosmic mode, only by CPU3 #endif