simdelay = 15;
write chip_mode, SEBDOU, mode_jtag;

// Activate the IRQ TST with the J2C function
write chip_jtag,      IA0+IRQ_TST, lbl_TST_cpu0;   // set int_clr start addr for cpu0

cmd = 1001b;            // write at address 1
data = reg5 & 0xFD;     // single bits, turning off the analog power on ORI
write chip_jtag,      srv_command, cmd | (data << 4);
expect chip_jtag,      srv_command, cmd | (data << 4);
write chip_jtag,      SMCMD, CMD_CHK_TST;     // start
wait simdelay
expect chip_jtag,      SMCMD, 0

cmd = 1000b;            // write at address 0
data = reg4;            // sel_p/s
write chip_jtag,      srv_command, cmd | (data << 4);
expect chip_jtag,      srv_command, cmd | (data << 4);
write chip_jtag,      SMCMD, CMD_CHK_TST;     // start
wait simdelay
expect chip_jtag,      SMCMD, 0

wait 1000000

cmd = 1001b;            // write at address 1
data = reg5;            // single bits, see the file parameters.tcs
write chip_jtag,      srv_command, cmd | (data << 4);
expect chip_jtag,      srv_command, cmd | (data << 4);
write chip_jtag,      SMCMD, CMD_CHK_TST;     // start
wait simdelay
expect chip_jtag,      SMCMD, 0

cmd = 0000b;            // read at address 0
write chip_jtag,      srv_command, cmd;      // read 0
expect chip_jtag,      srv_command, cmd;
write chip_jtag,      SMCMD, CMD_CHK_TST;     // start
wait simdelay
expect chip_jtag,      SMCMD, 0
expect chip_jtag,      srv_outdata, 0x00

cmd = 0100b;            // read at address 4
write chip_jtag,      srv_command, cmd;      // read 1
expect chip_jtag,      srv_command, cmd;
write chip_jtag, srv_outdata, 0xBADAFFE
write chip_jtag,      SMCMD, CMD_CHK_TST;     // start
wait simdelay
expect chip_jtag,      SMCMD, 0
expect chip_jtag,      srv_outdata, reg4

cmd = 0101b;            // read at address 5
write chip_jtag,      srv_command, cmd;      // read 1
expect chip_jtag,      srv_command, cmd;
write chip_jtag, srv_outdata, 0xBADAFFE
write chip_jtag,      SMCMD, CMD_CHK_TST;     // start
wait simdelay
expect chip_jtag,      SMCMD, 0
expect chip_jtag,      srv_outdata, reg5

//write                  IA0+IRQ_TST, lbl_LPW_cpu0;
write chip_jtag, IA0+IRQ_TST, lbl_LPW_cpu0;
restrict 1