/**************************************/
/* ALICE TRD                          */
/* Read-out board                     */
/* SCSN Configuration File            */
/*                                    */
/* 2004-03-08                         */
/* Jan de Cuveland, Venelin Angelov   */
/**************************************/

// ----------------------------
//  define SCSN IDs for ring 0
// ----------------------------
include src/scsn_ids.tcs

// TRAP definitions
include src/defines.tcs

restrict 1-SIMULATION
// optional for simulation
include src/TRAP_EB_init.tcs
// optional for simulation
include src/position.tcs
restrict 1

include dat/cpu0_labels.tcs
include dat/cpu1_labels.tcs
include dat/cpu2_labels.tcs
include dat/cpu3_labels.tcs

include src/parameters.tcs

include src/filter.tcs
//include src/FILTERCFG/filter_P.tcs

include src/main.tcs

include src/1divN.tcs

// reset ORI again
write chip_mode, SEBDOU, mode_rstn;
write chip_mode, SEBDOU, mode_jtag;

restrict USE_J2C
include src/j2c_init.tcs
restrict 1

pretrigger 5

restrict PASAPULSE
//////// Some shift
write PASAPRA, 0x30; // min: 0x00, max: 0x3F
write PASAPHA, 9
write PASADAC, 0x0FF
//write PASACHM, 0x55555
//write PASACHM, 0xAAAAA
//write chip2, PASACHM, (1 << 10)
write PASACHM, (1 << 3) | (1 << 7) | (1 << 11) | (1 << 15)
//write PASACHM, 0
write PASAPR1, 0
// start once
write PASAPR1, 1
wait 100
// clear
pretrigger 2
write PASAPR1, 0
write PASAPR1, 1
wait 100
write PASAPR1, 0
// clear
pretrigger 2
write           C12CPUA,10; // the counting starts from 10 ???
// In PASA Pulse mode the pretrigger counters in chips can not start siumultaneously because
// they will be first synchronized with the slow clock
// Note that in the normal pretrigger mode this is not the case!
// So, only in case of PASA Pulse we need the NI control signals permanently enabled.
// This leads to about 140 mA more /ROB.
write chip_hm,  NIOCE,  0x01;
write chip_bm,  NIOCE,  0x01;

write chip_bm,  NIICE,  0x01;
write chip_hm,  NIICE,  0x01;

write chip2  ,  NIICE,  0x01;
write chip6  ,  NIICE,  0x01;
write chip10 ,  NIICE,  0x01;
write chip14 ,  NIICE,  0x01;
write chip2  ,  NIOCE,  0x01;
write chip6  ,  NIOCE,  0x01;
write chip10 ,  NIOCE,  0x01;
write chip14 ,  NIOCE,  0x01;

restrict 1;