\chapter{Filter and Preprocessor}
\label{tpp}

\begin{figure}[htb]
  \centering
  \includegraphics*[width=15cm]{chap_tpp/TRAP3-TPP.eps}
  \caption[Location of Filter and Preprocessor]{\label{fig:TRAP3-TPP}Location of Filter and
  Preprocessor within the data stream}
  
\end{figure}

%-----------------------------------------------------------------------------
\section{Common Cotrol}
\label{tpp:common}

Data preprocessing (see \ref{tpp:pre}) and storage refer to a common time
reference. It is defined by the pretrigger signal which causes the GSM
(see \ref{sm}) to start the timing environment ($t_{Timer}$).

\begin{figure}[htb]
  \centering
  \includegraphics*[width=14cm]{chap_tpp/TRAP3-Bin-Timer.eps}
  \caption[Common Timing Control Unit]{\label{fig:TRAP3-Bin-Timer}Common Timing Control Unit}
  
\end{figure}

The timer $t_{Timer}$ runs at 10MHz up to the value of 127 and stops there. It
can be cleared by the GSM.

The time reference $t$ is defined by the delayed timer value:

\begin{equation}
  t =  \biggl\{
       \begin{array}{ll}
         t_{Timer} - t_0 & \textnormal{for } t_{Timer} \geq t_0 \\
	 0               & \textnormal{otherwise}
       \end{array}
\end{equation}

\register{TPPT0}{0x3000}{Common Timer Delay}
{
$ = t_0$, delay between timer and common preprocessing and storage time.
Measured in terms of 100ns.\\
This value also indicates the start of data storage within thew event buffer.\\
If the value 0 is chosen, the first time bin in the event buffer is being
overwritten each clock cycle.\\
Restricted to $[0,127]$.
}
{---- ---- ---- ---- ---- ---- -ddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0001}
{}

All remaining time constants refer to the common timing information $t$.

The data acquisition starts with the transisition of $t$ trough zero. Thus the
data acquisition time can be chose:

\begin{center}
  \fbox{Data acquisition for $t_{Timer} \geq t_0$ and $t < t_{AE}$}
\end{center}

\register{TPPAE}{0x3004}{Event Buffer Data Acquisition End}
{
$ = t_{AE}$\\
Restricted to $[0,127]$.
}
{---- ---- ---- ---- ---- ---- -ddd dddd}
{0000 0000 0000 0000 0000 0000 0001 1110}
{}

The common control will indicate the data acquistion and preprocessing end
towards the GSM if \fbox{$t > t_{Res}$}.

(here specify the recommended value, depending on the other parameters!!!)

\register{TPPGR}{0x3003}{Response Time to GSM}
{
$ = t_{Res}$\\
Restricted to $[0,127]$.
}
{---- ---- ---- ---- ---- ---- -ddd dddd}
{0000 0000 0000 0000 0000 0000 0001 0101}
{}

%-----------------------------------------------------------------------------
\section{Filter}
\label{tpp:filter}

The filter is located next to the ADC interface (see \ref{adc:spec:dig}). It
provides filtered data for data storage within the event buffers (see
\ref{tpp:eb}) and for tracklet preprocessing (see \ref{tpp:pre}). Additionally
it can filter data from the event buffer instead of the ADC values for testing
purposes.

\begin{figure}[htb]
  \centering
  \includegraphics*[width=14cm]{chap_tpp/TRAP3-Filter.eps}
  \caption[Filter Structure]{\label{fig:TRAP3-Filter}Filter Structure within one Channel}
  
\end{figure}

The filter is organized in 21 channels which operate in parallel. Data is being
exchanged between neighboring channels. One channel consists of the data control
logic and five filter stages: Nonlinearity, pedestal and gain Correction as well
as tail cancellation and crosstalk suppresion.

To keep numerical errors negligible two internal decimal places have been added.
They are used by the tracklet preprocessor but not stored into the event buffer.

%-----------------------------------------------------------------------------
\subsection{Data Control}
\label{tpp:filter:data}

Though this module is located within the filter channels it is mostly related to
the event buffer. It only affects the filter by a selectable data delay and a
data switch which provides the usage of event buffer data instead of ADC values.
See \ref{tpp:eb:acq} for a detailed discussion.

%-----------------------------------------------------------------------------
\subsection{Nonlinearity Correction}
\label{tpp:filter:nonlin}

The nonlinearity correction filter provides a slightly nonlinear transition
function:

\begin{equation}
  O(t) = I(t) \cdot 4 + LUT_{NL} \left( \frac{I(t)}{16} \right)
\end{equation}

The full dynamic range $[0,1023]$ is being divided into 64 bins. Each
of them contains 16 signal values. An independent additive can be defined for
each bin. The output contains two additional decimal places.

\begin{figure}[htb]
  \centering
  \includegraphics*[width=14cm]{chap_tpp/TRAP3-Filter-Nonlinearity.eps}
  \caption[Nonlinearity Correction Filter]{\label{fig:TRAP3-Filter-nonlin}Architecture of the Nonlinearity Correction Filter}
  
\end{figure}

\register{FLBY}{0x3018}{Nonlinearity Correction Filter Bypass}
{$=0$ bypass nonlinearity correction filter \\
 $=1$ use nonlinearity correction filter
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

\register{FLLn}{0x3100+n}{Nonlinearity Correction Filter Look Up Table}
{
$= LUT_{NL}(n)$, $n \in [00,0x3F]$\\
Additive for signal bin $[0,15]$, $[16,31]$, etc.\\
The value contains two decimal places.\\
Restricted to $[0.00,15.75]$.
}
{---- ---- ---- ---- ---- ---- --dd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}


%-----------------------------------------------------------------------------
\subsection{Pedestal Correction}
\label{tpp:filter:ped}

The pedestal correction filter determines and substracts individual pedestals in
each channel and adds a common pedestal:

\begin{equation}
  O_n(t) = I_n(t) + P_{FPNP} - P_n(t)
\end{equation}

The pedestal $P_n(t)$ is determined by a relaxation process:

\begin{eqnarray}
  P_{FPAn}(t+1) &=& P_{FPAn}(t) + \left( I(t) - \beta \cdot P_{FPAn}(t) \right)\\
  P_n(t) &=& \beta \cdot P_{FPAn}(t) 
\end{eqnarray}

Within these equations $\beta$ is the control parameter which influences the
settlement time $\tau$ and the cut-off frequency $\bar{\nu}$. See \cite{gu-dipl}
for more infomration. The control
parameter can be adjusted by the time constant register:
\begin{center}
  \begin{tabular}{|c|c|c|c|c|}
    \hline
    \textbf{FPTC}  & 0 & 1 & 2 & 3 \\
    \hline
    $\beta$ & $2^{-13}$ & $2^{-16}$ & $2^{-19}$ & $2^{-23}$ \\
    \hline
  \end{tabular}
\end{center}

\begin{figure}[htb]
  \centering
  \includegraphics*[width=14cm]{chap_tpp/TRAP3-Filter-Pedestal.eps}
  \caption[Pedestal Correction Filter]{\label{fig:TRAP3-Filter-Pedestal}Architecture of the Pedestal Correction Filter}
  
\end{figure}

\register{FPBY}{0x3019}{Pedestal Correction Filter Bypass}
{$=0$ bypass pedestal correction filter \\
 $=1$ use pedestal correction filter
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

\register{FPTC}{0x3020}{Pedestal Correction Time Constant}
{The first column contains the register value.
 The user has to reset the accumulators (see \textbf{FPCL}) after the
 configuration of this register.
 
 \begin{tabular}{|c|r|r|r|}
    \hline
    $\#$ & $\tau[ms]$ & $\tau[clocks]$ & $\bar{\nu}[Hz]$\\
    \hline
    $0$ & $ 0.82 $ & $ 8 192 $ & $ 491.1 $ \\
    $1$ & $ 6.55 $ & $ 65 536 $ & $ 61.4 $ \\
    $2$ & $ 52.43 $ & $ 524 288 $ & $ 7.7 $ \\
    $3$ & $ 838.86 $ & $ 8 388 608 $ & $ 0.5 $ \\
    \hline
 \end{tabular}
}
{---- ---- ---- ---- ---- ---- ---- --dd}
{0000 0000 0000 0000 0000 0000 0000 0011}
{}

\register{FPNP}{0x3021}{Pedestal Correction Additive}
{Common additive for all channels.\\
 The value contains two decimal places.\\
 Restricted to $[0,127.75]$.
}
{---- ---- ---- ---- ---- ---d dddd dddd}
{0000 0000 0000 0000 0000 0000 0111 1000}
{}

\register{FPCL}{0x3022}{Pedestal Correction Filter Clear}
{$=0$ clear pedestal correction filter \\
 $=1$ keep pedestal correction filter running
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0001}
{}

\register{FPAn}{0x3060+n}{Pedestal Correction Filter Accumulators}
{
$n \in [0,20]$\\
Pedestal accumulator value for channel n.\\
The number of decimal places of this value depends on register \textbf{FPTC}:\\

\begin{tabular}{|c|c|c|c|c|}
  \hline
  \textbf{FPTC}  & 0 & 1 & 2 & 3 \\
  \hline
  decimal places & 13 & 16 & 19 & 23 \\
  \hline
\end{tabular}

Restricted to $[0.00,256)$. \\
Read only.
}
{-ddd dddd dddd dddd dddd dddd dddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}


%-----------------------------------------------------------------------------
\subsection{Gain Correction}
\label{tpp:filter:gain}

The gain correction filter scales input data within a range of $\pm$ 12 \%. The
scaling factors can be configured for each individual channel. Because this
filter stage is located behind the pedestal correction filter, individual
additives for each channel can be defined to compensate scaling related pedestal
shifts:

\begin{equation}
  O_n(t) = \gamma_n \cdot I_n(t) + \rho_n
\end{equation}

To calibrate the gain variation which has to be compensated by this filter stage
two counters are available for each channel:

\begin{eqnarray}
  C_{A,n} &=&~\#~\Bigl\{t~|~T_B > O_n(t) \ge T_A \Bigr\}\\
  C_{B,n} &=&~\#~\Bigl\{t~|~O_n(t) \ge T_B \Bigr\}
\end{eqnarray}

If one of both counters of a channel reaches the maximum count ($2^{26}-1$) both
counters stop until they are cleared. See \cite{gu-dipl} for suggestions on the
calibration process.

\begin{figure}[htb]
  \centering
  \includegraphics*[width=14cm]{chap_tpp/TRAP3-Filter-Gain.eps}
  \caption[Gain Correction Filter]{\label{fig:TRAP3-Filter-Gain}Architecture of the Gain Correction Filter}
  
\end{figure}

\register{FGBY}{0x301A}{Gain Correction Filter Bypass}
{$=0$ bypass gain correction filter \\
 $=1$ use gain correction filter
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

\register{FGFn}{0x3080+n}{Gain Correction Filter Factors}
{
$n \in [0,20]$\\
$= ( \gamma_n - 0.875 ) \cdot 2^{11}$\\
Restricted to $0.875 \leq \gamma_n \leq 1.125 - 2^{-11}$ $\forall i$
}
{---- ---- ---- ---- ---- ---d dddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

\register{FGAn}{0x30A0+n}{Gain Correction Filter Additive}
{
$= \rho_n$, $n \in [0,20]$\\
The value contains two decimal places.\\
Restricted to $0.00 \leq \gamma_n \leq 15.75$ $\forall i$
}
{---- ---- ---- ---- ---- ---- --dd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

\register{FGTA}{0x3028}{Gain Correction Counter Threshold A}
{
$= T_A$\\
This value contains two decimal places.\\
Restricted to $[0,1023.75]$.
}
{---- ---- ---- ---- ---- dddd dddd dddd}
{0000 0000 0000 0000 0000 0000 0001 0100}
{}

\register{FGTB}{0x3029}{Gain Correction Counter Threshold B}
{
$= T_B$\\
This value contains two decimal places.\\
Restricted to $[0,1023.75]$.
}
{---- ---- ---- ---- ---- dddd dddd dddd}
{0000 0000 0000 0000 0000 1000 0000 1100}
{}

\register{FGCL}{0x302A}{Gain Correction Filter Clear}
{$=0$ clear gain correction filter \\
 $=1$ keep gain correction filter running
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0001}
{}

\register{FGCAn}{0x30C0+n}{Gain Correction Filter Counter A}
{
$= C_{A,n}$, $n \in [0,20]$\\
Counter A for channel n\\
Restricted to $[0,2^{26})$\\
Read only.
}
{---- --dd dddd dddd dddd dddd dddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

\register{FGCBn}{0x30E0+n}{Gain Correction Filter Counter B}
{
$= C_{B,n}$, $n \in [0,20]$\\
Counter B for channel n.\\
Restricted to $[0,2^{26})$\\
Read only.
}
{---- --dd dddd dddd dddd dddd dddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

%-----------------------------------------------------------------------------
\subsection{Tail Cancellation}
\label{tpp:filter:tail}

\begin{figure}[htb]
  \centering
  \includegraphics*[width=12cm]{chap_tpp/tail_simulation.eps}
  \caption[Ideal ion tail]{\label{fig:tail}The ideal ion tail can be
  expressed as the sum of two exponentials.}
  
\end{figure}

The tail cancellation filter suppresses the ion tail caused by the gas
chamber (see Fig. \ref{fig:tail}). It can be sufficiently approximated by a two
exponential approach ($N=2$):

\begin{equation}
  S(t) = \textbf{1}_{(t \geq 0)} \cdot \sum_{n=1}^{N}
         \alpha_{n}~e^{- \kappa_{n} t} + R_{N}(t)
\end{equation}

The time $t$ is being measured in terms of time bins.
For the present hardware implementation this has been simplified to:

\begin{equation}
  S(t) = \textbf{1}_{(t \geq 0)} \cdot \left[ \alpha_{L}~\lambda_{L}^{t}
         + ( 1-\alpha_{L} )~\lambda_{S}^{t} \right]
\end{equation}

See \cite{gu-dipl} for suggestions how the parameteres $\alpha_{L}$,
$\lambda_{L}=e^{-\kappa_L}$ and $\lambda_{S}=e^{-\kappa_S}$ 
can be obtained as floating point numbers. Note that $\left\{ \alpha_{L},
\lambda_{L} \right\}$ describes the long term decay while $\left\{
( 1-\alpha_{L} ), \lambda_{S} \right\}$ describes the short exponential.
The time constants have to be expressed in terms of cycle times.

\begin{figure}[htb]
  \centering
  \includegraphics*[width=14cm]{chap_tpp/TRAP3-Filter-Tail.eps}
  \caption[Tail Cancellation Filter]{\label{fig:TRAP3-Filter-Tail}Architecture of the Tail Cancellation Filter}
  
\end{figure}

\begin{figure}[htb]
  \centering
  \includegraphics*[width=7cm]{chap_tpp/TRAP3-Filter-Exp.eps}
  \caption[Exponential Generator]{\label{fig:TRAP3-Filter-Exp}Architecture of one Exponential Generator}
  
\end{figure}

\register{FTBY}{0x301B}{Tail Cancellation Filter Bypass}
{$=0$ bypass tail cancellation filter \\
 $=1$ use tail cancellation filter
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

\register{FTAL}{0x3030}{Tail Cancellation Long Decay Weight}
{$= \left[ \alpha_{L} \cdot 2^{11} \right]$ \\
 Restricted to $ 0 \leq \alpha_{L} \leq ( 0.5 - 2^{-11} )$
}
{---- ---- ---- ---- ---- --dd dddd dddd}
{0000 0000 0000 0000 0000 0000 1111 0110}
{}

\register{FTLL}{0x3031}{Tail Cancellation Long Decay Parameter}
{$= \left[ ( \lambda_{L} - 0.75 ) \cdot 2^{11} \right]$ \\
 Restricted to $ ( 0.75 ) \leq \lambda_{L} \leq ( 1 - 2^{-11} )$
}
{---- ---- ---- ---- ---- ---d dddd dddd}
{0000 0000 0000 0000 0000 0001 0001 1101}
{}

\register{FTLS}{0x3032}{Tail Cancellation Short Decay Parameter}
{$= \left[ ( \lambda_{S} - 0.25 ) \cdot 2^{11} \right]$ \\
 Restricted to $ ( 0.25 ) \leq \lambda_{S} \leq ( 0.5 - 2^{-11} )$
}
{---- ---- ---- ---- ---- ---d dddd dddd}
{0000 0000 0000 0000 0000 0000 1101 0011}
{}

The dc responce of the tail filter is given by:

\begin{equation}
  K_{TAIL, dc}=\frac{(1-\lambda_{S}) \cdot (1-\lambda_{L})}{1-\alpha_{L}~\lambda_{S}-(1-\alpha_{L})\lambda_{L}}
\end{equation}


%-----------------------------------------------------------------------------
\subsection{Crosstalk Suppression Filter}
\label{tpp:filter:cross}

The crosstalk suppression filter is based on a two dimensional convolution. The
filter matrix has the following form:
\begin{center}
  \begin{tabular}{|c|c|c|}
    \hline
    $W_0$ & $0$ & $W_0$ \\
    \hline
    $W_1$ & $0$ & $W_1$ \\
    \hline
    $W_2$ & $1$ & $W_2$ \\
    \hline
    $W_3$ & $0$ & $W_3$ \\
    \hline
    $W_4$ & $0$ & $W_4$ \\
    \hline
  \end{tabular}
\end{center}

Thus the Filter bahavior is determined by the five weights $W_n$:
\begin{equation}
  O_i(t) = I_i(t-2) + \sum_{n=0}^4 W_n \cdot \left( I_{i-1}(t-n)
                                               + I_{i+1}(t-n) \right)
\end{equation}

$I_{-1}(t)$ and $I_{21}(t)$ are assumed to be zero.

\begin{figure}[htb]
  \centering
  \includegraphics*[width=14cm]{chap_tpp/TRAP3-Filter-Xtalk.eps}
  \caption[Crosstalk Suppression Filter]{\label{fig:TRAP3-Filter-Xtalk}Architecture of the Crosstalk Suppression Filter}
  
\end{figure}

\register{FCBY}{0x301C}{Crosstalk Cancellation Filter Bypass}
{$=0$ bypass crosstalk cancellation filter \\
 $=1$ use crosstalk cancellation filter
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

\register{FCW1}{0x3038}{Crosstalk Cancellation Filter Weight 1}
{
 $= \biggl( \Bigl( (signed~int)~(W_1) \Bigr) \cdot 2^{10} \biggr)~\&~0xFF$,
 $n \in [0,4]$\\
 Restricted to $-0.125 \leq W_1 \leq 0.125 - 2^{-10}$.
}
{---- ---- ---- ---- ---- ---- dddd dddd}
{0000 0000 0000 0000 0000 0000 0001 1110}
{}

\register{FCW2}{0x3039}{Crosstalk Cancellation Filter Weight 2}
{
 $= \biggl( \Bigl( (signed~int)~(W_2) \Bigr) \cdot 2^{10} \biggr)~\&~0xFF$,
 $n \in [0,4]$\\
 Restricted to $-0.125 \leq W_2 \leq 0.125 - 2^{-10}$.
}
{---- ---- ---- ---- ---- ---- dddd dddd}
{0000 0000 0000 0000 0000 0000 1101 0100}
{}

\register{FCW3}{0x303A}{Crosstalk Cancellation Filter Weight 3}
{
 $= \biggl( \Bigl( (signed~int)~(W_3) \Bigr) \cdot 2^{10} \biggr)~\&~0xFF$,
 $n \in [0,4]$\\
 Restricted to $-0.125 \leq W_3 \leq 0.125 - 2^{-10}$.
}
{---- ---- ---- ---- ---- ---- dddd dddd}
{0000 0000 0000 0000 0000 0000 1110 0110}
{}

\register{FCW4}{0x303B}{Crosstalk Cancellation Filter Weight 4}
{
 $= \biggl( \Bigl( (signed~int)~(W_4) \Bigr) \cdot 2^{10} \biggr)~\&~0xFF$,
 $n \in [0,4]$\\
 Restricted to $-0.125 \leq W_4 \leq 0.125 - 2^{-10}$.
}
{---- ---- ---- ---- ---- ---- dddd dddd}
{0000 0000 0000 0000 0000 0000 0100 1010}
{}

\register{FCW5}{0x303C}{Crosstalk Cancellation Filter Weight 5}
{
 $= \biggl( \Bigl( (signed~int)~(W_5) \Bigr) \cdot 2^{10} \biggr)~\&~0xFF$,
 $n \in [0,4]$\\
 Restricted to $-0.125 \leq W_5 \leq 0.125 - 2^{-10}$.
}
{---- ---- ---- ---- ---- ---- dddd dddd}
{0000 0000 0000 0000 0000 0000 1110 1111}
{}


%-----------------------------------------------------------------------------
\section{Preprocessor}
\label{tpp:pre}

The tracklet preprocessor receives data from the digital filter (see
\ref{tpp:filter}). It detects tracklets and calculates their fit parameters. The
parameters are stored within the fit register file (FRF). The FRF is accessible
by the CPUs (see \ref{tp}).

\begin{figure}[htb]
  \centering
  \includegraphics*[width=14cm]{chap_tpp/TRAP3-Preprocessor.eps}
  \caption[Preprocessor Structure]{\label{fig:TRAP3-Preprocessor}Preprocessor Structure}
  
\end{figure}


The preprocessor contains hit detection and hit selection modules. They
determine which data is passed to the four arithmetic units. Here fit parameters
are calculated from the received hit data. The hit parameters are accumulated
for each channel seperately and stored into the FRF.\\
The FRF contains a tracklet
candidate selection unit which assigns tracklet candidates for the CPUs tracklet
parameter access. A tracklet candidate is a pair of channels with a reasonable
number of processed hits.
\\\par
The preprocessor only takes the inner channels into account as tracklet
candidates. The outermost channels (0, 20) are used for position calculation due
to the distributed charge of the hits.

The widths of the accumulators of the preprocessor
are chosen for a fit through a maximum of 20 hits. Nevertheless the duration can
be arbitrary chosen by the configuration of starting and ending time of the
linear fit:

\begin{center}
  \fbox{Linear Fit for $t_{FS} \leq t < t_{FE}$}
\end{center}

\register{TPFS}{0x3001}{Preprocessor's Linear Fit Start}
{
$ = t_{FS}$\\
Restricted to $[0,127]$.
}
{---- ---- ---- ---- ---- ---- -ddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0101}
{}

\register{TPFE}{0x3002}{Preprocessor's Linear Fit End}
{
$ = t_{FE}$\\
Restricted to $[0,127]$.
}
{---- ---- ---- ---- ---- ---- -ddd dddd}
{0000 0000 0000 0000 0000 0000 0001 0100}
{}

In parallel to the linear fit the charge along the tracklet is being
accumulated. For a better electron pion separation the total charge of two
independent configurable parts of the tracklets can be determined:

\begin{center}
  \fbox{Accumulate $Q_{T0}$ for $t_{QS0} \leq t < t_{QE0}$}\\
  \vspace{1ex}
  \fbox{Accumulate $Q_{T1}$ for $t_{QS1} \leq t < t_{QE1}$}
\end{center}

Note that the charge here has some pedestal, which should be taken into account when
interpreting the accumulated values.

The charge windows are independent on the linear fit window, but if TPQE1 $>$ TPFE the latched set of preprocessor
registers might be totally wrong. If TPD $>$ 11, the max good value of TPQE1 is TPFE $+$ 1.

\register{TPQS0}{0x3005}{Charge Accumulator 0 Start}
{
$ = t_{QS0}$\\
Restricted to $[0,127]$.
}
{---- ---- ---- ---- ---- ---- -ddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

\register{TPQE0}{0x3006}{Charge Accumulator 0 End}
{
$ = t_{QE0}$\\
Restricted to $[0,127]$.
}
{---- ---- ---- ---- ---- ---- -ddd dddd}
{0000 0000 0000 0000 0000 0000 0000 1010}
{}

\register{TPQS1}{0x3007}{Charge Accumulator 1 Start}
{
$ = t_{QS1}$\\
Restricted to $[0,127]$.
}
{---- ---- ---- ---- ---- ---- -ddd dddd}
{0000 0000 0000 0000 0000 0000 0000 1011}
{}

\register{TPQE1}{0x3008}{Charge Accumulator 1 End}
{
$ = t_{QE1}$\\
Restricted to $[0,127]$.
}
{---- ---- ---- ---- ---- ---- -ddd dddd}
{0000 0000 0000 0000 0000 0000 0001 0100}
{}

%-----------------------------------------------------------------------------
\subsection{Hit Detection and Selection}
\label{tpp:pre:hit}

First the channels are marked wheather they contain possible hits. Therefore the
value of channel i, $Q_i(t)$, has to be a local maximum and the joint charge
with the neighboring channels (cluster charge) has to be above some threshold:

\begin{eqnarray}
  Q_i(t) & \geq & Q_{i-1}(t)\\
  Q_i(t) & > & Q_{i+1}(t)\\
  Q_{i-1}(t) + Q_i(t) + Q_{i+1}(t) & \geq & T_H
\end{eqnarray}

Note that the charge here has some pedestal, which should be taken into account when
selecting the proper value for TPHT. This pedestal will be removed later when processing the hit,
see TPFP.

\register{TPHT}{0x3041}{Cluster Charge Threshold}
{
 $= T_H \cdot 4$\\
 This value contains two decimal places.\\
 Restricted to $-0.0 \leq T_H \leq 4095.75$.
}
{---- ---- ---- ---- --dd dddd dddd dddd}
{0000 0000 0000 0000 0000 0000 1010 0000}
{}

If the hits are up to four, the marked hits are passed to the arithmetics
directly. If the hits are five or six, the best four are selected for the following
arithmetic operations. If the hits are more than six, the best four in the leftmost three 
and the righmost three channels are selected.
A hit is considered to be better if its cluster charge (neglecting
the six LSBs) is bigger.

%See \cite{gu-dipl} for a more detailed discussion of
%the sorting method.

%-----------------------------------------------------------------------------
\subsection{Arithmetic Unit}
\label{tpp:pre:arith}

The tracklet preprocessor contains four arithmetic units. Each of them validates
the assigned hits, calculates their position and adds the correspondent fit
parameters to the sums in the given channel.
\\\par
For the hit verification a quality measure should be below a given treshold:

\begin{eqnarray}
  \frac{Q_{i-1}(t) \cdot Q_{i+1}(t)}{Q_i^2(t)} & < & T_Q\\
  \Longleftrightarrow ~ Q_{i-1}(t) \cdot Q_{i+1}(t) & < & T_Q \cdot Q_i^2(t)
\end{eqnarray}

Note that the charge here has some pedestal, which should be taken into account when
selecting the proper value for TPVT. This pedestal will be removed later when processing the hit,
see TPFP.

\register{TPVBY}{0x3043}{Cluster Verification Bypass}
{$=0$ bypass cluster verfication \\
 $=1$ use cluster verification
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

\register{TPVT}{0x3042}{Cluster Quality Threshold}
{
 $= T_Q \cdot 2^{10}$\\
 Restricted to $0.0 \leq T_Q \leq 2^{-4}-2^{10}$.
}
{---- ---- ---- ---- ---- ---- --dd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

The first estimate of the unsigned channel relative position of the cluster is
determined by the charge distribution over the neighboring channels:
\begin{eqnarray}
  \label{tpp:pre:arith_eqn}
  \widetilde{COG}(t) & = & \frac{|\tilde{Q}_{i+1}(t) - \tilde{Q}_{i-1}(t)|}
                                {\tilde{Q}_i(t)}\\
  \tilde{Q}_j(t) & = & Q_j(t) - P_{\bf TPFP} \hspace{1cm}, ~ j = i \pm 1,0
\end{eqnarray}

Equation \ref{tpp:pre:arith_eqn} is only valid with zero pedestal. Therefore the
pedestal corrected value are used. The constant pedestal from the pedestal and
gain correction filter is being transformed by the tail cancellation and
crosstalk suppression filters. The transformed pedestal should be given as a
parameter $P_{\bf TPFP}$.

\register{TPFP}{0x3040}{Filtered Pedestal}
{
 $= P_{\bf TPFP} \cdot 4$\\
 Restricted to $0.0 \leq P_{\bf TPFP} \leq 127,75$.
}
{---- ---- ---- ---- ---- ---d dddd dddd}
{0000 0000 0000 0000 0000 0000 0011 0111}
{}

The final estimate of the unsigned cluster position is obtained by a nonlinear
transformation of the first estimate:

\begin{equation}
  \widetilde{Pos}(t) = \frac{1}{2}\widetilde{COG}(t) + \cdot LUT_{Pos}
  \left( \left( \widetilde{COG}(t) \cdot 2^7 \right) \% ~ 2^7 \right)
\end{equation}

\register{TPLn}{0x3180+n}{Position Correction Look Up Table}
{
$= LUT_{Pos}(n) \cdot 2^{8}$, $n \in [00,7F]$\\
Additive for position.\\
Restricted to $[0.000,0.125)$.
}
{---- ---- ---- ---- ---- ---- ---d dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

The signed channel relative position follows immediately from the unsigned term:

\begin{eqnarray}
  x(t) & \equiv & Pos(t) = \widetilde{Pos}(t) \cdot
       sign \left( \tilde{Q}_{i+1}(t) - \tilde{Q}_{i-1}(t) \right) \\
  y(t) & \equiv & t
\end{eqnarray}

The tracklet are specified by the parameters of a straight line model:

\begin{equation}
  y(t) = a + b \cdot x(t)
\end{equation}

Thus the parameters can be derived from the observed hits.
$\bar{x}$ and $\bar{y}$ are the mean values of $x$ and $y$ respectively.

\begin{eqnarray}
  a(t) & = & \bar{y} - b \bar{x}\\
  b(t) & = & \frac{\sum_{i \leq t} \Bigl( x(i) - \bar{x} \Bigr)
                \Bigl( y(i) - \bar{y} \Bigr)}
	       {\sum_{i \leq t} \Bigl( x(i) - \bar{x} \Bigr)^2}
\end{eqnarray}

Therefore the following sums are calculated recursively within the arithmetic
units of the preprocessor:

\begin{eqnarray}
  \sum_{s \leq t} x(s) & = & x(t) + \sum_{s \leq t-1} x(s)\\
  \sum_{s \leq t} x^2(s) & = & x^2(t) + \sum_{s \leq t-1} x^2(s)\\
  \sum_{s \leq t} x(s) y(s) & = & x(t) y(t) + \sum_{s \leq t-1} x(s) y(s)\\
  \sum_{s \leq t} y(s) & = & y(t) + \sum_{s \leq t-1} y(s)\\
  \sum_{s \leq t} y^2(s) & = & y^2(t) + \sum_{s \leq t-1} y^2(s)\\
  \sum_{s \leq t} 1 & = & 1 + \sum_{s \leq t-1} 1\\
\end{eqnarray}

The last term represents a counter which gives the number of processed hits per
channel ($N_i$). Additionally two independent charge sums are accumulated:

\begin{eqnarray}
  Q_{T0,i} = \sum_{T_{S0} \leq t \leq T_{E0}} Q_{i-1}(t) + Q_i(t) + Q_{i+1}(t)\\
  Q_{T1,i} = \sum_{T_{S1} \leq t \leq T_{E1}} Q_{i-1}(t) + Q_i(t) + Q_{i+1}(t)
\end{eqnarray}

The starting and ending time of the two charge accumulations ($T_{S0}$ and 
$T_{E0}$, $T_{S1}$ and $T_{E1}$ respectively) refer to the common control of the
preprocessor and event buffer. They are introduced in \ref{tpp:common}.
The parameters are stored within the fit register file. 

%-----------------------------------------------------------------------------
\subsection{Fit Register File}
\label{tpp:pre:frf}

Two channels are combined to a tracklet candidate $\vec{i} = ( i , i+1 )$.
Each channel contains the parameters introduced above.

A sorting logic choses the four most reasonable candidates. Therefore a
candidate $\vec{i}$ has to fulfill the following conditions:

\begin{eqnarray}
  N_i & \geq & T_{CL}\\
  N_i + N_{i+1} & \geq & T_{CT}
\end{eqnarray}

$N_i$ represents the number of processed hits in channel $i$.
The selection works as following:

\begin{itemize}

\item All channels satisfying the two conditions above are marked

\item If more than four candidates are marked, the threshold applyied to the sum 
($N_i + N_{i+1}$) is further increased, but up to 20

\item Finally, starting from the highest selected channel, up to four are assigned to the CPUs 0..3.

\end{itemize}

% If more than four
%candidates satisfy these conditions, those with the highest total number of hits
%($N_i + N_{i+1}$) are selected. This selection works only until hit counts up to 20.
%If two channels have the same number of hits, the channel
%with the higher number will be selected first.
% If more than 4 channels have more than 20 hits, they will remain unsorted.
%Finally CPU0..n-1 get the best n channels,
%sorted descending by the channel number. The rest of the CPUs get channel=31, which indicates
%no tracklet candidate.

%See \cite{gu-dipl} for a more detailed discussion of the sorting method.

\register{TPCL}{0x3045}{Tracklet Candidate Left Hit Number Threshold}
{
$= T_{CL}$\\
Valid sorting only for $T_{CL} \geq 1$\\
Restricted to $[1,31]$.
}
{---- ---- ---- ---- ---- ---- ---d dddd}
{0000 0000 0000 0000 0000 0000 0000 0001}
{}

\register{TPCT}{0x3044}{Tracklet Candidate Total Hit Number Threshold}
{
$= T_{CT}$\\
Valid sorting only for $T_{CT} \geq 8$\\
Restricted to $[8,31]$.
}
{---- ---- ---- ---- ---- ---- ---d dddd}
{0000 0000 0000 0000 0000 0000 0000 1000}
{}

After the selection the candidates are assigned to the four CPUs. Each of them
accesses its own candidate registerlike (see \ref{tp}):

\begin{center}
  \begin{tabular}{|c|c|c|l|}
  \hline
  parameter & channel & width & CPU access \\
  \hline
  $i$ & $i$ & 5 & FRF[0] \\
  $N_i$ & $i$ & 5 & FRF[1] \\
  $Q_{T0,i}$ & $i$ & 15 & FRF[2].Bit[14..0] \\
  $Q_{T1,i}$ & $i$ & 16 & FRF[2].Bit[31..16] \\
  $\sum_t x_i(s)$ & $i$ & 9 & FRF[3] \\
  $\sum_t x_i^2(s)$ & $i$ & 14 & FRF[4] \\
  $\sum_t y_i(s)$ & $i$ & 14 & FRF[5] \\
  $\sum_t x_i(s) y_i(s)$ & $i$ & 17 & FRF[6] \\
  $\sum_t y_i^2(s)$ & $i$ & 21 & FRF[7] \\
  \hline
  \hline
  parameter & channel & width & CPU access \\
  \hline
  ${i+1}$ & ${i+1}$ & 5 & FRF[8] \\
  $N_{i+1}$ & ${i+1}$ & 5 & FRF[9] \\
  $Q_{T0,{i+1}}$ & ${i+1}$ & 15 & FRF[10].B{i+1}t[14..0] \\
  $Q_{T1,{i+1}}$ & ${i+1}$ & 16 & FRF[10].B{i+1}t[31..16] \\
  $\sum_t x_{i+1}(s)$ & ${i+1}$ & 9 & FRF[11] \\
  $\sum_t x_{i+1}^2(s)$ & ${i+1}$ & 14 & FRF[12] \\
  $\sum_t y_{i+1}(s)$ & ${i+1}$ & 14 & FRF[13] \\
  $\sum_t x_{i+1}(s) y_{i+1}(s)$ & ${i+1}$ & 17 & FRF[14] \\
  $\sum_t y_{i+1}^2(s)$ & ${i+1}$ & 21 & FRF[15] \\
  \hline
  \end{tabular}
\end{center}

After the selection the parameters for the lower channel are latched and the
parameters for the upper channel are provided by the constantly driven address.
The computation time needed for the candidate selection has to be taken into
account:

\register{TPD}{0x3047}{Tracklet Candidate Latch Delay}
{
Delay between end of preprocessing and end of tracklet candidate selection in
terms of 120 MHz clock cycles.
Restricted to $[0,15]$. Recommended value 15.
}
{---- ---- ---- ---- ---- ---- ---- dddd}
{0000 0000 0000 0000 0000 0000 0000 1111}
{}

The number of hits of all channels is accessible through the global i/o bus for
testing purposes:

\register{TPHn}{0x3140+n}{Number of Hits in Channel n}
{
Number of processed hits in channel n.\\
Read only.\\
Restricted to $[0,31]$.
}
{---- ---- ---- ---- ---- ---- ---d dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

It is possible to get the parameters of an arbitrary channel through the
registerlike interface. The upper channel FRF[8]..FRF[15] of the candidate can be changed
anytime while the lower channel will be fixed to the values that correspond to
the settings during the last preprocessing.

\register{TPCBY}{0x3046}{Test Indices Flag}
{$=0$ bypass tracklet candidate selection, use test indices \\
 $=1$ use tracklet candidate selection, neglect test indices
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0001}
{}

\register{TPCIn}{0x3048+n}{Test Index for CPU n}
{Channel number for tracklet candidate interface.
}
{---- ---- ---- ---- ---- ---- ---d dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

Beware of the different channel numbering for ADC values and preprocessor
parameters:

\begin{center}
  \begin{tabular}{|l|c|c|c|c|c|c|c|c|c|c|c|c|c|}
  \hline
  preprocessor &-&0&1&2&3&4& ~ ... ~ &14&15&16&17&18&-\\
  \hline
  \hline
  ADC &0&1&2&3&4&5& ~ ... ~ &15&16&17&18&19&20\\
  \hline
  \end{tabular}
\end{center}

\begin{figure}[htb]
  \centering
  \includegraphics*[width=14cm]{chap_tpp/TRAP3-Channel-Assignment.eps}
  \caption[Numbering Sceme of the TRAP Data Channels]{\label{fig:TRAP3-Channels}Numbering Sceme of the TRAP Data Channels}
  
\end{figure}


%-----------------------------------------------------------------------------
\section{Event Buffer}
\label{tpp:eb}

The event buffer offers data storage for 21 data channels in parallel. Within
each channel 64 words are available. A word consistes of 10 data bits (according
to the ADC resolution) and one parity bit.

The event buffer is connected to the ADCs and the digital filter. It is
accessable through the global I/O bus for writing and through the CPU's local
I/O busses for reading.

%-----------------------------------------------------------------------------
\subsection{Data Acquisition}
\label{tpp:eb:acq}

\begin{figure}[htb]
  \centering
  \includegraphics*[width=14cm]{chap_tpp/TRAP3-TPP-Data-Control.eps}
  \caption[Data Control Unit]{\label{fig:TRAP3-TPP-Data}Structure of the Data Control Unit}
  
\end{figure}

The main functionality of the event buffer is to acquire ADC data during
possible events. To compensate delayed pretrigger signals or to see the past of
an event, the data can be delayed on its way from the ADCs to the digital filter
and event buffer.

\register{EBD}{0x3009}{Event Buffer Input Delay}
{This value determines the delay between the ADCs digital output and the digital
filter and event buffer in terms of 100ns.

\vspace{1ex}

\begin{tabular}{|l|c|c|c|c|c|c|}
  \hline
  value & 0 & 1 & 2 & 3 & 4 & 5 \\
  \hline
  delay[ns] & 100 & 200 & 300 & 400 & 500 & 600 \\
  \hline
\end{tabular}

\vspace{1ex}

Restricted to [0,5].
}
{---- ---- ---- ---- ---- ---- ---- -ddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

It can be configured whether the data before or after the digital filtering will
be stored within the event buffer.

\register{EBSF}{0x300C}{Event Buffer Storage Mode}
{$=0$ store filtered data \\
 $=1$ store unfiltered data
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0001}
{}

The data is organized in 64 words for each channel. The {\em write} word
address within each channel is derived from the common timing reference:

\begin{equation}
  \textnormal{Acquisition Word Address} = ( t + t_{Acq} ) ~ \% ~ 64
  \label{tpp:eb:acq:acqeq}
\end{equation}

\register{EBAQA}{0x300A}{Event Buffer Acquisition Offset Address}
{
$= t_{Acq}$\\
Restricted to [0,127].\\
see equation \ref{tpp:eb:acq:acqeq}.
}
{---- ---- ---- ---- ---- ---- -ddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

Instead of the current ADC values data from the event buffer can be taken
{\em read}, see equation \ref{tpp:eb:acq:simeq}) as the digital filter's input.
Thus the filter and the preprocessor functionality can
be tested. Beware: 

\begin{itemize}

\item the simulation data also has to pass the input pipeline delay.

\item In order to use Event Buffer as data source you have to set the {\em SMMODE.s}
bit to '1'. This enables the read clock of the event buffers during the preprocessing. 

\item when reading the event buffers (see {\em EBRn below)}, if EBSIM remains 0 (active),
the CPU's read address will not reach the read address of the event buffer memory, instead a 
constant read address coming from the bin timer will be applied. So, before the readout by the CPUs
via EBRn, set EBSIM to 1 and eventually reset it back after the readout, if desired for
the next event.
\end{itemize}

\begin{equation}
  \textnormal{Simulation Word Address} = ( t + t_{Sim} ) ~ \% ~ 64
  \label{tpp:eb:acq:simeq}
\end{equation}

\register{EBSIM}{0x300D}{Event Buffer Simulation Mode}
{$=0$ use event buffer data for filtering and preprocessing \\
 $=1$ use ADC data for filtering and preprocessing
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0001}
{}

\register{EBSIA}{0x300B}{Event Buffer Simulation Offset Address}
{
$= t_{Sim}$\\
Restricted to [0,127].\\
see equation \ref{tpp:eb:acq:simeq}.
}
{---- ---- ---- ---- ---- ---- -ddd dddd}
{0000 0000 0000 0000 0000 0000 0010 0000}
{}

%-----------------------------------------------------------------------------
\subsection{Interface to I/O Busses}
\label{tpp:eb:lio}

The event buffer is accessible via different interfaces for reading and for
writing. While writing has to be done through the global I/O bus, reading is
organized locally. Thus five channels are assigned to  CPU0 to CPU2 and six
channels are assigned to CPU3 for reading.

\register{EBRn}{0x0800+n}{Event Buffer Data Read (LIO)}
{
Within each channel 64 data words can be stored:\\
$j \in [0,63]$

\vspace{1ex}

\begin{tabular}{|c|l|c|c|}
  \hline
  CPU\# & memory address & channel & word address \\
  \hline
  \hline
  i & 0x0800+j & $0 + 5 \cdot i$ & j \\
  i & 0x0840+j & $1 + 5 \cdot i$ & j \\
  i & 0x0880+j & $2 + 5 \cdot i$ & j \\
  i & 0x08C0+j & $3 + 5 \cdot i$ & j \\
  i & 0x0900+j & $4 + 5 \cdot i$ & j \\
  \hline
  3 & 0x0940+j & $20$ & j \\
  \hline
\end{tabular}

\vspace{1ex}

The provision of the parity bit depends on \textbf{EBPP}.\\
Read only.
}
{---- ---- ---- ---- ---- -pdd dddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

\register{EBWn}{0x2000+n}{Event Buffer Data Write}
{
Within each channel 64 data words can be stored. Each word is accessible twice.
\\
$c \in [0, 20]$, $j \in [0, 127]$

\vspace{1ex}

\begin{tabular}{|l|c|c|}
  \hline
  memory address & channel & word address \\
  \hline
  \hline
  $0x2000 + 0x80 \cdot c+j$ & $c$ & $j ~ \% ~ 0x40$ \\
  \hline
\end{tabular}

\vspace{1ex}

Write only.
}
{---- ---- ---- ---- ---- --dd dddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

The data is stored with an automatically generated parity bit. It can be chosen
whether one wants to read the data with or without the parity bit:

\register{EBPP}{0x300E}{Event Buffer Parity Bit Mask}
{$=0$ provide parity bit during readout ($p~d_9 d_8 d_7 ... d_2 d_1 d_0$). \\
 $=1$ hide parity bit.
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0001}
{}

Parity errors are counted independently during each read cycle. For reading,
each channel is assigned to one of the four CPUs (see below). So there exists
one counter per CPU. All four counters are cleared by one flag. The counters
will stop if they reach the maximum count.

\register{EBPC}{0x300F}{Event Buffer Parity Violation Counters Clear}
{$=0$ clear parity violation counters \\
 $=1$ keep parity violation counters
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0001}
{}

\register{EBPn}{0x3010+n}{Event Buffer Parity Violation Counter n}
{
Parity violation counter for all channels that are assigned to CPU n:

\vspace{1ex}

\begin{tabular}{|l|c|c|c|c|}
  \hline
  CPU\#    & 0 & 1 & 2 & 3 \\
  \hline
  channels & [0, 4] & [5, 9] & [10, 14] & [15, 20] \\
  \hline
\end{tabular}

\vspace{1ex}

Read only.
}
{---- ---- ---- ---- ---- ---d dddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

%-----------------------------------------------------------------------------
\subsection{Data Indication (Zero Suppression)}
\label{tpp:eb:indi}

There are various possibilities for the indication of the interesting data
values. Here, any combination of three criteria is available:

\begin{eqnarray}
  I_{0,i} (t) & = & \biggl\{ \begin{array}{ll}
                	   0 & \textnormal{if } Q_i(t) \geq Q_{i-1}(t)
			       \textnormal{ and } Q_i(t) \geq Q_{i+1}(t)\\
			   1 & \textnormal{otherwise}\\
			 \end{array} \\
  I_{1,i} (t) & = & \biggl\{ \begin{array}{ll}
                	   0 & \textnormal{if } Q_{i-1}(t) + Q_i(t) + Q_{i+1}(t)
		                        	\geq T_{IT}\\
			   1 & \textnormal{otherwise}\\
			 \end{array} \\
  I_{2,i} (t) & = & \biggl\{ \begin{array}{ll}
                	   0 & \textnormal{if } Q_i(t) \geq T_{IS}\\
			   1 & \textnormal{otherwise}\\
			 \end{array}
\end{eqnarray}

\register{EBIS}{0x3014}{Event Buffer Single Indicator Threshold}
{
$= T_{IS}$\\
Restricted to [0,1023].\\
}
{---- ---- ---- ---- ---- --dd dddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0101}
{}

\register{EBIT}{0x3015}{Event Buffer Sum Indicator Threshold}
{
$= T_{IT}$\\
Restricted to [0,4095].\\
}
{---- ---- ---- ---- ---- dddd dddd dddd}
{0000 0000 0000 0000 0000 0000 0010 1000}
{}

A first decision whether the data is indicated ($\tilde{D}_i(t)$) is derived
from the set of criteria $\vec{I}_i(t) = (I_{2,i}, I_{1,i}, I_{0,i})$ by the
usage of a fully configurable look-up table:

\begin{equation}
  \tilde{D}_i(t) = LUT_{Ind} \Bigl( (int) ~ \vec{I}_i(t) \Bigr)
\end{equation}

\register{EBIL}{0x3016}{Event Buffer Indicator Look-up Table}
{
The bit at position j corresponds to $LUT_{Ind}(j)$.\\
Restricted to [0,FF].\\
}
{---- ---- ---- ---- ---- ---- dddd dddd}
{0000 0000 0000 0000 0000 0000 1111 0000}
{}

The final decision for the inidication of a data value can depend on the
neighbor values too:

\begin{equation}
  D_i(t) = \Biggl\{ \begin{array}{cl}
                      \tilde{D}_{i-1}(t) \wedge \tilde{D}_i(t) \wedge
		      \tilde{D}_{i+1}(t) & \textnormal{if } I_N = 0\\
		      \tilde{D}_i(t) & \textnormal{if } I_N = 1\\
		    \end{array}
\end{equation}

\register{EBIN}{0x3017}{Event Buffer Indicator Neighbor Sensitivity}
{$=0$ take account of neighbor's values \\
 $=1$ use own values only
}
{---- ---- ---- ---- ---- ---- ---- ---b}
{0000 0000 0000 0000 0000 0000 0000 0001}
{}

The indicators $D_i(t)$ are stored in parallel to the data acquisition. They are
not changed by an event buffer access through the global I/O bus. The indicators
can be accessed via the local busses.

\register{EBIn}{0x0980+n}{Event Buffer Indicators (LIO)}
{
Each indicator bit can be read according to the following schema. Beware: CPU3
accesses six channels while CPU0-2 reach five channels only.

\vspace{1ex}

\begin{tabular}{|c|c|c|c|}
  \hline
  CPU\# & address & channel & time bins \\
  \hline
  \hline
  i & 0x0980 & $0 + 5 \cdot i$ & [31, 0] \\
  i & 0x0981 & $0 + 5 \cdot i$ & [63, 32] \\
  \hline
  i & 0x0982 & $1 + 5 \cdot i$ & [31, 0] \\
  i & 0x0983 & $1 + 5 \cdot i$ & [63, 32] \\
  \hline
  i & 0x0984 & $2 + 5 \cdot i$ & [31, 0] \\
  i & 0x0985 & $2 + 5 \cdot i$ & [63, 32] \\
  \hline
  i & 0x0986 & $3 + 5 \cdot i$ & [31, 0] \\
  i & 0x0987 & $3 + 5 \cdot i$ & [63, 32] \\
  \hline
  i & 0x0988 & $4 + 5 \cdot i$ & [31, 0] \\
  i & 0x0989 & $4 + 5 \cdot i$ & [63, 32] \\
  \hline
  3 & 0x098A & $20$ & [31, 0] \\
  3 & 0x098B & $20$ & [63, 32] \\
  \hline
\end{tabular}

\vspace{1ex}

Read only.
}
{dddd dddd dddd dddd dddd dddd dddd dddd}
{0000 0000 0000 0000 0000 0000 0000 0000}
{}

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