\instruction{NOP}
{No Operation} % headline
{} % syntax
{none} % operation
{0000 0000 0000 0000 0000 0000} % opcode
{Performs no operation.} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{none}

\instruction{IEXT}
{Immediate Extend} % headline
{a} % syntax
{K-reg $\leftarrow$ a} % operation
{0101 000a aaaa aaaa aaaa aaaa} % opcode
{Loads the internal K-reg with a 17 bit constant. The first \hlink{MOV},
\hlink{CMP}, \hlink{SGIO} after IEXT which uses the immediate addressing mode will extend the 12 bit
immediate value with the additional 17 bits from the
internal K-reg. The resulting 29 bit value will be sign extended to 32 bit.
The internal K-reg will be cleared. In order to simplify the use of IEXT, \hlink{MOV},
\hlink{CMP} and \hlink{SGIO}, the assembler extends the immediate value to 32 bit signed and takes bits
(28:12) for IEXT and bits (11:0) for \hlink{MOV}, \hlink{CMP}, \hlink{SGIO}.
\minisec{Example}
{\ttfamily
\#def myconstant=0x6543210;
\par IEXT myconstant; \textit{load K-reg with 0x6543}
\par MOV~ myconstant, GRF[8]; \textit{GRF[8]=0x6543210}
\par ; \textit{K-reg is already 0, therefore a warning is expected}
\par MOV~ myconstant, PRF[8]; \textit{PRF[8]=0x210}
\par ~
}
\par See \hlink{MOV}, \hlink{CMP}, \hlink{SGIO}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{Zero	  & - \\
 Carry    & - \\
 Negative & - \\
 TCO	  & - \\
 Signed   & - \\
}
{a & IMM17 \\
}

\instruction{ADD}
{Addition without Carry} % headline
{a, b, t} % syntax
{(t) $\leftarrow$ (a) + (b)} % operation
{1000 011a aaaa -bbb bbbt tttt} % opcode
{Performs a 32~Bit addition without Carry of operand a and operand b and stores the result in target t.} % description
{ \bul & \bul & \bul & \bul & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & carry(a + b) \\
 Negative & MSB(t) \\
 TCO	  & (MSB(a) \& MSB(b) \& $\overline{\textnormal{MSB(t)}}$) $|$\\
  & ($\overline{\textnormal{MSB(a)}}$ \& $\overline{\textnormal{MSB(b)}}$ \& MSB(t)) \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
 a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}

\instruction{ADC}
{Addition with Carry} % headline
{a, b, t} % syntax
{(t) $\leftarrow$ (a) + (b) + carry} % operation
{1000 001a aaaa -bbb bbbt tttt} % opcode
{Performs a 32~Bit addition with Carry of operand a and operand b and stores the result in target t.} % description
{ \bul & \bul & \bul & \bul & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & carry(a + b + carry) \\
 Negative & MSB(t) \\
 TCO	  & (MSB(a) \& MSB(b) \& $\overline{\textnormal{MSB(t)}}$) $|$\\
  & ($\overline{\textnormal{MSB(a)}}$ \& $\overline{\textnormal{MSB(b)}}$ \& MSB(t)) \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
 a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}

\instruction{SUB}
{Substraction without Carry} % headline
{a, b, t} % syntax
{(t) $\leftarrow$ (a) - (b)} % operation
{1000 101a aaaa -bbb bbbt tttt} % opcode
{Performs a 32~Bit substraction without Carry of operand a and operand b and stores the result in target t.} % description
{ \bul & \bul & \bul & \bul & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & carry(a - b) \\
 Negative & MSB(t) \\
 TCO	  & (MSB(a) \& $\overline{\textnormal{MSB(b)}}$ \& $\overline{\textnormal{MSB(t)}}$) $|$\\
  & ($\overline{\textnormal{MSB(a)}}$ \& MSB(b) \& MSB(t)) \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
 a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}

\instruction{CMP}
{Compare} % headline
{a, b} % syntax
{(a) - (b)} % operation
{1000 100a aaaa -bbb bbb0 0000 (direct)\\
 1100 100a aaaa bbbb bbbb bbbb (immediate)} % opcode
{Performs a 32~Bit substraction without Carry of operand a and operand b and discards the result.
\minisec{Example}
{\ttfamily
             CMP FIT[0], GRF[3];
\par         JMP cc\_ltu, smaller;
\par         . . .
\par         IEXT 0x1234567;
\par         CMP PRF[14], 0x1234567;
\par ~
}
\par See \hlink{SUB}, \hlink{MOV}
} % description
{ \bul & \bul & \bul & \bul & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & carry(a - b) \\
 Negative & MSB(t) \\
 TCO	  & (MSB(a) \& $\overline{\textnormal{MSB(b)}}$ \& $\overline{\textnormal{MSB(t)}}$) $|$\\
  & ($\overline{\textnormal{MSB(a)}}$ \& MSB(b) \& MSB(t)) \\
 Signed   & Negative $\oplus$ TCO \\
}
{a & PRF, FIT \\
 b & GRF, PRF, FIT, CON (direct)\\
   & IMM12e (immediate)\\
}

\instruction{SBC}
{Substraction with Carry} % headline
{a, b, t} % syntax
{(t) $\leftarrow$ (a) - (b) - carry} % operation
{1000 111a aaaa -bbb bbbt tttt} % opcode
{Performs a 32~Bit substraction with Carry of operand a and operand b and stores the result in target t.} % description
{ \bul & \bul & \bul & \bul & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & carry(a - b - carry) \\
 Negative & MSB(t) \\
 TCO	  & (MSB(a) \& $\overline{\textnormal{MSB(b)}}$ \& $\overline{\textnormal{MSB(t)}}$) $|$\\
  & ($\overline{\textnormal{MSB(a)}}$ \& MSB(b) \& MSB(t)) \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
 a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}

\instruction{CPC}
{Compare with Carry} % headline
{a, b} % syntax
{(a) - (b) - carry} % operation
{1000 111a aaaa -bbb bbb0 0000} % opcode
{Performs a 32~Bit substraction with Carry of operand a and operand b and discards the result.
\minisec{Example}
{\ttfamily
         ; \textit{compare two 64-bit numbers}
\par         CMP    PRF[ 9], PRF[ 3];
\par         CPC    PRF[10], PRF[ 4];
\par         JMP    cc\_ltu, smaller;
\par ~
}
\par See \hlink{SUB}, \hlink{MOV}
} % description
{ \bul & \bul & \bul & \bul & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & carry(a - b - carry) \\
 Negative & MSB(t) \\
 TCO	  & (MSB(a) \& $\overline{\textnormal{MSB(b)}}$ \& $\overline{\textnormal{MSB(t)}}$) $|$\\
  & ($\overline{\textnormal{MSB(a)}}$ \& MSB(b) \& MSB(t)) \\
 Signed   & Negative $\oplus$ TCO \\
}
{a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}
\instruction{NEG}
{Two's complement, arithmetic negation} % headline
{b, t} % syntax
{(t) $\leftarrow$ 0 - (b)} % operation
{1010 1110 0000 -bbb bbbt tttt} % opcode
{Performs a two's complement of b and stores the result in target t.} % description
{ \bul & \bul & \bul & - & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & set if t /= 0 \\
 Negative & MSB(t) \\
 TCO	  & - \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
 b & GRF, PRF, FIT, CON \\
}
\instruction{SHA}
{Arithmetical shift} % headline
{a, b, t} % syntax
{(t) $\leftarrow$ (b) $\ll$ (a) \\ fill from left with b(31)} % operation
{0111 011a aaaa -bbb bbbt tttt (direct)\\
1011 011a aaaa -bbb bbbt tttt (immediate)} % opcode
{Performs an aithmetical shift of operand b by the value of a interpreted as a
signed 5 bit number (-16..15) and stores the result in target t. Positive a means
shift left (zero-fill from right), negative a means shift right (sign replication fill
from left). In the case of direct addressing mode the other bits
of the register pointed by a are ignored.} % description
{ \bul & \bul & \bul & - & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & set to 0 if a = 0 \\
          & set to b(32-a) if a $>$ 0 \\
          & set to b(-a-1) if a $<$ 0 \\
 Negative & MSB(t) \\
 TCO	  & - \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
 a & PRF, FIT \\
   & IMM5 \\
 b & GRF, PRF, FIT, CON \\
}

\instruction{MUL}
{Multiply Unsigned} % headline
{a, b, t} % syntax
{(ht)(t) $\leftarrow$ (a) * (b)} % operation
{1001 000a aaaa -bbb bbb0 0ttt} % opcode
{Performes a 32 x 32 $\rightarrow$ 64~Bit unsigned multiplication of operand a and operand b within two clock
cycles and stores the result in target t and the most significant 32~Bit (ht) in PRF[13].
Note that the flags will be stored without latency.
\minisec{Example}
{\ttfamily
 MUL~~PRF[14], PRF[15], PRF[0];
\par NOP;~\textit{have to wait 1 clock!}
\par SRA~~PRF[13], 12; \textit{bits 63..32 of the result}
\par SRA~~PRF[ 0] , 8; \textit{bits 31.. 0 of the result}
\par ~
}
\par See \hlink{MUS}, \hlink{MUL32}, \hlink{MUS32}
} % description
{ \bul & - & \bul & \bul & \bul } % condition flags affected (\bul or -)
{Zero	  & set if a = 0 or b = 0 \\
 Carry    & - \\
 Negative & MSB(a) $\oplus$ MSB(b) \\
 TCO	  & 0 \\
 Signed   & MSB(a) $\oplus$ MSB(b) \\
}
{t & PRF[7]..PRF[0] for bits 31..0\\
 & PRF[13] for bits 63..32 of the result\\
 a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}

\instruction{MUS}
{Multiply Signed} % headline
{a, b, t} % syntax
{(ht)(t) $\leftarrow$ (a) * (b)} % operation
{1001 010a aaaa -bbb bbb0 0ttt} % opcode
{Performes a 32 x 32 $\rightarrow$ 64~Bit signed multiplication of operand a and operand b within two clock
cycles and stores the result in target t and the most significant 32~Bits (ht) in PRF[13].
Note that the flags will be stored without latency.
\minisec{Example}
{\ttfamily
\par MUS PRF[14], PRF[15], PRF[0];
\par MOV PRF[ 0], PRF[ 9]; \textit{use the old value of PRF[0]}
\par SRA PRF[13], 12; \textit{bits 63..32 of the result}
\par SRA PRF[ 0], ~8; \textit{bits 31..~0 of the result}
\par ~
}
\par See \hlink{MUL}, \hlink{MUS32}, \hlink{MUL32}
} % description
{ \bul & - & \bul & \bul & \bul } % condition flags affected (\bul or -)
{Zero	  & set if a = 0 or b = 0 \\
 Carry    & - \\
 Negative & MSB(a) $\oplus$ MSB(b) \\
 TCO	  & 0 \\
 Signed   & MSB(a) $\oplus$ MSB(b) \\
}
{t & PRF[7]..PRF[0] for bits 31..0\\
 & PRF[13] for bits 63..32 of the result\\
 a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}

\instruction{MUL32}
{Multiply Unsigned 32 bit} % headline
{a, b, t} % syntax
{(t) $\leftarrow$ (a) * (b)} % operation
{1001 000a aaaa -bbb bbb0 0ttt} % opcode
{Performes a 32 x 32 $\rightarrow$ 32~Bit unsigned multiplication of operand a and operand b within two clock
cycles and stores the result in target t. The most significant 32~Bits will be
discarded. Note that the flags will be stored without latency.
\minisec{Example for pipelining}
{\ttfamily
\par MUL32 PRF[14], PRF[15], PRF[7];
\par MUL32 PRF[11], PRF[12], PRF[6];
\par SRA~~ PRF[ 7], 8; \textit{store the result of the first mul}
\par SRA~~ PRF[ 6],12; \textit{store the result of the second mul}
\par ~
}
\par See \hlink{MUL}, \hlink{MUS}, \hlink{MUS32}
} % description
{ \bul & - & \bul & \bul & \bul } % condition flags affected (\bul or -)
{Zero	  & set if a = 0 or b = 0 \\
 Carry    & - \\
 Negative & MSB(a) $\oplus$ MSB(b) \\
 TCO	  & 0 \\
 Signed   & MSB(a) $\oplus$ MSB(b) \\
}
{t & PRF[7]..PRF[0] for bits 31..0 of the result\\
 a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}

\instruction{MUS32}
{Multiply Signed 32 bit} % headline
{a, b, t} % syntax
{(t) $\leftarrow$ (a) * (b)} % operation
{1001 010a aaaa -bbb bbb0 0ttt} % opcode
{Performes a 32 x 32  $\rightarrow$ 32~Bit signed multiplication of operand a and operand b within two clock
cycles and stores the result in target t. The most significant 32~Bits will be
discarded. 
Note that the flags will be stored without latency.
\minisec{Example for incorrect use}
{\ttfamily
\par MUS32 PRF[14], PRF[15], PRF[3];
\par MOV ~~0x234, ~~PRF[3]; \textit{writing to the same register}
\par SRA ~~PRF[ 3], 8; \textit{undefined result}
\par ~
}
\par See \hlink{MUL}, \hlink{MUS}, \hlink{MUL32}
} % description
{ \bul & - & \bul & \bul & \bul } % condition flags affected (\bul or -)
{Zero	  & set if a = 0 or b = 0 \\
 Carry    & - \\
 Negative & MSB(a) $\oplus$ MSB(b) \\
 TCO	  & 0 \\
 Signed   & MSB(a) $\oplus$ MSB(b) \\
}
{t & PRF[7]..PRF[0] for bits 31..0 of the result\\
 a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}

\instruction{DIV}
{Divide Signed 64:32 bit} % headline
{a, b} % syntax
{start\\
(PRF[13], a) / (b)} % operation
{1001 100a aaaa -bbb bbb0 0000} % opcode
{Starts a 64/32 $\rightarrow$ 32~Bit signed division of operand (PRF[13], a) by b within 19 clock
cycles. Dividend(63:32) is taken from PRF[13], Dividend(31:0) is taken from operand a.
With one clock delay the division error (E) flag will be set if an overflow
happens, otherwise the division busy flag (D) will be set. When the division result is
calculated the division busy flag (D) will be cleared. PRF[13] can be overwritten
immediately after starting the division.
\minisec{Example}
{\ttfamily
     ~~~~~~~~MOV 0, PRF[13];
\par ~~~~~~~~DIV PRF[15], PRF[2];
\par ~~~~~~~~NOP; \textit{wait for flags to be set}
\par ~~~~~~~~JMP cc\_errdiv, diverror; 
\par dwait: JMP cc\_divb, dwait; \textit{wait for division end}
\par ~~~~~~~~DIE PRF[3]; \textit{store the result}
\par ~
}
\par See \hlink{DIE}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{Zero	  & - \\
 Carry    & - \\
 Negative & - \\
 TCO	  & - \\
 Signed   & - \\
}
{a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}

\instruction{DIE}
{Divide End} % headline
{t} % syntax
{(t) $\leftarrow$ division result} % operation
{1001 1110 0000 0000 000t tttt} % opcode
{Stores the result from the last division and sets the zero flag if the result is 0.
\minisec{Example}
{\ttfamily
     ~~~~~~~~MOV 0, PRF[13];
\par ~~~~~~~~DIV PRF[15], PRF[2];
\par ~~~~~~~~NOP; \textit{wait for flags to be set}
\par ~~~~~~~~JMP cc\_errdiv, diverror; 
\par dwait: JMP cc\_divb, dwait; \textit{wait for division end}
\par ~~~~~~~~DIE PRF[3]; \textit{store the result}
\par ~
}
\par See \hlink{DIV}
} % description
{ \bul & - & - & - & - } % condition flags affected (\bul or -)
{Zero	  & set if division result = 0\\
 Carry    & - \\
 Negative & - \\
 TCO	  & - \\
 Signed   & - \\
}
{t & GRF, PRF \\
}
\instruction{AND}
{Bitwise logical AND} % headline
{a, b, t} % syntax
{(t) $\leftarrow$ (a) \& (b)} % operation
{1010 011a aaaa -bbb bbbt tttt} % opcode
{Performs a logically AND of the individual bits of operand a and operand b and stores the result in target t.
\minisec{Example - masking bits 31..8}
{\ttfamily
     ~~~~~~~~MOV 0x0FF, PRF[12];
\par ~~~~~~~~AND PRF[15], PRF[12], PRF[15];
\par ~
}
} % description
{ \bul & - & \bul & - & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & - \\
 Negative & MSB(t) \\
 TCO	  & - \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
 a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}
\instruction{ANDT}
{Bitwise logical AND without write back} % headline
{a, b} % syntax
{(a) \& (b)} % operation
{1010 010a aaaa -bbb bbb0 0000} % opcode
{Performs a logically AND of the individual bits of operand a and operand b and
discards the result.} % description
{ \bul & - & \bul & - & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & - \\
 Negative & MSB(result) \\
 TCO	  & - \\
 Signed   & Negative $\oplus$ TCO \\
}
{a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}
\instruction{OR}
{Bitwise logical OR} % headline
{a, b, t} % syntax
{(t) $\leftarrow$ (a) $|$ (b)} % operation
{1010 101a aaaa -bbb bbbt tttt} % opcode
{Performs a logically OR of the individual bits of operand a and operand b and stores the result in target t.} % description
{ \bul & - & \bul & - & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & - \\
 Negative & MSB(t) \\
 TCO	  & - \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
 a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}
\instruction{COM}
{Complement, logical NOT} % headline
{b, t} % syntax
{(t) $\leftarrow$ ($\overline{\textnormal{b}}$)} % operation
{1011 1110 0000 -bbb bbbt tttt} % opcode
{Performs a logically inversion of the individual bits of operand b and stores the result in target t.} % description
{ \bul & \bul & \bul & - & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & 1 \\
 Negative & MSB(t) \\
 TCO	  & - \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
 b & GRF, PRF, FIT, CON \\
}
\instruction{EOR}
{Bitwise logical exclusive OR} % headline
{a, b, t} % syntax
{(t) $\leftarrow$ (a) $\oplus$ (b)} % operation
{1010 001a aaaa -bbb bbbt tttt} % opcode
{Performs a logically exclusive OR of the individual bits of operand a and operand b and stores the result in target t.} % description
{ \bul & - & \bul & - & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & - \\
 Negative & MSB(t) \\
 TCO	  & - \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
 a & PRF, FIT \\
 b & GRF, PRF, FIT, CON \\
}
\instruction{SHL}
{Logical shift} % headline
{a, b, t} % syntax
{(t) $\leftarrow$ (b) $\ll$ (a)} % operation
{0111 001a aaaa -bbb bbbt tttt (direct)\\
1011 001a aaaa -bbb bbbt tttt (immediate)} % opcode
{Performs a logically shift of operand b by the value of a interpreted as a
signed 5 bit number (-16..15) and stores the result in target t. Positive a means
shift left, negative a means shift right. In the case of direct addressing mode the other bits
of the register pointed by a are ignored.} % description
{ \bul & \bul & \bul & - & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & set to 0 if a = 0 \\
          & set to b(32-a) if a $>$ 0 \\
          & set to b(-a-1) if a $<$ 0 \\
 Negative & MSB(t) \\
 TCO	  & - \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
   & GRF, PRF \\
 a & PRF, FIT \\
   & IMM5 \\
 b & GRF, PRF, FIT, CON \\
}
\instruction{SHLT}
{Logical shift w/o write back} % headline
{a, b} % syntax
{(b) $\ll$ (a)} % operation
{0111 000a aaaa -bbb bbbt tttt (direct)\\
1011 000a aaaa -bbb bbbt tttt (immediate)} % opcode
{Performs a logically shift of operand b by the value of a interpreted as a
signed 5 bit number (-16..15) and discards the result. Positive a means
shift left, negative a means shift right.
\minisec{Example}
{\ttfamily
\par ~~~~~~SHLT -4, PRF[1]; \textit{copy bit 3 to carry}
\par ~~~~~~JMP cc\_ncarry, labA; \textit{jump if bit 3 is 0}
\par ~~~~~~SHLT 2, PRF[1]; \textit{copy bit 30 to carry}
\par ~~~~~~JMP cc\_carry, labB; \textit{jump if bit 30 is 1}
\par ~~~~~~...
\par labA: ...
\par ~~~~~~...
\par labB: ...
\par ~
}
\par See \hlink{SHL}
} % description
{ \bul & \bul & \bul & - & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & set to 0 if a = 0 \\
          & set to b(32-a) if a $>$ 0 \\
          & set to b(-a-1) if a $<$ 0 \\
 Negative & MSB(t) \\
 TCO	  & - \\
 Signed   & Negative $\oplus$ TCO \\
}
{ a & PRF, FIT \\
   & IMM5 \\
 b & GRF, PRF, FIT, CON \\
}
\instruction{ROR}
{Rotate Right through carry} % headline
{b, t} % syntax
{(t) $\leftarrow$ ( c, b(31:1) )} % operation
{1011 1010 0000 0bbb bbbt tttt} % opcode
{Rotates the bits of operand b to the right and stores the result in target t.
\par t(31) $\leftarrow$ carry, t(30:0) $\leftarrow$ b(31:1), carry $\leftarrow$ b(0)
\minisec{Example}
{\ttfamily
\par SHLT 0, PRF[1]; \textit{clear carry}
\par ROR CON[1], PRF[1];
\par ;\textit{Carry and Zero are set, PRF[1]}=0
\par JMP cc\_nzero, exit;
\par JMP cc\_ncarry, exit;
\par JMP cc\_neg, exit;
\par SRA+ PRF[1];
\par ROR CON[0], PRF[1];
\par ;\textit{Carry and Zero are cleared, N is set}
\par ;\textit{PRF[1]}=0x80000000
\par JMP cc\_carry, exit;
\par JMP cc\_zero, exit;
\par JMP cc\_nneg, exit;
\par SRA+ PRF[1];
\par ;\textit{The CPU doesn't jump to exit and comes to this point}
}
} % description
{ \bul & \bul & \bul & - & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & b(0) \\
 Negative & MSB(t) \\
 TCO	  & - \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
 b & GRF, PRF, FIT, CON \\
}
\instruction{SWP}
{Swap the Lo and Hi part} % headline
{b, t} % syntax
{(t) $\leftarrow$ ( b(15:0), b(31:16) )} % operation
{0111 1010 0000 0bbb bbbt tttt} % opcode
{Swaps the Lo and Hi parts of operand b and stores the result in target t.
\par t(31:16) $\leftarrow$ b(15:0), t(15:0) $\leftarrow$ b(31:16)
\minisec{Example}
{\ttfamily
\par IEXT 0x02220111;
\par MOV 0x02220111, PRF[1];
\par; \textit{Now PRF[1] is} 0x02220111
\par SWP PRF[1], PRF[2];
\par; \textit{Now PRF[2] is} 0x01110222
\par ~
}
} % description
{ \bul & - & \bul & - & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t = 0 \\
 Carry    & - \\
 Negative & MSB(t) \\
 TCO	  & - \\
 Signed   & Negative $\oplus$ TCO \\
}
{t & GRF, PRF \\
 b & GRF, PRF, FIT, CON \\
}
\instruction{MOV}
{Copy source to destination} % headline
{b, t} % syntax
{(t) $\leftarrow$ (b)} % operation
{1100 0010 0000 0bbb bbbt tttt (direct)\\
1100 011b bbbb bbbb bbbt tttt (immediate)} % opcode
{Copies the operand b to the target t. The immediate value is interpreted as 12 bit
unsigned.
\par For immediate only: If \hlink{IEXT} was executed before, additional 17 bits from the internal K-reg are used to extend the
immediate value to 29 bits (the last is used for sign extension).
The internal K-reg will be cleared.
\par t(11:0) $\leftarrow$ b, t(28:12) $\leftarrow$ K-reg, t(31:29) $\leftarrow$
K-reg(16), K-reg $\leftarrow$ 0
\par The assembler uses only bits (11:0) of the immediate constant. If there was not an \hlink{IEXT}
before and the immediate value is out of the 12 bit unsigned range, the assembler can
ignore this, print a warning or print an error message (configurable).
\minisec{Example}
{\ttfamily
\par; \textit{(direct)}
\par MOV CON[5], PRF[6]
\par ; \textit{(immediate, 12 bit)}
\par MOV ~0x03A, GRF[8];
\par ; \textit{(immediate, with extension)}
\par IEXT -4;
\par MOV~ -4, PRF[3];
\par ~
}
\par See \hlink{IEXT}, \hlink{MVPCR}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{Zero	  & - \\
 Carry    & - \\
 Negative & - \\
 TCO	  & - \\
 Signed   & - \\
}
{t & GRF, PRF \\
 b & GRF, PRF, FIT, CON \\
   & IMM12e, Label \\
}

\instruction{MVPCR}
{Copy PC+offset} % headline
{d, t} % syntax
{(t) $\leftarrow$ (b)} % operation
{1100 011b bbbb bbbb bbbt tttt} % opcode
{This a pseudoinstruction, in hardware is the same as \hlink{MOV} with immediate source operand. The assembler
interpretes d as an offset to the present program address:
\par immediate value (b) = present program address + offeset (d).
\minisec{Example}
{\ttfamily
\par; \textit{How to organize subroutines}
\par ~~~~~~MVPCR +2, PRF[7]; \textit{store the return address}
\par ~~~~~~JMP~~~ cc\_uncond, subr; \textit{jump to the subroutine}
\par ; \textit{continue the main program}
\par ~~~~~~ADD ...
\par ; \textit{the subroutine}
\par subr: ...
\par ; \textit{PRF[7] not changed in the subroutine!!!}
\par ~~~~~~JMP cc\_uncond, PRF[7]; \textit{return from subroutine}
\par ~
}
\par See \hlink{MOV}, \hlink{JMPR}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{Zero	  & - \\
 Carry    & - \\
 Negative & - \\
 TCO	  & - \\
 Signed   & - \\
}
{t & GRF, PRF \\
 d & PC\_OFFS \\
}


\instruction{JMP}
{All possible branches} % headline
{c, a} % syntax
{if condition c met then\\ PC~$\leftarrow$~(a)} % operation
{0000 1000 aaaa 0000 000c cccc (direct)\\
0000 010a aaaa aaaa aaac cccc  (immediate)} % opcode
{All possible branches, inclusive unconditional. If the condition is met, then load (a) into the program counter. In this case,
unlike most RISC processor, the instruction \textbf{following} the branch instruction \textbf{will
not be executed}.
The predefined conditions are listed at the beginning of this section. The old style
branch instructions:
\par~
\par \textbf{Conditional:} BZS, BZC, BSS, BSC, BVS, BVC, BNS, BNC, BCS, BCC, BBS,
BBC, BDS, BDC, BES, BEC (the second letter is for: Z-zero, S-signed, V-overflow, N-negative, C-carry, B-busy, D-divider busy,
E-error in divider; the third letter is for: S-set, C-cleared)
\par \textbf{Unconditional:} BRA
\par~
\par are still supported by the assembler, but not recommended for new programs.
\minisec{Example}
{\ttfamily
\par ~~~~~~~MOV GRF[4], PRF[1];
\par ~~~~~~~JMP cc\_zero, exit;
\par loop: ...
\par ~~~~~~~SUB PRF[1], CON[1], PRF[1]; PRF[1]--
\par ~~~~~~~JMP cc\_nzero, loop;
\par exit: ...
\par ~
}
\par See \hlink{JMPR}, \hlink{MVPCR}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{a & PRF\\
   & Label\\
c & cc\_cond\\
}

\instruction{JMPR}
{All possible branches, relative} % headline
{c, d} % syntax
{if condition c met then\\ PC~$\leftarrow$~(a)} % operation
{0000 010a aaaa aaaa aaac cccc} % opcode
{This is a pseudoinstruction, in hardware the same as \hlink{JMP} with immediate address. The
only difference is that the operand d here is interpreted as an offset relative to
the present program counter. The assembler computes the jump address as:
\par jump address (a) = present address + offeset (d).
\par The offeset can be positive (forward) or negative (backward). Zero means jump to
the same address. This is very useful to avoid writing many labels.
\minisec{Example}
{\ttfamily
\par ; \textit{a typical case where a lot of labels are used}
\par wait: JMP cc\_busy, wait; 
\par ; \textit{with JMPR it looks so :}
\par ~~~~~~~JMPR cc\_busy, 0; 
\par ~
}
\par See \hlink{JMP}, \hlink{MVPCR}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{d & PC\_OFFS\\
c & cc\_cond\\
}

\instruction{SEM}
{Set synchronisation Mask} % headline
{a} % syntax
{SMASK $\leftarrow$ a} % operation
{0001 0000 aaaa aaaa aaaa aaaa} % opcode
{Loads the internal SMASK register with a 16 bit constant.
\minisec{Example}
{\ttfamily
\par SEM b1000\_0000\_0000\_1000;
\par SYN;
\par ; \textit{The CPU will wait until some other}
\par ; \textit{CPU writes to GRF[3] and to GRF[15]}
}
\par See \hlink{SYT}, \hlink{SYN}, Chapter \ref{tp:sync}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{Zero	  & - \\
 Carry    & - \\
 Negative & - \\
 TCO	  & - \\
 Signed   & - \\
}
{a & IMM16 \\
}


\instruction{SYT}
{Copy synchronisation Mask} % headline
{t} % syntax
{t(15:0) $\leftarrow$ SMASK\\ t(31:16) $\leftarrow$ 0} % operation
{1100 1110 0000 0000 000t tttt} % opcode
{Stores the internal SMASK-reg zero-filled from left in one PRF or GRF register.
\minisec{Example}
{\ttfamily
\par \#def timeout=0x0ABE;
\par ~~~~~~~~...
\par ; \textit{Looping to check if some CPU has written}
\par ; \textit{to GRF[3] or GRF[15] and jump accordingly}
\par ; \textit{to different locations}
\par ~~~~~~~~SEM b1000\_0000\_0000\_1000;
\par ~~~~~~~~MOV timeout, PRF[2];
\par check: SUB PRF[2], CON[1], PRF[2];
\par ~~~~~~~~JMP cc\_zero, exit; \textit{timeout reached}
\par ~~~~~~~~SYT PRF[1]; \textit{copy SMASK to PRF[1]}
\par ~~~~~~~~SHLT -4, PRF[1]; \textit{copy bit 3 to carry}
\par ~~~~~~~~JMP cc\_ncarry, lab3; \textit{jump if bit 3 is 0}
\par ~~~~~~~~SHLT -16, PRF[1]; \textit{copy bit 15 to carry}
\par ~~~~~~~~JMP cc\_ncarry, lab15; \textit{jump if bit 15 is 0}
\par ~~~~~~~~JMP cc\_uncond, check;
\par exit: ...
\par ...
\par lab3: ~~...
\par ...
\par lab15: ~...
\par ~
}
\par See \hlink{SEM}, \hlink{SYN}, Chapter \ref{tp:sync}
} % description
{ \bul & - & \bul & - & \bul } % condition flags affected (\bul or -)
{Zero	  & set if t=0 \\
 Carry    & - \\
 Negative & MSB(t) \\
 TCO	  & - \\
 Signed   & Negative $\oplus$ TCO  \\
}
{t & GRF, PRF \\
}

\instruction{SYN}
{Synchonize} % headline
{} % syntax
{Synchonize, wait\\
until SMASK=0} % operation
{0000 1100 0000 0000 0000 0000} % opcode
{Suspends the CPU until the internal SMASK register is cleared or 
cold or warm RESET is asserted
or high level interrupt occurs.
\minisec{Example}
{\ttfamily
\par SEM b1000\_0000\_0000\_1000;
\par SYN;
\par ; \textit{The CPU will wait until some other}
\par ; \textit{CPU writes to GRF[3] and to GRF[15]}
}
\par See \hlink{SEM}, \hlink{SYN}, Chapter \ref{tp:sync}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{Zero	  & - \\
 Carry    & - \\
 Negative & - \\
 TCO	  & - \\
 Signed   & - \\
}
{none &\\
}

\instruction{LRA}
{Read from RAM} % headline
{m, t} % syntax
{t $\leftarrow$ RAM[PRF[15]], mode} % operation
{1101 001m m000 0000 0000 tttt} % opcode
{Read from RAM in 8/16/32 bit mode (see Figure \ref{fig:memr}). The address(1:0) will be masked with "10" and
"00" by 16 and 32 bit access. For 32 bit access mm="00", for 16 bit access mm="01",
for 8 bit access mm="11". These constants are predefined as rr\_dword, rr\_word,
rr\_byte. The PRF[15](11:2) must be not modified by the previous instruction - insert a NOP if necessary. 
If the previous instruction was \hlink{SRA} or \hlink{SRA+}, the RAM read will be undefined. The \hlink{LRA} and \hlink{LRA+} instructions
should be used in pairs, either LRA followed by \hlink{LRA}, or \hlink{LRA} followed by \hlink{LRA+}.
\minisec{Example}
{\ttfamily
\par IEXT 0x04030201;
\par MOV ~0x04030201, PRF[1];
\par SRA PRF[1], 8;

\par MOV 8|9|10|11, PRF[15];
\par NOP; \textit{wait 1 clock}
\par LRA rr\_dword, PRF[2]; \textit{read 32 bit,}
\par LRA rr\_dword, PRF[2]; 0x04030201

\par MOV 8|9|10|11, PRF[15];
\par NOP; \textit{wait 1 clock}
\par LRA rr\_word, ~PRF[6]; \textit{read 16 bit,}
\par LRA rr\_word, ~PRF[6]; 0x0201|0x0201|0x0403|0x0403

\par MOV 8|9|10|11, PRF[15];
\par NOP; \textit{wait 1 clock}
\par LRA rr\_byte, ~PRF[7]; \textit{read ~8 bit,}
\par LRA rr\_byte, ~PRF[7]; 0x01|0x02|0x03|0x04

\par ~
}
\par See \hlink{LRA+}, \hlink{SRA}, \hlink{SRA+}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{m & IMM2\\
t & PRF\\
}

\instruction{LRA+}
{Read from RAM with address autoincrement} % headline
{m, t} % syntax
{t $\leftarrow$ RAM[PRF[15]], mode\\
PRF[15](11:0)+=1/2/4} % operation
{1111 001m m000 0000 0000 tttt} % opcode
{Read from RAM in 8/16/32 bit mode (see Figure \ref{fig:memr}). The address(1:0) will be masked with "10" and
"00" by 16 and 32 bit access. For 32 bit access mm="00", for 16 bit access mm="01",
for 8 bit access mm="11". These constants are predefined as rr\_dword, rr\_word,
rr\_byte. The PRF[15](11:2) must be not modified by the previous instruction - insert a NOP if necessary. 
If the previous instruction was \hlink{SRA} or \hlink{SRA+}, the RAM read will be undefined. The \hlink{LRA} and
\hlink{LRA+} instructions
should be used in pairs, either \hlink{LRA} followed by \hlink{LRA}, or \hlink{LRA} followed by \hlink{LRA+}.
\par PRF[15] will be autoincremented by 1 in byte mode, by 2 in word mode and by 4
in dword mode.
\minisec{Example}
{\ttfamily
\par MOV ~0x0100, PRF[15];
\par NOP; \textit{wait 1 clock}
\par LRA ~rr\_dword, PRF[ 8];
\par LRA+ rr\_dword, PRF[ 8];
\par NOP; \textit{wait 1 clock}
\par LRA ~rr\_dword, PRF[ 9];
\par LRA+ rr\_dword, PRF[ 9];
\par ~
}
\par See \hlink{LRA}, \hlink{SRA}, \hlink{SRA+}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{m & IMM2\\
t & PRF\\
}

\instruction{SRA}
{Store in RAM} % headline
{a, t} % syntax
{RAM[t] $\leftarrow$ (a)} % operation
{0001 0100 aaaa 00tt ttt0 0000 (direct)\\
0100 0000 aaaa tttt tttt tttt (immediate)
} % opcode
{Store in RAM in 32 bit mode. The address bits (1:0) will be ignored. 
The next instruction may not be RAM read, otherwise the result will be undefined.
The SRA instruction should be not followed/preceed by an other \hlink{SRA}/\hlink{SRA+} instruction.
%The address should not be modified by the previous instruction.
\minisec{Example}
{\ttfamily
\par \#def daddr=0x40;
\par MOV 0x888, PRF[8];
\par SRA PRF[8], daddr; \textit{immediate}
\par ; 
\par MOV 32, PRF[15]; \textit{address}
\par NOP; \textit{wait 1 clock-?}
\par SRA+ PRF[8]; \textit{store PRF[8]}
\par NOP; \textit{wait 1 clock}
\par SRA+ PRF[9]; \textit{store PRF[9]}
\par ~
}
\par See \hlink{LRA}, \hlink{LRA+}, \hlink{SRA+}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{a & PRF (direct)\\
  & IMM12 (immediate)\\
t & PRF, GRF\\
}

\instruction{SRA+}
{Store in RAM with address autoincrement} % headline
{a} % syntax
{RAM[PRF[15]] $\leftarrow$ (a)\\
PRF[15](11:0)+=4} % operation
{0011 1000 aaaa 0000 0000 0000} % opcode
{Store in RAM in 32 bit mode. The address bits (1:0) will be
ignored. The next instruction may not be RAM read, otherwise the result will be undefined.
\par PRF[15] will be autoincremented by 4.
\minisec{Example}
{\ttfamily
\par \#def daddr=0x40;
\par MOV 0x888, PRF[8];
\par SRA PRF[8], daddr; \textit{immediate}
\par ; 
\par MOV 32, PRF[15]; \textit{address}
\par NOP; \textit{wait 1 clock-?}
\par SRA+ PRF[8]; \textit{store PRF[8]}
\par NOP; \textit{wait 1 clock}
\par SRA+ PRF[9]; \textit{store PRF[9]}
\par ~
}
\par See \hlink{LRA}, \hlink{LRA+}, \hlink{SRA}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{a & PRF\\
}

\instruction{LPIO}
{Load from privat I/O} % headline
{b, t} % syntax
{t $\leftarrow$ PIO[(b)]} % operation
{1110 0010 0000 00bb bbb0 tttt (direct)\\
1110 011b bbbb bbbb bbb0 tttt (immediate)
} % opcode
{Load from privat I/O. The address space is 12 bit only. Note that some peripherial devices (Event buffers, NI) latch synchronously the
address with the clock, the data can be latched by the CPU with the next clock. However, the
counter/timer and the global bus read buffer have no latency.
\minisec{Example}
{\ttfamily
\par ~~~~~\#def lcnt\_ctrl=0x201;
\par ~~~~~\#def lcnt\_dini=0x200;
\par ~~~~~\#def lcnt\_dout=0x202;
\par ~~~~~; \textit{using the counter/timer to measure}
\par ~~~~~; \textit{the time needed for some code segment}
\par ~~~~~MOV b\_0011\_0010\_1111, prf[4];
\par ~~~~~SPIO PRF[4], lcnt\_ctrl; \textit{init control reg}
\par ~~~~~SPIO PRF[4], lcnt\_dini; \textit{init data}
\par ~~~~~MOV 20, PRF[4]; \textit{loop length}
\par ~~~~~LPIO lcnt\_dout, PRF[1]; \textit{latch the start time}
\par ~~~~~;
\par tl: SUB PRF[4], CON[1], PRF[4]; \textit{test loop}
\par ~~~~~JMP cc\_nzero, tl
\par ~~~~~;
\par ~~~~~LPIO lcnt\_dout, PRF[2]; \textit{latch the stop time}
\par ~~~~~SUB prf[2], prf[1], prf[2]; \textit{get the difference}
\par ~~~~~;
\par ; PRF[2] \textit{should be :}
\par ; 19*(2(loop)+1(int nop))+
\par ; + 2(last loop)+1(load counter)
\par ~
}
\par See \hlink{LPIO+}, \hlink{SPIO}, Chapter \ref{tp:arch:lgio}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{b & PRF, GRF\\
  & IMM12\\
t & PRF\\
}

\instruction{LPIO+}
{Load from privat I/O with address autoincrement} % headline
{t} % syntax
{t $\leftarrow$ PIO[(b)]\\
PRF[14](11:0)++} % operation
{1110 1110 0000 0000 0000 tttt
} % opcode
{Load from privat I/O. The address is taken from PRF[14](11:0). PRF[14] will be
autoincremented by 1. Note that some peripherial devices (Event buffers, NI) latch synchronously the
address with the clock, the data can be latched by the CPU with the next clock. However, the
counter/timer and the global bus read buffer have no latency.
\minisec{Example}
{\ttfamily
\par ~~~~~~ \#def io\_inc\_addr=PRF[14];
\par ~~~~~~ \#def mem\_inc\_addr=PRF[15];
\par init: MOV 0x800, io\_inc\_addr; \textit{Event buffer}
\par ~~~~~~ MOV 0, mem\_inc\_addr
\par read: LPIO+ PRF[0]; \textit{dummy read}
\par ~~~~~~ LPIO+ PRF[0]; \textit{EB[0]}
\par ~~~~~~ LPIO+ PRF[1]; \textit{EB[1]}
\par ~~~~~~ LPIO+ PRF[2]; \textit{EB[2]}
\par ~~~~~~ LPIO+ PRF[3]; \textit{EB[3]}
\par ~~~~~~ ; \textit{the last two instructions could be}
\par ~~~~~~ ; LPIO io\_inc\_addr, PRF[2]; \textit{EB[2]}
\par ~~~~~~ ; LPIO n, PRF[3]; \textit{EB[3]}
\par ~~~~~~ ; \textit{where n is a random number!}
\par ~~~~~~ SRA+ PRF[0]
\par ~~~~~~ SRA+ PRF[1]
\par ~~~~~~ SRA+ PRF[2]
\par ~~~~~~ SRA+ PRF[3]
\par ~
}
\par See \hlink{LPIO}, \hlink{SPIO}, Chapter \ref{tp:arch:lgio}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{t & PRF\\
}

\instruction{SPIO}
{Store in privat I/O} % headline
{a, t} % syntax
{PIO[t] $\leftarrow$ (a)} % operation
{0100 0100 aaaa 00tt ttt0 0000 (direct)\\
0010 0000 aaaa tttt tttt tttt (immediate)
} % opcode
{Store in privat I/O. In the case of direct addressing, only bits (11:0) will be used
for the address.
\minisec{Example}
{\ttfamily
\par \#def lcnt\_ctrl=0x201;
\par \#def lcnt\_dini=0x200;
\par ; \textit{initialize the counter/timer}
\par MOV~ b\_0011\_0010\_1111, prf[4];
\par SPIO PRF[4], lcnt\_ctrl; \textit{control reg}
\par MOV~ 0, PRF[4];
\par SPIO PRF[4], lcnt\_dini; \textit{init data}
}
\par ~
\par See \hlink{LPIO}, \hlink{LPIO+}, Chapter \ref{tp:arch:lgio}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{a & PRF (direct)\\
t & PRF, GRF\\
  & IMM12 (immediate)\\
}

\instruction{LGIO}
{Load from global I/O} % headline
{t, b} % syntax
{PIO[0x300+t] $\leftarrow$ GIO[(b)]} % operation
{1110 100t 0000 00bb bbb0 0000 (direct)\\
1110 110t bbbb bbbb bbbb bbbb (immediate)
} % opcode
{Request from the arbiter to read from global I/O. The address space is 16 bit.
In the case of direct addressing, only bits (15:0) will be used for the address.
The Arbiter will store the requested data in one of the two special global bus read
buffers in the privat I/O at addresses 0x300 or 0x301 (depending on t). The convention
is to use 0x300 (t=0) in normal programs and 0x301 (t=1) in interrupt procedures.
The CPU can check if the requested read is done by using the special Busy flag.
It will be set by the \hlink{LGIO} or \hlink{LGIO+} and cleared when the data are available. Note that
the arbiter is not pipelined, a second read request from the same CPU will overwrite the address stored
with the first request of this CPU.
\minisec{Example}
{\ttfamily
\par ~~~~~~~\#def gbus\_rbuf0=0x300;
\par ~~~~~~~LGIO 0, 0xD002
\par wait: JMP cc\_busy, wait; 
\par ~~~~~~~LPIO gbus\_rbuf0, PRF[1];
\par ~~~~~~~; \textit{after reset at} 0xD002 \textit{should be 8}
}
\par See \hlink{LGIO+}, \hlink{SGIO}, \hlink{SGIO+}, \hlink{LPIO}, Chapter \ref{tp:arch:lgio}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{b & PRF, GRF\\
  & IMM16\\
t & IMM1\\
}

\instruction{LGIO+}
{Load from global I/O with address autoincrement} % headline
{t} % syntax
{PIO[0x300+t] $\leftarrow$ GIO[PRF[14](15:0)]\\
PRF[14](11:0)++} % operation
{1111 010t 0000 0000 0000 0000} % opcode
{Request from the arbiter to read from global I/O. The address space is 16 bit.
Only bits (15:0) of PRF[14] will be used for the address and then incremented by
1.
The Arbiter will store the requested data in one of the two special global bus read
buffers in the privat I/O at addresses 0x300 or 0x301 (depending on t). The convention
is to use 0x300 (t=0) in normal programs and 0x301 (t=1) in interrupt procedures.
The CPU can check if the requested read is done by using the special Busy flag.
It will be set by the \hlink{LGIO} or \hlink{LGIO+} and cleared when the data are available. Note that
the arbiter is not pipelined, a second read/write request from the same CPU will overwrite the address stored
with the first request of this CPU.
\minisec{Example}
{\ttfamily
\par ~~~~~IEXT 0x3100; \textit{non-lin LUT begin}
\par ~~~~~MOV~ 0x3100, PRF[14];
\par ~~~~~IEXT 0x3140; \textit{non-lin LUT end+}
\par ~~~~~MOV~ 0x3140, PRF[10];
\par ~~~~~MOV~ 0, PRF[15];
\par ; \textit{copy non-lin LUT to RAM}
\par rn: LGIO+ 0;
\par r1: JMP~ cc\_busy, r1; \textit{wait}
\par ; \textit{read from global bus read buffer 0 in local I/O}
\par ~~~~~LPIO 0x300, PRF[4];
\par ~~~~~SRA+ PRF[4];
\par ~~~~~CMP~ PRF[14], PRF[10];
\par ~~~~~JMP~ cc\_nzero, rn;
}
\par See \hlink{LGIO}, \hlink{SGIO}, \hlink{SGIO+}, \hlink{LPIO}, Chapter \ref{tp:arch:lgio}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{t & IMM1\\
}

\instruction{SGIO}
{Store to global I/O} % headline
{a, t} % syntax
{GIO[t] $\leftarrow$ (a)} % operation
{0010 0100 aaaa 00tt ttt0 0000 (direct)\\
0010 1000 aaaa tttt tttt tttt (immediate)
} % opcode
{Request the arbiter to store to the global I/O. The address space is 16 bit.
In the case of direct addressing, only bits (15:0) will be used for the address.
In the case of immediate addressing, the missing 4 bits (15:12) are loadable through
the instruction \hlink{IEXT} (see \hlink{MOV}, \hlink{CMP}), otherwise are "0000".
The Arbiter stores first the write data and the address in internal registers.
The CPU can check if the requested write is done by using the special Busy flag.
It will be set by \hlink{SGIO} or \hlink{SGIO+} and cleared when the data are written to the I/O device. Note that
the arbiter is not pipelined, a second read/write request from the same CPU will
overwrite the address/write data stored with the first request of this CPU.
\minisec{Example}
{\ttfamily
\par \#def IM\_DM\_CNF=0xD000;
\par ; \textit{prepare to copy IMEM1 do DMEM}
\par MOV~  b\_01\_1, PRF[1]; \textit{read bank 1 of IMEM}
\par IEXT IM\_DM\_CNF;
\par SGIO PRF[1], IM\_DM\_CNF;
\par ; \textit{an other possibility}
\par IEXT IM\_DM\_CNF;
\par MOV~ IM\_DM\_CNF, PRF[2];
\par SGIO PRF[1], PRF[2];
}
\par See \hlink{LGIO}, \hlink{LGIO+}, \hlink{SGIO+}, \hlink{IEXT}, \hlink{MOV}, Chapter \ref{tp:arch:lgio}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{a & PRF\\
t & PRF, GRF\\
  & IMM12e\\
}

\instruction{SGIO+}
{Store to global I/O with address autoincrement} % headline
{a} % syntax
{GIO[PRF[14](15:0)] $\leftarrow$ (a)\\
PRF[14](11:0)++} % operation
{0011 1100 aaaa 0000 0000 0000} % opcode
{Request the arbiter to store to the global I/O. The address space is 16 bit.
PRF[14](15:0) will be used for the address and then incremented by 1.
The Arbiter stores first the write data and the address in internal registers.
The CPU can check if the requested write is done by using the special Busy flag.
It will be set by \hlink{SGIO} or \hlink{SGIO+} and cleared when the data are written to the I/O device. Note that
the arbiter is not pipelined, a second read/write request from the same CPU will
overwrite the address/write data stored with the first request of this CPU.
\minisec{Example}
{\ttfamily
\par ; \textit{write 0,1,2... to the non-lin LUT (6 bit)}
\par ~~~~~IEXT~ 0x3100; \textit{non-lin LUT start address}
\par ~~~~~MOV~~ 0x3100, PRF[14];
\par ~~~~~IEXT~ 0x3140; \textit{non-lin LUT end address+}
\par ~~~~~MOV~~ 0x3140, PRF[10];
\par wn: JMP~~ cc\_busy\ wn; \textit{wait}
\par ~~~~~SGIO+ PRF[14]; GIO[PRF[14]]=PRF[14], PRF[14]++
\par ~~~~~CMP~~ PRF[14], PRF[10];
\par ~~~~~JMP~~ cc\_nzero, wn;
\par ~
}
\par See \hlink{LGIO}, \hlink{LGIO+}, \hlink{SGIO}, Chapter \ref{tp:arch:lgio}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{a & PRF}

\instruction{CLI}
{Disable low priority interrputs} % headline
{} % syntax
{} % operation
{0010 1100 0000 0000 0000 0000} % opcode
{Disable the low priority interrupts.  Note that the interrupt controller doens't
accept a second low level interrupt while already responding to a low level interrupt
and \hlink{IRT} was not executed.
So, it is not necessary to disable interrupts with CLI at the beginning of interrupt
routine. Even after CLI the interrupt controller will respond to high level
interrupts.
After reset the low level interrupts are disabled.
\minisec{Example}
{\ttfamily
\par ; \textit{Disable low priority interrupts}
\par CLI
\par ...
\par ; \textit{Enable low priority interrupts}
\par STI
\par ~
}
\par See \hlink{STI}, \hlink{INT}, \hlink{IRQCLR}, \hlink{COPIRQ}, \hlink{IRT}, Chapter \ref{tp:intr}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{none}

\instruction{STI}
{Enable low priority interrputs} % headline
{} % syntax
{} % operation
{0011 0000 0000 0000 0000 0000} % opcode
{Enable the low priority interrupts. After reset the low level interrupts are disabled.
\minisec{Example}
{\ttfamily
\par ; \textit{Disable low priority interrupts}
\par CLI
\par ...
\par ; \textit{Enable low priority interrupts}
\par STI
\par ~
}
\par See \hlink{CLI}, \hlink{INT}, \hlink{IRQCLR}, \hlink{COPIRQ}, IRT, Chapter \ref{tp:intr}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{none}

\instruction{INT}
{Activate a software interrupt} % headline
{b} % syntax
{Irq inputs $\leftarrow$ (b)} % operation
{0100 1100 bbbb bbbb bbbb bbbb
} % opcode
{The 13-bit immediate value will be OR-ed with the interrupt inputs and then masked. So it is
possible to start an interrupt routine, or even more than one interrupt routine. Note
that INT is not equivalent to \hlink{JMP} to the corresponding address and return to the next
address after \hlink{IRT}! Without the two \hlink{NOP}s after INT in the example, \hlink{SRA+} dumps the old
values of PRF[1], because the interrupt controller needs two clocks to start the
interrupt procedure.
\minisec{Example}
{\ttfamily
\par ~~~~~~MOV irq, PRF[1];
\par ~~~~~~SGIO PRF[1], 0x0B06; \textit{irq cnt start address}
\par wt2: JMP cc\_busy wt2;
\par ~~~~~~STI; \textit{enable low level interrupts}
\par ~~~~~~SRA+ PRF[1]; \textit{now PRF[1] is} 0x50
\par ~~~~~~INT b0100\_0000;
\par ~~~~~~NOP;
\par ~~~~~~NOP;
\par ~~~~~~SRA+ PRF[1]; \textit{now PRF[1] is} 0x51
\par ~~~~~~INT b0100\_0000;
\par ~~~~~~NOP;
\par ~~~~~~NOP;
\par ~~~~~~SRA+ PRF[1]; \textit{now PRF[1] is} 0x52
\par ~~~~~~...
\par ORG 0x50; \textit{continue assembling from address} 0x50
\par irq: ADD PRF[1], CON[1], PRF[1];
\par ~~~~~ IRT
\par ~
}
\par See \hlink{CLI}, \hlink{STI}, \hlink{IRQCLR}, \hlink{COPIRQ}, \hlink{IRT}, Chapter \ref{tp:intr}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{b & IMM13
}

\instruction{COPIRQ}
{Copy the interrupt requests} % headline
{t} % syntax
{(t) $\leftarrow$ IRQ(12:0)} % operation
{0100 1110 0000 0000 000t tttt} % opcode
{Copy the stored interrupt requests to a PRF or GRF. Only the enabled interrupt
requests will be stored. In the next example COPIRQ is used to test when exactly
starts the software interrupt.
\minisec{Example}
{\ttfamily
\par ~~~~~~MOV b0100\_0000, PRF[1]; \textit{only IRQ6 is enabled}
\par ~~~~~~SGIO PRF[1], 0x0B0D; \textit{irq soft en mask}
\par wt1: JMP cc\_busy wt1;
\par ~~~~~~MOV irq, PRF[1];
\par ~~~~~~SGIO PRF[1], 0x0B06; \textit{irq cnt start address}
\par wt2: JMP cc\_busy wt2;
\par ~~~~~~STI; \textit{enable low level interrupts}
\par ~~~~~~SRA+ PRF[1]; \textit{now PRF[1] is} 0x50
\par ~~~~~~INT b0100\_1010; \textit{IRQ1 and IRQ3 will be masked}
\par ~~~~~~COPIRQ PRF[2]; \textit{executed before the IRQ}
\par ~~~~~~COPIRQ PRF[3]; \textit{executed before the IRQ}
\par ~~~~~~COPIRQ PRF[4]; \textit{executed after the IRQ}
\par ~~~~~~SRA+ PRF[1]; 0x51
\par ~~~~~~SRA+ PRF[2]; 0x40 - \textit{only IRQ6 is active}
\par ~~~~~~SRA+ PRF[3]; 0x40 - \textit{only IRQ6 is active}
\par ~~~~~~SRA+ PRF[4]; 0x00 - \textit{no IRQ is inactive}
\par ~~~~~~...
\par ORG 0x50; \textit{continue assembling from address} 0x50
\par irq: ADD PRF[1], CON[1], PRF[1];
\par ~~~~~ IRT
\par ~
}
\par See \hlink{CLI}, \hlink{STI}, \hlink{INT}, \hlink{IRQCLR}, \hlink{IRT}, Chapter \ref{tp:intr}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{t & PRF, GRF
}

\instruction{IRQCLR}
{Clear interrupt request} % headline
{b} % syntax
{StoredIRQs  $\leftarrow$ ($\overline{\textnormal{b}}$) \& StoredIRQs} % operation
{1100 1100 bbbb bbbb bbbb bbbb} % opcode
{The inverted 16-bit immediate value will be AND-ed with the stored interrupts 
and stored as interrupt requests. So it is possible to clear some or all other requests
in an interrupt procedure.
\minisec{Example}
{\ttfamily
\par ~~~~~~MOV b1100\_0000, PRF[1]; \textit{only IRQ6,7 are enabled}
\par ~~~~~~SGIO PRF[1], 0x0B0D; \textit{irq soft enable mask}
\par wt1: JMP cc\_busy wt1;
\par ~~~~~~MOV irq, PRF[1];
\par ~~~~~~SGIO PRF[1], 0x0B06; \textit{irq cnt start address}
\par wt2: JMP cc\_busy wt2;
\par ~~~~~~STI; \textit{enable low level interrupts}
\par ~~~~~~SRA+ PRF[1]; \textit{now PRF[1] is} 0x50
\par ~~~~~~INT b1100\_1010; \textit{IRQ1 and IRQ3 will be masked}
\par ~~~~~~COPIRQ PRF[2]; \textit{executed before the IRQ proc}
\par ~~~~~~COPIRQ PRF[3]; \textit{executed before the IRQ proc}
\par ~~~~~~COPIRQ PRF[4]; \textit{executed after the IRQ proc}
\par ~~~~~~SRA+ PRF[1]; 0x51
\par ~~~~~~SRA+ PRF[2]; 0xC0 - IRQ6,7 are active
\par ~~~~~~SRA+ PRF[3]; 0xC0 - IRQ6,7 are active
\par ~~~~~~SRA+ PRF[4]; 0x00 - no IRQ is inactive
\par ~~~~~~...
\par ORG 0x50; \textit{continue assembling from address} 0x50
\par irq: ADD PRF[1], CON[1], PRF[1];
\par ~~~~~~IRQCLR b1000\_0000; \textit{clear IRQ7}
\par ~~~~~ IRT
\par ~
}
\par See \hlink{CLI}, \hlink{STI}, \hlink{INT}, \hlink{COPIRQ}, \hlink{IRT}, Chapter \ref{tp:intr}
} % description
{ - & - & - & - & - } % condition flags affected (\bul or -)
{}
{b & IMM16
}

\instruction{IRT}
{Return from interrupt} % headline
{} % syntax
{} % operation
{0011 0100 0000 0000 0000 0000} % opcode
{Return from interrupt. Restore the flags and copy the return address to the program
counter.
\minisec{Example}
{\ttfamily
\par irq: ...
\par ~~~~~ ...
\par ~~~~~ IRT
\par ~
}
\par See \hlink{CLI}, \hlink{STI}, \hlink{INT}, \hlink{IRQCLR}, \hlink{COPIRQ}, Chapter \ref{tp:intr}
} % description
{ \bul & \bul & \bul & \bul & \bul } % condition flags affected (\bul or -)
{Zero	  & restored to the state before the IRQ \\
 Carry    & restored to the state before the IRQ \\
 Negative & restored to the state before the IRQ \\
 TCO	  & restored to the state before the IRQ \\
 Signed   & restored to the state before the IRQ \\
}
{none}
