\chapter{Global State Machine}
\label{sm}


%-----------------------------------------------------------------------------
\section{State Diagramm}
\label{sm:dia}

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|l|c|c|l|}\hline
state name & binary & hex & Description \\ \hline
low\_powr & 0000 & 0 & Low power state \\ \hline
test\_chk & 0001 & 1 & Test mode \\ \hline
wait\_pre & 0011 & 3 & Wait for pretrigger \\ \hline
preproc   & 0111 & 7 & Preprocessor is running \\ \hline
tr\_proc  & 1111 & F & CPUs proceed the tracklets \\ \hline
tr\_send  & 1110 & E & Send the tracklet information \\ \hline
wait\_L1  & 1100 & C & Wait for the L1 accept \\ \hline
zero\_sp  & 1000 & 8 & CPUs make zero suppression \\ \hline
full\_rd  & 1001 & 9 & Full readout \\ \hline
clear\_st & 1011 & B & Clear, prepare for the next event \\ \hline
\end{tabular}
\caption[Global states]
{Global states}
\label{tab:gsmstates}
\end{table}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_sm/TRAP_States.eps}
 \caption[State diagram of the global state machine]{State diagram of the global state machine}
 \label{fig:gsmstates}
\end{figure}

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|c|l|l|}\hline
Code & Name & Description\\\hline\hline
1 & pretrigger & Pretrigger or L0A or L1A\\\hline
2 & clear & Clear, the state machines goes to clear state\\\hline
3 & reserved & Reserved, can be counted in TRAP\\\hline
4 & low\_power & The state machine goes to low power state\\\hline
5 & acq & The state machine goes to acquisition state, switch the ADCs and filter clock on\\\hline
6 & test & Activate the test interrupt\\\hline
7 & pasap & Start PASA test pulse and trigger\\\hline
\end{tabular}
\caption[Pretrigger commands]{Pretrigger commands.}
 \label{tab:pretrpci}
\end{table}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_sm/pretr.eps}
 \caption[Pretrigger commands]{Pretrigger commands}
 \label{fig:pretrcmd}
\end{figure}


%blabla \reg{SML0.t} bla.
%-----------------------------------------------------------------------------
\section{Global I/O Programming Model}
\label{sm:pm}

\register{SML0}{0x0A00}{GSM level 0 time and ignore}
{Register to set the time for the level 0 accept and ignore}
{SSSS RRRR RR-- ---- -itt tttt tttt tttt}
{0000 0000 00-- ---- -100 0000 0101 0000}
{t & time in TRAP clocks for L0 accept. If a pretrigger comes in the time window 
 (SML0.time , SML0.time+SMMODE.delta) or the ignore bit is set, a L0A (accept) will be generated, 
 otherwise L0R will be generated.\\
i & ignore L0 reject\\
  S & state - read only (see Table \ref{tab:gsmstates}) \\
 R & reject state - read only, L2A, L2R, L1A, L1R, L0A, L0R\\
}

\register{SML1}{0x0A01}{GSM level 1 time and ignore}
{Register to set the time for the level 1 accept and ignore}
{SSSS RRRR RR-- ---- -itt tttt tttt tttt}
{0000 0000 00-- ---- -100 0010 0000 0000}
{t & time in TRAP clocks for L1 accept. If a pretrigger comes in the time window 
 (SML1.time , SML1.time+SMMODE.delta) or the ignore bit is set, a L1A (accept) will be
 generated, otherwise L1R will be generated.\\
i & ignore L1 reject \\
 S & state - read only (see Table \ref{tab:gsmstates}) \\
 R & reject state - read only, L2A, L2R, L1A, L1R, L0A, L0R\\
}

\register{SML2}{0x0A02}{GSM level 2 time and ignore}
{Register to set the time for the level 1 accept and ignore}
{SSSS RRRR RR-- ---- -itt tttt tttt tttt}
{0000 0000 00-- ---- -100 0011 1000 0100}
{t & time in TRAP clocks for L2 accept. If a pretrigger comes in the time window 
 (SML1.time , SML1.time+SMMODE.delta) or the ignore bit is set, a L2A (accept) will be
 generated, otherwise L2R will be generated.\\
 i & ignore L2 reject \\
 S & state - read only (see Table \ref{tab:gsmstates}) \\
 R & reject state - read only, L2A, L2R, L1A, L1R, L0A, L0R\\
}

\register{SMMODE}{0x0A03}{GSM mode bits}
{Register for different operation modes}
{SSSS RRRR RR-- ---- pppp snme eeee dddd}
{0000 0000 00-- ---- 1111 0000 1110 0010}
{p & Enable network interface input ports 3..0\\
 s & Simulation flag, must be set in order to have read clock to the event buffers when
the CPUs are off. Otherwise the event buffers have read clock only when the
corresponding CPU is on.\\
 n & No CPU flag. When this flag is set the master state machine will not wait
 for CPU done command to switch from tr\_proc to tr\_send and from zero\_sp
 to full\_rd states \\
 m & Merger only flag, when set the ADCs will be disabled. The state machine
 will use its own bintimer instead of the bintimer of the preprocessor. \\
 e & EOD2CPU\_delay specifies the delay between the before last preprocessor clock and the
CPU start (in fast clocks). If MergerOnly is '1' this value will be used to set the
number of timebins.\\
 d & Delta time, the max variation of L0, L1 and L2 time, see SML0, SML1, SML2\\
 S & state - read only (see Table \ref{tab:gsmstates}) \\
 R & reject state - read only, L2A, L2R, L1A, L1R, L0A, 
 L0R - the Rs usable only for simulations, as the state machine will enter the clear state
 immediately and all reject state bits will be cleared\\
}

\register{SMCMD}{0x0A04}{GSM command register}
{Command register for different commands, write only}
{---- ---- ---- ---- cccc cccc cccc cccc}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & Writing to this address the proper code will
execute the corresponding command, see Table \ref{tab:gsmcmd}\\
}

Note: When reading from all registers (not only 0x0A00..0x0A03), the upper bits
will be filled with the status of the state machine and reject/accept flags.
In addition, when reading from the command registers (0x0A04 .. 0x0A07), bits 11..0 
show directly the status of the clocks and enables.

\register{SM all}{0x0Axx}{Reading from all state machine registers}
{Reading from all state machine registers}
{SSSS RRRR RR-- ---- ---- EEEE EEEE EEEE}
{0000 0000 00-- ---- ---- 0000 0000 0000}
{S & state, see Table \ref{tab:gsmstates} \\
 R & reject state L2A, L2R, L1A, L1R, L0A, L0R\\
 E & status of the corresponding clock or enable, see Table \ref{tab:gsmonoff}\\
}

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|l|c|l|}\hline
command name & code & Description \\ \hline
lp         & 0x0012 & go to low power state \\ \hline
acq        & 0x0112 & go to acquisition state\\ \hline
chk\_tst   & 0x0212 & go to test mode \\ \hline
ext\_clr   & 0x0312 & exit clear state \\ \hline
clear      & 0x0412 & go to clear state \\ \hline
pretrigg   & 0x0512 & internally generate pretrigger\\ \hline
selftp     & 0x0612 & start the self-test state machine \\ \hline
CPU\_done  & 0x0712 & CPU finished the tracklet processing or raw data compression \\ \hline
\end{tabular}
\caption[Commands to the global state machine]
{Commands to the global state machine}
\label{tab:gsmcmd}
\end{table}

\register{SMOFFON}{0x0A05}{GSM command register for switching clock/enable}
{Command register for switching clock/enable, write only}
{---- ---- cccc cccc cccc ssss ssss ssss}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & off mask, see Table \ref{tab:gsmonoff}\\
 s & on mask, see Table \ref{tab:gsmonoff}\\
}

\register{SMON}{0x0A06}{GSM command register for switching on clock/enable}
{Command register for switching on clock/enable, write only}
{---- ---- ---- ---- ---- ssss ssss ssss}
{---- ---- ---- ---- ---- ---- ---- ----}
{s & on mask, see Table \ref{tab:gsmonoff}\\
}

\register{SMOFF}{0x0A07}{GSM command register for switching off clock/enable}
{Command register for switching off clock/enable, write only}
{---- ---- ---- ---- ---- cccc cccc cccc}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & off mask, see Table \ref{tab:gsmonoff}\\
}

Note: SMOFFON, SMON, SMOFF command registers can be used to switch simultaneously all
clocks and/or enables controlled by the configuration registers from 
Table \ref{tab:gsmonoff}. For each separate clock or enable, switching on/off is possible
only if the mm bits in the corresponding configuration register are "11".

\register{NITM0}{0x0A08}{NI timer 0}
{NI timer 0}
{---- ---- ---- ---- --tt tttt tttt tttt}
{---- ---- ---- ---- --11 1111 1111 1111}
{t & time [CPU clocks] after pretrigger for switching NI and CPU clock on, NI input and output
control ports and NI output data port on and for generating CPU done\\
}

\register{NITM1}{0x0A09}{NI timer 1}
{NI timer 1}
{---- ---- ---- ---- --tt tttt tttt tttt}
{---- ---- ---- ---- --11 1111 1111 1111}
{t & time [CPU clocks] after pretrigger for switching NI input data ports on\\
}

\register{NITM2}{0x0A0A}{NI timer 2}
{NI timer 2}
{---- ---- ---- ---- --tt tttt tttt tttt}
{---- ---- ---- ---- --11 1111 1111 1111}
{t & time [CPU clocks] after pretrigger for switching NI and CPU clock on, NI input and output
control ports on and for generating CPU done\\
}

Note: The t-bit in the corresponding NICLK, NIODE, NIOCE, NIIDE, NIICE configuration
register must be set in order to use the timers 0..2.

\register{NIP4D}{0x0A0B}{NI output port enable}
{NI output port enable}
{---- ---- ---- ---- ---- ---- bnnn ffff}
{---- ---- ---- ---- ---- ---- 0111 1111}
{b & bypass the NI\_P4\_CTRL signal\\
 n & The NI\_P4 data cells are switched on with the high to low transition of 
 the NI\_P4\_CTRL input, the internal NI\_P4\_CTRL is delayed by nnn clocks\\
 f & The internal NI\_P4\_CTRL is set immediately with the low to high transition 
 of the NI\_P4\_CTRL input, the NI\_P4 data cells are switched off after ffff clocks\\
}

Note: nnn and ffff are ignored in the case of bypass set. In order to switch on/off
the NI\_P4 data cells the bits t/o in the NIODE register must be set,
as well as the bits mm must be "11".

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|l|c|c|l|}\hline
Baseaddress & Bit \# in on/off mask register & Description \\ \hline
{\ttfamily} 0x0A20 & 0 & Clock CPU 0\\ \hline
{\ttfamily} 0x0A22 & 1 & Clock CPU 1\\ \hline
{\ttfamily} 0x0A24 & 2 & Clock CPU 2\\ \hline
{\ttfamily} 0x0A26 & 3 & Clock CPU 3\\ \hline
{\ttfamily} 0x0A28 & 4 & Clock NI\\ \hline
{\ttfamily} 0x0A2A & 5 & Clock Digital Filter\\ \hline
{\ttfamily} 0x0A2C & 6 & Clock Preprocessor\\ \hline
{\ttfamily} 0x0A2E & 7 & ADC Enable\\ \hline
{\ttfamily} 0x0A30 & 8 & NI output data port\\ \hline
{\ttfamily} 0x0A32 & 9 & NI output control port\\ \hline
{\ttfamily} 0x0A34 & 10 & NI input data ports\\ \hline
{\ttfamily} 0x0A36 & 11 & NI input control ports\\ \hline
\end{tabular}
\caption[Baseaddresses for switching clocks and LVDS pins]
{Baseaddresses for switching clocks and LVDS pins}
\label{tab:gsmonoff}
\end{table}

\register{CPU0CLK}{0x0A20}{Configuration of the CPU 0 clock}
{Register to configure how to switch the clock of CPU 0 on and off}
{---- ---- ---- ---- ---- ---- --St oamm}
{---- ---- ---- ---- ---- ---- --00 0111}
{t & enable switching on the CPU 0 by a high-level interrupt or NITM0 or NITM2\\
o & enables switching off the CPU 0 by the command ext\_clr, see Table \ref{tab:gsmcmd}\\
a & enable that the global state machine turns CPU 0 clock on/off when its own
control output for CPU 0 clock makes a transition\\
m & "00" - permanently off (t, o and a are ignored), "01" - permanently on (t, o and a are ignored), 
"10" - controlled by the global state machine directly (t, o and a are ignored),
"11" - controlled by transitions in global state machine outputs (if a is set),
writing to the start-stop register CPU0SS, SMOFFON, SMON, SMOFF and the cases
enabled by bits t and o\\
S & state - read only, 1 - on, 0 - off\\
}

\register{CPU0SS}{0x0A21}{Switch the clock of CPU 0}
{Command register to switch the clock of CPU 0 on and off}
{---- ---- ---- ---- ---- ---- ---- ---c}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & turn the CPU 0 clock on/off when 1/0 (write only). The mm field in CPU0CLK must be "11".\\
}

\register{CPU1CLK}{0x0A22}{Configuration of the CPU 1 clock}
{Register to configure how to switch the clock of CPU 1 on and off}
{---- ---- ---- ---- ---- ---- --St oamm}
{---- ---- ---- ---- ---- ---- --00 0111}
{t & enable switching on the CPU 1 by a high-level interrupt or NITM0 or NITM2\\
o & enables switching off the CPU 1 by the command ext\_clr, see Table \ref{tab:gsmcmd}\\
a & enable that the global state machine turns CPU 1 clock on/off when its own
control output for CPU 0 clock makes a transition\\
m & "00" - permanently off (t, o and a are ignored), "01" - permanently on (t, o and a are ignored), 
"10" - controlled by the global state machine directly (t, o and a are ignored),
"11" - controlled by transitions in global state machine outputs (if a is set),
writing to the start-stop register CPU1SS, SMOFFON, SMON, SMOFF and the cases
enabled by bits t and o\\
S & state - read only, 1 - on, 0 - off\\
}

\register{CPU1SS}{0x0A23}{Switch the clock of CPU 1}
{Command register to switch the clock of CPU 1 on and off}
{---- ---- ---- ---- ---- ---- ---- ---c}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & turn the CPU 1 clock on/off when 1/0 (write only). The mm field in CPU1CLK must be "11".\\
}

\register{CPU2CLK}{0x0A24}{Configuration of the CPU 2 clock}
{Register to configure how to switch the clock of CPU 2 on and off}
{---- ---- ---- ---- ---- ---- --St oamm}
{---- ---- ---- ---- ---- ---- --00 0111}
{t & enable switching on the CPU 2 by a high-level interrupt or NITM0 or NITM2\\
o & enables switching off the CPU 2 by the command ext\_clr, see Table \ref{tab:gsmcmd}\\
a & enable that the global state machine turns CPU 0 clock on/off when its own
control output for CPU 0 clock makes a transition\\
m & "00" - permanently off (t, o and a are ignored), "01" - permanently on (t, o and a are ignored), 
"10" - controlled by the global state machine directly (t, o and a are ignored),
"11" - controlled by transitions in global state machine outputs (if a is set),
writing to the start-stop register CPU2SS, SMOFFON, SMON, SMOFF and the cases
enabled by bits t and o\\
S & state - read only, 1 - on, 0 - off\\
}

\register{CPU2SS}{0x0A25}{Switch the clock of CPU 2}
{Command register to switch the clock of CPU 2 on and off}
{---- ---- ---- ---- ---- ---- ---- ---c}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & turn the CPU 2 clock on/off when 1/0 (write only). The mm field in CPU2CLK must be "11".\\
}

\register{CPU3CLK}{0x0A26}{Configuration of the CPU 3 clock}
{Register to configure how to switch the clock of CPU 3 on and off}
{---- ---- ---- ---- ---- ---- --St oamm}
{---- ---- ---- ---- ---- ---- --00 0111}
{t & enable switching on the CPU 3 by a high-level interrupt or NITM0 or NITM2\\
o & enables switching off the CPU 3 by the command ext\_clr, see Table \ref{tab:gsmcmd}\\
a & enable that the global state machine turns CPU 0 clock on/off when its own
control output for CPU 0 clock makes a transition\\
m & "00" - permanently off (t, o and a are ignored), "01" - permanently on (t, o and a are ignored), 
"10" - controlled by the global state machine directly (t, o and a are ignored),
"11" - controlled by transitions in global state machine outputs (if a is set),
writing to the start-stop register CPU3SS, SMOFFON, SMON, SMOFF and the cases
enabled by bits t and o\\
S & state - read only, 1 - on, 0 - off\\
}

\register{CPU3SS}{0x0A27}{Switch the clock of CPU 3}
{Command register to switch the clock of CPU 3 on and off}
{---- ---- ---- ---- ---- ---- ---- ---c}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & turn the CPU 3 clock on/off when 1/0 (write only). The mm field in CPU3CLK must be "11".\\
}

\register{NICLK}{0x0A28}{Configuration of the NI clock}
{Register to configure how to switch the clock of NI on and off}
{---- ---- ---- ---- ---- ---- --St oamm}
{---- ---- ---- ---- ---- ---- --00 0111}
{t & enable switching on by NITM0 or NITM2\\
o & enable switching off when NI state machine sends done to the global state
machine\\
a & enable that the global state machine turns NI clock on/off when its own
control output for NI clock makes a transition\\
m & "00" - permanently off (t, o and a are ignored), "01" - permanently on (t, o and a are ignored), 
"10" - controlled by the global state machine directly (t, o and a are ignored),
"11" - controlled by transitions in global state
machine outputs (if a is set),
writing to the start-stop register NICLKSS, SMOFFON, SMON, SMOFF and the cases
enabled by bits t and o\\
S & state - read only, 1 - on, 0 - off\\
}

\register{NICLKSS}{0x0A29}{Switch the clock of NI}
{Command register to switch the clock of NI on and off}
{---- ---- ---- ---- ---- ---- ---- ---c}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & turn the NI clock on/off when 1/0 (write only). The mm field in NICLK must be "11".\\
}

\register{FILCLK}{0x0A2A}{Configuration of the Filter clock}
{Register to configure how to switch the clock of the Filter on and off}
{---- ---- ---- ---- ---- ---- --St oamm}
{---- ---- ---- ---- ---- ---- --00 0111}
{t & not used\\
o & not used\\
a & enable that the global state machine turns Filter clock on/off when its own
control output for Filter clock makes a transition\\
m & "00" - permanently off (a is ignored), "01" - permanently on (a is ignored), 
"10" - controlled by the global state machine directly (a is ignored),
"11" - controlled by transitions in global state machine outputs (if a is set),
writing to the start-stop register FILCLKSS, SMONOFF, SMON, SMOFF\\
S & state - read only, 1 - on, 0 - off\\
}

\register{FILCLKSS}{0x0A2B}{Switch the clock of Filter}
{Command register to switch the clock of Filter on and off}
{---- ---- ---- ---- ---- ---- ---- ---c}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & turn the Filter clock on/off when 1/0 (write only). The mm field in FILCLK must be "11".\\
}

\register{PRECLK}{0x0A2C}{Configuration of the Preprocessor clock}
{Register to configure how to switch the clock of the Preprocessor on and off}
{---- ---- ---- ---- ---- ---- --St oamm}
{---- ---- ---- ---- ---- ---- --00 0111}
{t & not used\\
o & not used\\
a & enable that the global state machine turns Preprocessor clock on/off when its own
control output for Preprocessor clock makes a transition\\
m & "00" - permanently off (a is ignored), "01" - permanently on (a is ignored), 
"10" - controlled by the global state machine directly (a is ignored),
"11" - controlled by transitions in global state machine outputs (if a is set),
writing to the start-stop register PRECLKSS, SMONOFF, SMON, SMOFF\\
S & state - read only, 1 - on, 0 - off\\
}

\register{PRECLKSS}{0x0A2D}{Switch the clock of Preprocessor}
{Command register to switch the clock of Preprocessor on and off}
{---- ---- ---- ---- ---- ---- ---- ---c}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & turn the Preprocessor clock on/off when 1/0 (write only). The mm field in
PRECLK must be "11".\\
}

\register{ADCEN}{0x0A2E}{Configuration of the ADC Enable}
{Register to configure how to switch the enable to the ADCs}
{---- ---- ---- ---- ---- ---- --St oamm}
{---- ---- ---- ---- ---- ---- --00 0111}
{t & not used\\
o & not used\\
a & enable that the global state machine turns ADC Enable on/off when its own
control output for ADC Enable makes a transition\\
m & "00" - permanently off (a is ignored), "01" - permanently on (a is ignored), 
"10" - controlled by the global state machine directly (a is ignored),
"11" - controlled by transitions in global state machine outputs (if a is set),
writing to the start-stop register ADCENSS, SMONOFF, SMON, SMOFF\\
S & state - read only, 1 - on, 0 - off\\
}

\register{ADCENSS}{0x0A2F}{Switch the enable of the ADCs}
{Command register to switch the enable of the ADCs on and off}
{---- ---- ---- ---- ---- ---- ---- ---c}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & turn the ADC Enable on/off when 1/0 (write only). The mm field in
ADCEN must be "11".\\
}

\register{NIODE}{0x0A30}{Configuration of the NI output data port}
{Register to configure how to switch the enable of NI output data port}
{---- ---- ---- ---- ---- ---- --St oamm}
{---- ---- ---- ---- ---- ---- --00 0111}
{t & enables swithing on by the NITM0 or NIP4D\\
o & enable switching off by the NI state machine and by the NIP4D\\
a & enable that the global state machine turns NI output data port enable 
on/off when its own control output for this signal has a transition\\
m & "00" - permanently off (t, o and a are ignored), "01" - permanently on (t, o and a are ignored), 
"10" - controlled by the global state machine directly (t, o and a are ignored),
"11" - controlled by transitions in global state
machine outputs (if a is set),
writing to the start-stop register NIODESS, NI state machine (if o set)\\
S & state - read only, 1 - on, 0 - off\\
}

\register{NIODESS}{0x0A31}{Switch the NI output data port enable}
{Command register to switch the NI output data port enable}
{---- ---- ---- ---- ---- ---- ---- ---c}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & turn the NI output data port enable on/off when 1/0 (write only). The mm
field in NIODE must be "11".\\
}

\register{NIOCE}{0x0A32}{Configuration of the NI output control port}
{Register to configure how to switch the enable of NI output control port}
{---- ---- ---- ---- ---- ---- --St oamm}
{---- ---- ---- ---- ---- ---- --00 0001}
{t & enables switching on by the NI timer 0 or 2\\
o & enable switching off when NI state machine sends done to the global state
machine\\
a & enable that the global state machine turns NI output control port enable 
on/off when its own control output for this signal has a transition\\
m & "00" - permanently off (o and a are ignored), "01" - permanently on (o and a are ignored), 
"10" - controlled by the global state machine directly (o and a are ignored),
"11" - controlled by transitions in global state
machine outputs (if a is set),
writing to the start-stop register NIOCESS, SMOFFON, SMON, SMOFF and the cases
enabled by bits t and o\\
S & state - read only, 1 - on, 0 - off\\
}

Note: For OASE mode should be used the reset value in order to have clock at the strobe output 
after power up. For all other chips 0x7 (board merger) or 0x1F is recommended.

\register{NIOCESS}{0x0A33}{Switch the NI output control port enable}
{Command register to switch the NI output control port enable}
{---- ---- ---- ---- ---- ---- ---- ---c}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & turn the NI output control port enable on/off when 1/0 (write only). The mm
field in NIOCE must be "11".\\
}

\register{NIIDE}{0x0A34}{Configuration of the NI input data ports}
{Register to configure how to switch the enable of NI input data ports}
{---- ---- ---- ---- ---- ---- --St oamm}
{---- ---- ---- ---- ---- ---- --00 0111}
{t & enables switching on by the NI timer 1 or 3\\
o & enable switching off when NI state machine sends done to the global state
machine\\
a & enable that the global state machine turns NI input data ports enable
on/off when its own control output for this signal has a transition\\
m & "00" - permanently off (o and a are ignored), "01" - permanently on (o and a are ignored),
"10" - controlled by the global state machine directly (o and a are ignored),
"11" - controlled by transitions in global state
machine outputs (if a is set),
writing to the start-stop register NIIDESS, NI state machine (if o set), NI timer 1,3 (if t set)\\
S & state - read only, 1 - on, 0 - off\\
}

\register{NIIDESS}{0x0A35}{Switch the NI input data ports enable}
{Command register to switch the NI input data ports enable}
{---- ---- ---- ---- ---- ---- ---- ---c}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & turn the NI input data ports enable on/off when 1/0 (write only). The mm
field in NIIDE must be "11".\\
}

\register{NIICE}{0x0A36}{Configuration of the NI input control ports}
{Register to configure how to switch the enable of NI input control ports}
{---- ---- ---- ---- ---- ---- --St oamm}
{---- ---- ---- ---- ---- ---- --00 0111}
{t & enables switching on by the NI timer 0 or 2\\
o & enable switching off when NI state machine sends done to the global state
machine\\
a & enable that the global state machine turns NI input control ports enable
on/off when its own control output for this signal has a transition\\
m & "00" - permanently off (o and a are ignored), "01" - permanently on (o and a are ignored),
"10" - controlled by the global state machine directly (o and a are ignored),
"11" - controlled by transitions in global state
machine outputs (if a is set),
writing to the start-stop register NIICESS, NI state machine (if o set), NI timer 0 or 2\\
S & state - read only, 1 - on, 0 - off\\
}

\register{NIICESS}{0x0A37}{Switch the NI input control ports enable}
{Command register to switch the NI input control ports enable}
{---- ---- ---- ---- ---- ---- ---- ---c}
{---- ---- ---- ---- ---- ---- ---- ----}
{c & turn the NI input control ports enable on/off when 1/0 (write only). The mm
field in NIICE must be "11".\\
}

Note: reading from the odd addresses (0x0A21..0x0A37) is equivalent to reading from the
corresponding even addresses (0x0A20..0x0A36).
