\chapter{Slow Control Serial Network}
\label{scsn}


%-----------------------------------------------------------------------------
\section{Architecture}
\label{scsn:arch}

\subsection{Network structure}
\label{scsn:arch:netstr}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15cm]{chap_scsn/scsn_bridge.eps}
 \caption[SCSN architecture. Bridge operation]{SCSN architecture. Bridge operation}
 \label{fig:scsnbridge}
\end{figure}

The main structure of the slow control network emerged from the TRD 14 Technical Design Report. 
The requirements to have a redundant architecture with few wires only, and still be able
to connect 65000 clients, led to a daisy-chain like architecture (Figure \ref{fig:scsnbridge}). Up to 126 clients (called
slaves) are connected in a ring structure with exactly one controller (called master)15 . Between two
devices (master or slave) there are 2 links, one for each data flow direction, each link being single
serial signal. Current Implementations use LVDS at about 40 MHz.
To gain redundancy each of the slaves supports X-bridging (see Figure
\ref{fig:scsnbridge}, right). In "normal" (un-bridged)
mode, a slave forwards the data to the next slave (until it arrives at the master) in the same ring.
Whereas in "bridged" mode, the data is sent back on the other ring, breaking up the full duplex ring
into two half-duplex rings. Usage of this method, allows the network to operate with broken clients,
as well.


\subsection{Network protocol}
\label{scsn:arch:netpro}

First of all a two basic statements which are discussed in the following sections:

1) Data is exchanged in fixed size packets called frames. Each frame start is indicated by a
start-bit (1) and terminates after a fixed length or an receive-error.

2) Principle : One Frame In - One Frame Out! Each frame is created by the master and termi-nates
there. The slaves only forward or alter the frame.
The network interface has to take care about certain services, like (de)serialization, addressing,
processing or forwarding the data.

All the bits of the physical layer are grouped into frames which are also buffered here. Framing is
implemented via a start bit, and a bit counter, using a fixed size frame. Dealing with transmission errors, 
(re)calculating the frame CRC-sum 19 , as well as
the implementation of the network bridge is also part of the data link layer. All buffer errors (except
the CRC-Errors) are handled internally.
If a complete frame has arrived, the data link layer sends the received frame (without checksum)
up to the network layer (NWL). Checksum errors are also reported and left to be handled by the
NWL. Since it takes some time to process
the frame, frames have to be separated from each other by an interframe space. This is done by
sendtiming/outputbuffer units. After flushing the output buffer, the buffer is locked for a short time
(not ready to send). Usually the network and application layer transactions are much faster ($<$ 10
clocks) than the network speed (including interframe-space about 250 clocks).

\begin{figure}[htb]
 \centering
 \includegraphics*[width=8cm]{chap_scsn/scsn_frame.eps}
 \caption[SCSN frame structure]{SCSN frame structure}
 \label{fig:scsnframe}
\end{figure}

\subsection{Data frame definition}
\label{scsn:arch:frame}

To understand the function of the network layer, the frame and addressing mode have to be defined
first. Each Frame consists of a header (like the envelope of a letter, containing the address and
sender), and the "letter" itself, which is called the data or the payload.
The SCSN network allows only the master to "write" a letter. It is addressed to one or all slaves
in the network. The receiver opens the letter, reads and/or alters the data and sends it back to the
master. Slaves may not address frames to any other slaves. If a slave receives a frame not addressed
to itself, the frame is just forwarded to the next slave until the frame is back at the server.
Figure \ref{fig:scsnframe} shows the frame definition and the according layers.
The current payload definition
provides 16 bit address, 32 bit data and 5 bit command requests, which 
allow standard input/output to almost all known bus systems.

\begin{table}[htb]
 \centering
 \label{tab:scsnnum}
 \scriptsize
\begin{tabular}{|l|c|l|}\hline
Address&src/dst&Description\\\hline\hline
1&1&master sends to ({\em requests}) client 1\\\hline
127&1&master broadcasts\index{Broadcast} to all clients\\\hline
1&0&client 1 answers the master (replacing the master request)\\\hline
0&0&Error frame, forward to master, unknown sender (see hopcounter)\\\hline
\end{tabular}
\caption[Network Address Table examples]{Network Address Table examples. The Address and src/dst bits are part of the frame header.}
\end{table}

Each received frame can either be
\begin{itemize}
\item {\it just forwarded}. (thereby increasing the hop counter)
\item {\it processed}, but {\bf not} altered and forwarded (thereby increasing the hop counter). e.g. broadcasts.
\item {\it processed}, altered. This creating a new frame (hop counter 0 - by default this is an error-frame), addressed back to the master, that is put back on the wire, instead of the original frame. e.g. read/write commands.
\item {\it answered with error}.
\end{itemize}


%-----------------------------------------------------------------------------
\section{Interface to Global Bus}
\label{scsn:gio}

The scsn slave design in the TRAP chip has the highest priority on the global
configuration bus. When the request is to write, the scsn slave gets from the arbiter
immediately confirmation that the operation is done. When the request is for reading,
the arbiter will do this after finishing the the present global bus transaction (if
any). The confirmation to the scsn slave will be send with some delay of max 10 clocks
(depends on the selected timing model for the arbiter).

After passing through the slave the packet will be resend to the next slave/master.
In order to avoid overlapping of the packets a minimum distance of about a packet length
is strongly recommended.

%-----------------------------------------------------------------------------
\section{Software Environment}
\label{scsn:soft}

For interface between the TRAP chips and a PC, a FPGA design with a proper software is
requered. Please note, that this part is subject to freqent changes!

The present FPGA design is for the PCI ACEX Board, developed in KIP Uni-Heidelberg.
It contains a SCSN master with two rings, pretrigger sender and clock multiplexer and
divider. The clock frequency of the TRAP and SCSN master must be the same. The source of
the clock can be either the quartz oscillator on the ACEX Board or the oscillator on the
TRAP test board. In the present design this selection is done by an external input
(ADC0\_D0) on the ADC connector of the ACEX Board. When this pin is '1', the internal
clock will be used, otherwise the external clock.

\begin{figure}[htb]
 \centering
 \includegraphics*[width=7cm]{chap_scsn/lvds_acex.eps}
 \caption[Pinout of the ACEX SCSN master]{Pinout of the ACEX SCSN master}
 \label{fig:lvdsacex}
\end{figure}

Table \ref{tab:scsnpci} shows the internal registers in the PCI design.

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|c|l|c|c|p{7cm}|}\hline
Address (Offset) & Name & Width & Type & Description\\\hline\hline
0x000 & r0\_DataL & 16 & r/w & Bits 15.. 0 of send/receive data\\\hline
0x001 & r0\_DataH & 16 & r/w &  Bits 31..16 of send/receive data\\\hline
0x002 & r0\_Address & 16 & r/w & The internal address in TRAP\\\hline
0x003 & r0\_Command & 4 & r/w &  Command, see Table \ref{tab:scsncmd}\\\hline
0x004 & r0\_MCM\_addr & 8 & r/w &  The address of the slave, writing here starts sending\\\hline
0x007 & r0\_status & 16 & r &  The status of the master, bits 7..0 are equal for both rings
(Table \ref{tab:scsnpcistat})\\\hline
0x008 & r1\_DataL & 16 & r/w & Bits 15.. 0 of send/receive data\\\hline
0x009 & r1\_DataH & 16 & r/w &  Bits 31..16 of send/receive data\\\hline
0x00A & r1\_Address & 16 & r/w & The internal address in TRAP\\\hline
0x00B & r1\_Command & 4 & r/w &  Command, see Table \ref{tab:scsncmd}\\\hline
0x00C & r1\_MCM\_addr & 8 & r/w &  The address of the slave, writing here starts sending\\\hline
0x00F & r1\_status & 16 & r &  The status of the master, bits 7..0 are equal for both rings (Table \ref{tab:scsnpcistat})\\\hline
0x040 & Pretrigg & 3 & r/w & Send pretrigger command, see Table \ref{tab:pretrpci} \\\hline
0x080 & ConfReg & 16 & r/w & Control the voltage regulators, clock speed...\\\hline
0x100 & Reset & - & w & Reset the scsn design in FPGA Board\\\hline
\end{tabular}
\caption[PCI FPGA design address space]{PCI FPGA design address
space for rings 0/1, pretrigger, configuration and reset.}
 \label{tab:scsnpci}
\end{table}

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|c|l|l|}\hline
Bits & Name & Description\\\hline\hline
0 & d0\_received & Ring 0 has received a packet\\\hline
1 & d0\_receive\_error & Error receiving the packet in ring 0\\\hline
2 & d0\_answer & Received frame is an answer frame\\\hline
3 & d0\_sendb & Currently sending data out on ring 0\\\hline
4 & d1\_received & Ring 1 has received a packet\\\hline
5 & d1\_receive\_error & Error receiving the packet in ring 1\\\hline
6 & d1\_answer & Received frame is an answer frame\\\hline
7 & d1\_sendb & Currently sending data out on ring 1\\\hline
15..8 & hop\_cnt & Hop counter of received frame\\\hline
\end{tabular}
\caption[SCSN master status register]{SCSN master status register.}
 \label{tab:scsnpcistat}
\end{table}


\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|r|l|l|}\hline
Code & Name & Description\\\hline\hline
0 & neterr & Network error reply (invalid checksum, bitstuff error, timeout)\\\hline
1 & readnrq & Read without request, trap1 only\\\hline
2 & writenrq & Write without request, trap1 only\\\hline
3 & readbnrq & Read broadcast without request, trap1 only\\\hline
4 & bridge & Bridge set when data(0)='1' and reset to non-bridged state (serial) when
data(0)='0'\\\hline
5 & cycle & Bus timing set to fast when data(31)='0' and set to slow when data(31)='1'\\\hline
6 & reset & Reset the TRAP chip\\\hline
7 & NOP & No operation, used for ping\\\hline
9 & read & Read with request, for TRAP the only correct read mode\\\hline
10 & write & Write with request, for TRAP the only correct read mode\\\hline
14 & ereply & unknown command error reply\\\hline
\end{tabular}
\caption[SCSN commands]{SCSN commands.}
 \label{tab:scsncmd}
\end{table}

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|r|l|p{11cm}|}\hline
Code & Name & Description\\\hline\hline
8 & pause & Pause, used in the PCI program to make a pause. If data=0 the program will
wait for a key to be pressed, data$>$0 means delay proportional to data, data$<$0 means check
max abs(data) if the chip is in low power state and continue\\\hline
12 & pretrigger & Pretrigger command, used in the PCI program to send a pretrigger
command=data(2:0)\\\hline
13 & power & Power on/off when data=1/0\\\hline
15 & slowclk & Slow clock enable/disable when data=1/0. Only if the TRAP clock comes
from the PCI Board. Fast/Slow clock is the ACEX Board quartz oscillator direct or /2\\\hline
\end{tabular}
\caption[SCSN pseudo commands]{SCSN pseudo commands, used in the current PCI software
only. They will be not send physically to the slaves.}
 \label{tab:scsncmdpci}
\end{table}

%-----------------------------------------------------------------------------
\subsection{Installation and First Usage}

The ACEX PCI Board needs 3.3V PCI slot.

The pci2trap program is running under linux with the PSI driver installed.

When started without parameters the program will print short help and will detect the
number of SCSN slaves.

More information now is very preliminary, as the program was used with trap1 only and
will be modified for sure in the next weeks.

\label{scsn:soft:inst}
