\chapter{Instruction Set Overview}
\label{app:instr}

\tableofinstructions

%-----------------------------------------------------------------------------
\chapter{Local and Global I/O Memory Mapping}
\label{app:lgio}

\tableofregisters

%-----------------------------------------------------------------------------
\chapter{TRAP Pad Geometry}
\label{app:pads}

\begin{figure}[htb]
 \centering
 \includegraphics*[width=15.5cm]{chap_appendix/eps/trap2_pads.eps}
 \caption[Pad geometry of TRAP]{Pad geometry of TRAP.}
 \label{fig:pads}
\end{figure}

\begin{longtable}{|l|l|p{7cm}|}
\caption{List of PADS of the TRAP} \vspace{2ex} \label{app:pads:padliste}\\
\hline
Pad & Type & Description \\
\hline \hline
VDDAi & power & +1.8V analog supply for ADCi\\
\hline
VSSAi & power & ground of 1.8V analog for ADCi\\
\hline
VDDA\_REF & power &  +1.8V analog supply for the differential reference voltage generation, Bandgap and
Temperature-sensor\\
\hline
VSSA\_REF & power &  ground for VDDA\_REF \\
\hline
IN+i & analog in &  IN+ of ADCi\\
\hline
IN--i & analog in & IN-- of ADCi\\
\hline
PA\_SCLK & LVCMOS out & CLOCK-signal of the PASA's slow control interface\\
\hline
PA\_SDAT & LVCMOS out & DATA-signal of the PASA's slow control interface, 3.3V-level\\
\hline
PA\_SSTR & LVCMOS out & STROBE-signal of the PASA's slow control interface, 3.3V-level\\
\hline
VDDD & power & +1.8V digital supply\\
\hline
VSSD & power & ground of 1.8V digital\\
\hline
VDD33 & power & +3.3V supply\\
\hline
VSS33 & power & ground of 3.3V\\
\hline
VDDPLL & power & +1.8V digital (used for the PLL)\\
\hline
VSSPLL & power & ground of 1.8V digital (used for the PLL)\\
\hline
EXTREF & analog in/out & Output of the 1.26V bandgap voltage. R$_{out}$=100k$\Omega$. The input of the differential
reference voltage generator is connected here, too.\\
\hline
EXTREF\_GND & analog in/out & ground pad of EXTREF\\
\hline
AUX+ & analog in & IN+ of the auxiliary channel for ADC22\\
\hline
AUX-- & analog in & IN-- of the auxiliary channel for ADC22\\
\hline
GNDW0..8 & power & Digital core ground\\
\hline
GNDS0..5 & power & Digital core ground\\
\hline
GNDE0..9 & power & Digital core ground\\
\hline
GND\_IOW0..5 & power & Digital I/O ground\\
\hline
GND\_IOS0..5 & power & Digital I/O ground\\
\hline
GND\_IOE0..7 & power & Digital I/O ground\\
\hline
PWRW0..8 & power & Digital core +1.8V\\
\hline
PWR0..5 & power & Digital core +1.8V\\
\hline
PWR0..9 & power & Digital core +1.8V\\
\hline
PWR\_IOW0..5 & power & Digital I/O +3.3V\\
\hline
PWR\_IOS0..5 & power & Digital I/O +3.3V\\
\hline
PWR\_IOE0..7 & power & Digital I/O +3.3V\\
\hline
GND\_DMW0..1 & power & Data memory block ground, internally connected to digital ground\\
\hline
PWR\_DMW0..1 & power & Data memory block +1.8V, internally isolated from core +1.8V\\

\hline
CLK\_ADC\_IN+/- & LVDS in & clock for the ADC and by default for the digital core, 120 MHz\\
\hline
PTRG\_IN+/- & LVDS in & pretrigger, starts the measurement, see Fig. \ref{fig:pretrcmd}\\

\hline
NIP0..3\_D0..9+/- & LVDS in & network interface input ports, data inputs\\
\hline
NIP0..3\_STB+/- & LVDS in & network interface input ports, strobe inputs\\
\hline
NIP0..3\_CTL+/- & LVDS out & network interface input ports, control outputs\\
\hline
NIP0..3\_CLKO+/- & LVDS out & clock fanout outputs\\
\hline
NIP0..3\_PTRGO+/- & LVDS out & pretrigger fanout outputs\\

\hline
NIP4\_D0..9+/- & LVDS out & network interface output port, data outputs\\
\hline
NIP4\_STB+/- & LVDS out & network interface output port, strobe output\\
\hline
NIP4\_CTL+/- & LVDS in & network interface output port, control input\\
\hline
NIP\_CTL+/- & LVDS out & network interface output port, control output\\

\hline
CLK\_DIG\_IN+/- & LVDS in & clock for the digital core, see Chapter \ref{intro:arch:clock}\\

\hline
PSEL\_CLK0..3 & LVCMOS in pull-up & configuration of the digital core clock, see Chapter \ref{intro:arch:clock}\\

\hline
VDD\_PLL & power & Power of the PLL for the CLK\_DIG\_IN +1.8V\\

\hline
PRESETN & LVCMOS in pull-up & reset of the digital core, active low (edge sensitive), internally digitally filtered,
min width 1us\\

\hline
POUT\_RNG & LVCMOS in pull-up & enable the JTAG interface, active high\\

\hline
PIRQEXT & LVCMOS in pull-up & interrupt, active low (edge sensitive), min width 25 ns\\

\hline
PTCK & LVCMOS in pull-down & JTAG TCK\\

\hline
PTDI & LVCMOS in pull-up & JTAG TDI\\

\hline
PTMS & LVCMOS in pull-up & JTAG TMS\\

\hline
PTDO & LVCMOS out & JTAG TDO\\

\hline
SEBDIR0..2 & LVCMOS bidir pull-up & 3 in/out pins with individually programmable direction and
output enable, after reset produce short negative pulse and used as reset fanout\\

\hline
SCSN0..1\_DI+/- & LVDS in & slow control serial network inputs of ports 0 and 1\\

\hline
SCSN0..1\_DO+/- & LVDS out & slow control serial network outputs of ports 0 and 1\\

\hline
NC & - & not connected internally\\

\hline
\end{longtable}

Note: 

1) CLK\_DIG\_IN, PSEL\_CLK0..3 and VDD\_PLL are for test purposes only and should remain
unconnected.

2) All internal pull-up and pull-down resistors are about 33k.

3) All LVDS inputs are internally terminated with 105 +/- 5 $\Omega$.

%4) The marked pads in Fig. \ref{fig:pads} are not necessary for MCMs which don't use the NIP0..3
%ports and clock and pretrigger fanout outp[uts. As these MCMs are 12/17 (about 70\%) of all, depending on the
%bonding yield, if enough merger MCMs are produced, the rest can be bonded without these pads to
%reduce the time and cost.
4) All LVDS output cells are powered by +1.8V digital core voltage and when enabled and terminated
consume about 4 mA. Permanently enabled are SCSN0..1\_DO and only the necessary clock and pretrigger
fanouts and NIP4\_STB (individually programmable).
