\chapter{Analog to Digital Converter}
\label{adc}




The TRAPADC consists of 21 10bit 10MS/s ADCs with differential inputs. Furthermore, a 22. 10bit 80KS/s
ADC, an analog MUX, a Temperature-sensor, a Bandgap circuit and a PLL.

\section{Connections}
\label{adc:conn}


Fig.\ref{adc:conn:pads} shows the position and names of all pads.\\
Table \ref{adc:conn:padliste} lists all pads, while table \ref{adc:conn:pinliste} lists all pins connected to the TRAP
on-chip.

\begin{figure}[h]
\begin{center}
\includegraphics[width=15cm]{chap_adc/pads.eps}
\end{center}
\caption{Position of pads of the TRAP-ADCs}
\label{adc:conn:pads}
\end{figure}

\begin{longtable}{|l|p{12cm}|}
\caption{List of PADS of the TRAP-ADCs} \vspace{2ex} \label{adc:conn:padliste}\\
\hline
Pad & Description \\
\hline \hline
VDDAi & +1.8V analog supply for ADCi\\
\hline
VSSAi & ground of 1.8V analog for ADCi\\
\hline
VDDA\_REF & +1.8V analog supply for the differential reference voltage generation, Bandgap and
Temperature-sensor\\
\hline
VSSA\_REF & ground for VDDA\_REF \\
\hline
IN+i & IN+ of ADCi\\
\hline
IN--i & IN-- of ADCi\\
\hline
PA\_SCLK & CLOCK-signal of the PASA's slow control interface, 3.3V-level\\
\hline
PA\_SDAT & DATA-signal of the PASA's slow control interface, 3.3V-level\\
\hline
PA\_SSTR & STROBE-signal of the PASA's slow control interface, 3.3V-level\\
\hline
VDDD & +1.8V digital supply\\
\hline
VSSD & ground of 1.8V digital\\
\hline
VDD33 & +3.3V supply\\
\hline
VSS33 & ground of 3.3V\\
\hline
VDDPLL & +1.8V digital (used for the PLL)\\
\hline
VSSPLL & ground of 1.8V digital (used for the PLL)\\
\hline
EXTREF & Output of the 1.26V bandgap voltage. R$_{out}$=100k$\Omega$. The input of the differential
reference voltage generator is connected here, too.\\
\hline
EXTREF\_GND & ground pad of EXTREF\\
\hline
AUX+ & IN+ of the auxiliary channel for ADC22\\
\hline
AUX-- & IN-- of the auxiliary channel for ADC22\\
\hline
\end{longtable}


\begin{longtable}{|l|p{9cm}|}

\caption{List of PINS of the TRAP-ADCs} \label{adc:conn:pinliste}\\

\hline
Pin & Description \\
\hline \hline
B9i ... B0i & 10 digital outputs of ADCi. Data format is two's complement.\\
 \hline
PA\_SDAT & DATA-signal of the PASA's slow control interface, 1.8V-level\\
 \hline
PA\_SCLK & CLOCK-signal of the PASA's slow control interface, 1.8V-level\\
 \hline
PA\_SSTR & STROBE-signal of the PASA's slow control interface, 1.8V-level\\
 \hline
TEST1 & first bit for controlling the self-test-mode of the 21 ADCs. See sec.\ref{adc:oper:selftest} for details\\
 \hline
TEST2 & second bit for controlling the self-test-mode of the 21 ADCs. See sec.\ref{adc:oper:selftest} for details\\
 \hline
EN\_INPUTBUFFER & enables the inputbuffers of the 21 ADCs. See sec.\ref{adc:oper:inputbuffer} for details\\
 \hline
AZ\_AUTO & enables the continous Autozero of the 21 ADCs. See sec.\ref{adc:oper:AZ} for details\\
 \hline
 PW2, PW1, PW0 & three power control bits for the 21 ADCs. See sec.\ref{adc:oper:power} for details\\
\hline
DA4\_ADC .. DA0\_ADC & five bits to adjust the differential reference voltage of ALL ADCs and thus the input
range. See sec.\ref{adc:oper:reference} for details\\
\hline
DR & data ready output of the 21 ADCs. High state signalizes valid data at each of the 21 B9i...B0i
outputs. The timing of DR is described in sec.\ref{adc:oper}\\
\hline
SAMPLE & input to make the 21 ADCs sample at a specific point in time. Constant high level at SAMPLE makes
the 21 ADCs run continously. Sec.\ref{adc:oper} explains the timing\\
\hline
EN & Enable input for the 21 ADCs. High level turns on all bias currents of the 21 ADCs. Low level shuts
down all bias currents and resets the controller of the 21 ADCs.\\
\hline
CLK\_IN & 120MHz clock input for the PLL of the 21 ADCs. See sec.\ref{adc:22:pll} for details\\
\hline
CLK\_OUT & 240MHz clock output of the PLL of the 21 ADCs. See sec.\ref{adc:22:pll} for details\\
\hline
ASEL2, ASEL1, ASEL0 & Select inputs of the analog MUX. See sec.\ref{adc:22} for allocation of the channels\\
\hline
PW2\_22, PW1\_22, PW0\_22 & three power control bits for the 22. ADC. See sec.\ref{adc:oper:power} for details\\
\hline
AZ\_AUTO\_22 & enables the continous Autozero of the 22. ADC. See sec.\ref{adc:oper:AZ} for details\\
\hline
MC\_TEMPS\_7 ... MC\_TEMPS\_0 & eight input bits to configure the gain of the Temperature-sensor. See
sec.\ref{adc:22:tempsensor} for details\\
\hline
OC\_TEMPS\_7 ... OC\_TEMPS\_0 & eight input bits to configure the offset of the temperature sensor.
OC\_TEMPS\_7 is the sign bit. See sec.\ref{adc:22:tempsensor} for details\\
\hline
START\_MUX & input to start the analog MUX's operation and thus the sampling of ADC22. See sec.\ref{adc:22} for
details\\
\hline
CLK\_MUX & clock input for analog MUX, ADC22 and Temperature-sensor. Clock frequency around 4MHz. 
See sec.\ref{adc:22} for details\\
\hline
BYPASS\_MUX & input to set the gain of the analog MUX to exactly 1 by bypassing the attenuation unit.\\
\hline
ATT2\_MUX ... ATT0\_MUX & three input bits to control the gain of the analog MUX. The gain factors
are listed in sec.\ref{adc:22}\\
\hline
B9\_22 ... B0\_22 & 10 digital outputs of ADC22. Data format is two's complement.\\
\hline
DR\_22 & data ready output of the 22. ADC. High state signalizes valid data at the B9\_22...B0\_22
outputs. The timing of DR\_22 is described in sec.\ref{adc:22}\\
\hline
EN\_22 & Enable input for the 22. ADC. High level turns on all bias currents of the 22. ADC. Low level shuts
down all bias currents and resets the controller of the 22. ADC.\\
\hline
READY\_TEMPS & output of the Temperature-sensor signalizing a valid output voltage. The analog MUX has to be
triggered with START\_MUX immediately. See sec.\ref{adc:22:tempsensor} for details\\
\hline
EN\_TEMPS & Enable input of the Temperature-sensor. High level starts the operation of the
Temperature-sensor. Low level sets it into power-down mode\\
\hline
\end{longtable}

\section{Operation} \label{adc:oper}
The 10bit 10MS/s ADCs are designed to quantize the output voltages  of the charge-sensitive
Preamplifier-and-Shaper (PASA), that is connected via chip-to-chip-bonding at the input-side of the ADCs.
The differential input pads of the ADCs have the same pitch of 100$\mu$m like the differential outputs of
the PASA.\\
The ADCs work with a cyclic principle of operation in switched-capacitor-technique, resulting in extremely
low power and area requirements. The differential input range is programmable (see \ref{adc:oper:reference})
with a nominal common-mode voltage of 0.9V. For further input specifications see
sec.\ref{adc:oper:inputbuffer}.\\ 
All 21 ADCs run synchronously.
The normal operation of the ADCs is controlled with the EN-and SAMPLE-pins by the TRAP. EN=1 enables the
ADCs, while EN=0 sets them in power-down-mode.\\
The SAMPLE-pin controls the sampling operation. SAMPLE=1 is recognized by the ADCs with the next rising edge
of the 240MHz clock, this may be a rising or falling edge of the 120MHz clock. Three clock cycles later the 
input switches of the ADCs are closed; this is the actual
sampling. After SAMPLE=1 has been recognized, the sampling and cyclic conversion is performed regardless of
the state of SAMPLE. If SAMPLE is constantly 1, the ADCs sample continously after each 24 clock cycles.\\
The DR-pin signalizes valid data at the 10 digital outputs B9..B0 of each ADC with DR=1. DR becomes high 12
clock cycles after the ADCs have sampled. The data belong to the sample before the last one, so the latency
is 36 clock cycles (for continous operation). DR stays 1 for 20 clock cycles and becomes 0 for 4.\\
The data format of the digital output data is two's complement.\\
After EN has been set to 1 the first few samples ($\approx$3,) may have a
reduced accuracy.

\subsection{Adjustable reference voltage of the ADCs} \label{adc:oper:reference}

The differential architecture of the ADCs requires a differential reference voltage, which is internally
derived from the single-ended 1.2V Bandgap voltage. The differential reference has a nominal value of 1V with a
common-mode-voltage of 0.9V. The input range of the ADCs depends on the reference voltage: 

\[ V_{in} = \pm V_{ref} \]

To overcome variations of the PASA's gain, the reference voltage and thus the input range are adjustable with
the DA4\_ADC .. DA0\_ADC -pins by the TRAP. 
For V$_{Bandgap}$=1.26V the range lasts from 1.05V to 1.45V. This corresponds to $\approx$2.1mV/LSB to $\approx$2.9mV/LSB.\\
The generated differential reference is common for the 21 ADCs and the 22.ADC. The reference voltage
generator is always active and not affected by any enable-signal.

\subsection{Configurable Power consumption} \label{adc:oper:power}

The bias currents of the analog parts of the ADCs are adjustable to compensate current variations due to resistance
variations and allow an adaption of the bias currents to changes of the sample rate. Furthermore, this
allows to reduce the power consumption in idle periods without completely turning off the ADCs (EN stays
1). This allows an immediate return to normal power and full accuracy within one sample.\\
The supply currents of the different supplying voltage sources for the 21 ADCs (at 1.8V, 3.3V,
V$_{Bandgap}$=1.2V, f$_{clk}$=120MHz) are:

\begin{table}[h]
\begin{center}
\begin{tabular}{llcl}
3.3V: & I$_{33}$ &=& 15mA \\
digital 1.8V: & I$_{18d}$ &=& 4mA \\
analog 1.8V: & I$_{18a}$ &=& $26mA + 48.3mA \cdot \frac{PW_{i}}{7}$
\end{tabular}
\end{center}
\end{table}

Here PW2, PW1 and PW0 are the three pins controlled by the TRAP that adjust the currents of the 21 ADCs.
The typical setting for 10MS/s operation is 011.\\
PW2\_22, PW1\_22 and PW0\_22 control the current for the 22.ADC. As this ADC is identical like the 21 ADCs,
due to its lower operating frequency it can work with lower power consumption, so setting PWx\_22 to 0 will
still be sufficient for this ADC.\\
Disabling the 21 ADCs reduces their current consumption to I$_{18a,dis.}$=10mA, I$_{18d,dis.}$=0mA and
I$_{33,dis.}$=0.3mA.\\
On-chip some decoupling capacitors for the supply voltages are implemented. Fig.\ref{adc:oper:caps} shows the
equivalent structure of the decoupling capacitors. 

\begin{figure}[h]
\begin{center}
\includegraphics[height=5cm]{chap_adc/caps.eps}
\end{center}
\caption{Equivalent structure of the on-chip decoupling}
\label{adc:oper:caps}
\end{figure}

Each of these equivalent RC-devices consists of a large number of unit devices in parallel.
Fig.\ref{adc:oper:capseinzeln} shows the unit devices that were used.

\begin{figure}[h]
\begin{center}
\includegraphics[height=5cm]{chap_adc/capseinzeln.eps}
\end{center}
\caption{Unit decoupling device}
\label{adc:oper:capseinzeln}
\end{figure}

The resistance acts as current limiting in case
of oxide breakdown of a single unit device, as the capacitors are MOS-devices. Furthermore, it ensures
sufficient damping of the LC circuit consisting of bondwire and decoupling capacitor.

\subsection{Configurable Autozero} \label{adc:oper:AZ}

The ADCs make use of an Autozero-technique to cancel their own offset and reduce own $\frac{1}{f}$-noise.
The Autozero-operation is either performed regularly with each new sample or not at all.\\
Disabling the Autozero (AZ) can lower the overall noise of the ADCs in short measuring periods, where
$\frac{1}{f}$-noise is negligible, because the AZ itself is one source of $\frac{kT}{C}$-noise in the ADC.\\
The pins AZ\_AUTO and AZ\_AUTO\_22 control the AZ for the 21 ADCs and the 22., resp.. AZ\_AUTO =1 makes the
ADCs perform the AZ while AZ\_AUTO =0 inhibits it. The state of the AZ\_AUTO is checked by the ADCs with the
rising clock edge two cycles before the sampling happens.\\
If no AZ is performed over longer periods, each ADC's offset will slowly drift from 0V to its actual value.

\subsection{Configurable input circuit of the 21 ADCs} \label{adc:oper:inputbuffer}

The ADCs offer two different configurations for their input circuit:
\begin{enumerate}
\item
a continous-time working buffer with high impedance input that minimizes the impact of the switched
capacitors inside the ADC on the driving signal source. It is supplied with 3.3V.

\begin{table}[h]
\begin{center}

\begin{tabular}{l|l}
cut-off-frequency f$_{g}$ & 65MHz (for R$_{source}$=50$\Omega$) \\
power consumption per channel & 0.8mW \\
input capacitance per input pad C$_{in}$ & 1pF \\

\end{tabular}
\caption{Data of the input buffer}
\end{center}
\end{table}


\item
a direct connection to the signal capacitors of the ADC, that are charged during sampling by the driving
signal source. This requires a lower driving impedance than with the input buffer. The equivalent input
circuit for the direct input of the ADC during sampling is shown in Fig.\ref{adc:oper:input}. At the sampling point
some MOS-switches inject charge to the driving signal source. The effect of this charge injection must be over
before the next sampling happens.

\begin{figure}[h]
\begin{center}
\includegraphics[height=5cm]{chap_adc/eingang.eps}
\end{center}
\caption{Equivalent input circuit of the ADCs for direct input connection}
\label{adc:oper:input}
\end{figure}

\begin{table}[h]
\begin{center}

\begin{tabular}{l|l}
cut-off-frequency f$_{g}$ & 300MHz (for R$_{source}$=50$\Omega$)\\
input capacitance per input pad C$_{in}$ & 1.4pF - 2.8pF (depends on sampling capacitor)\\
injected charge at sampling & 80fC - 150fC \\
\end{tabular}
\caption{Data of the direct input}
\end{center}
\end{table}



\end{enumerate}

The sampling intervall t$_{Sample}$ is 24 clock cycles long (100ns at 240MHz), the same time as the
quantization of the previously taken sample lasts. At the beginning of the sample
intervall the discharged C$_{sample}$ is connected to the inputs according to Fig.\ref{adc:oper:input} via
R$_{sample}$. At the end of the sample intervall C$_{sample}$ is disconnected from the inputs, storing the
instantaneous signal value which is quantized afterwards.\\
Immediately after the sampling the next sample intervall starts (with a different device C$_{sample}$) and
lasts again 24 clock cycles.\\
The pin EN\_INPUTBUFFER controls the input configuration of the 21 ADCs.\\
 \mbox{EN\_INPUTBUFFER=1} leads to usage
of the inputbuffers, while \mbox{EN\_INPUTBUFFER=0} leads to the direct sampling input and power-down of the
inputbuffer.\\
If the output impedance of the PASA allows the use of the direct sampling input, this option should be preferred
not only for its lower power consumption, but it offers lower noise and distortion, no offset and higher
cut-off-frequency.\\
The common-mode-voltage should for both input configurations lie at 0.9V. None of the two input lines may 
exceed the range between gnd
and 1.8V.\\
 The direct input will always exhibit a better CMRR, because it avoids the common-mode influence of the
 inputbuffer.\\

\subsection{Self-test mode of the 21 ADCs}  \label{adc:oper:selftest}

In order to detect defective ADC-channels without connecting an input signal, the differential inputs can be
internally connected to the differential reference voltage or shorted. This leads to three different
testsignals: +V$_{ref}$, --V$_{ref}$ and 0V. The corresponding digital output codes should be +511, --511 and
0.\\
To control this self-test mode the 21 ADCs have the pins TEST1 and TEST2. Table \ref{adc:oper:testmode} lists the
four possible settings.

\begin{table}[h]
\begin{center}
\begin{tabular}{cc|l}
TEST1 & TEST2 & mode\\
\hline
0 & 0 & normal measurements\\
0 & 1 & +V$_{ref}$\\
1 & 0 & --V$_{ref}$\\
1 & 1 & 0V\\
\end{tabular}
\caption{Settings of TEST1 and TEST2}
\label{adc:oper:testmode}
\end{center}
\end{table}

The self-test mode should only be used with enabled inputbuffer because the internal reference is not designed to
be loaded by the direct input of the ADC.

\section{22. ADC with analog MUX} \label{adc:22}

Beside the 21 ADCs converting the PASA-signals the design features a 22.ADC with 10bit, 80kS/s for measuring some additional
signals. This ADC is in general identical to the 21: It uses the same reference voltages, has configurable
power and Autozero, but no inputbuffer and no testmode.\\ Pins of the 22.ADC are EN\_22, DR\_22,
AZ\_AUTO\_22, PW\_22\_3, PW\_22\_2, PW\_22\_0 and B9\_22 ... B0\_22.\\
SAMPLE-signal and CLK are supplied by the analog MUX.\\
The analog input signals for the 22. ADC are supplied via the analog MUX which allows to select one of eight inputs
 (six are used). The connections of the MUX are listed in table \ref{adc:22:mux}:
 
 \begin{table}[h]
\begin{center}
 \begin{tabular}{ccc|l}
 ASEL2 & ASEL1 & ASEL0 & channel \\
 \hline
 0 & 0 & 0 & 1.8V digital\\
 0 & 0 & 1 & 1.8V analog \\
 0 & 1 & 0 & 3.3V\\
 0 & 1 & 1 & AUX-pads \\
 1 & 0 & 0 & V$_{temp}$ of Bandgap\\
 1 & 0 & 1 & not used \\
 1 & 1 & 0 & not used \\
 1 & 1 & 1 & Temperature-sensor\\
 \end{tabular}
\end{center}
 \caption{Allocation of the channels of the analog MUX}
 \label{adc:22:mux}
 \end{table}
 
ASEL2, ASEL1 and ASEL0 are three pins controlled by the TRAP. The MUX works with signal charges: by charge
sharing with the capacitors of the 22.ADC it offers several attenuation factors that can be selected with
the \mbox{ATT2\_MUX}, \mbox{ATT1\_MUX} and \mbox{ATT0\_MUX-pins}. Table \ref{adc:22:muxsettings} lists the various factors.

 \begin{table}[h]
\begin{center}
 \begin{tabular}{ccc|l|l}
 ATT\_MUX2 & ATT\_MUX1 & ATT\_MUX0 & gain & measured\\
 \hline
 0 & 0 & 0 & 0.5 & 0.42 \\
 0 & 0 & 1 & 0.5 & 0.42 \\
 0 & 1 & 0 & 0.66 & 0.59 \\
 0 & 1 & 1 & 0.33 & 0.29 \\
 1 & 0 & 0 & 0.66 & 0.59 \\
 1 & 0 & 1 & 0.33 & 0.29 \\
 1 & 1 & 0 & 0.75 & 0.68 \\
 1 & 1 & 1 & 0.25 & 0.23 \\
 \end{tabular}
\end{center}
 \caption{Allocation of the attenuation factors of the analog MUX}
 \label{adc:22:muxsettings}
 \end{table}

 An additional pin BYPASS\_MUX sets the gain precisely to -1 by directly connecting ADC-input and selected
 source.\\
 By using the attenuation factors it is possible to measure signals larger than the $\pm$1V input signal
 range of the ADC.\\
 \indent A clock signal for analog MUX, ADC22 and Temperature-sensor must be supplied to the pin CLK\_MUX.
 The frequency should be around 4MHz. The MUX supplies the Temperature-sensor with this clock divided
 by four and ADC22 with it divided by two, resulting in $\approx$80KS/s.\\
 Via the START\_MUX-pin measurements are started. START\_MUX=1 must be applied at least for one clock cycle
 length of the 1MHz clock but not longer than two cycles. During START\_MUX=1 the ASELx and
 ATTx\_MUX-states must not change.\\
 The latency from sampling to data out is similar to that of the 21 ADCs: After START\_MUX=1 it takes the
 time until the next START\_MUX=1 plus 40 of the
 4MHz-clock cycles until DR\_22 signalizes valid data at B9\_22 ... B0\_22, corresponding to the input
 signal of the MUX when START\_MUX was set to 1.\\
Due to the ``pipeline''-structure of the ADC this data come out only if the next sample has already been
started (via START\_MUX).\\
After EN\_22 has been set to 1 the 22.ADC may deliver some first samples of reduced accuracy, similar to the
21 ADCs. The same may happen after longer periods without clock, even if EN\_22 remained 1.\\
 The analog
1.8V-power for the 22.ADC is connected to the analog 1.8V of ADC14.\\
The maximum possible input signals at the AUX+ and AUX-- pads are limited by the 3.3V supply and ground.\\
For each channel of the analog MUX the TRAP has settings for the corresponding gain, that are applied
simultaneously with the channel-selection-bits ASELx.

\subsection{Temperature-sensor} \label{adc:22:tempsensor}

The chip features a Temperature-sensor that generates a temperature-proportional output signal. A small
PTAT-voltage of the Bandgap-circuit is amplified in a switched capacitor circuit to achieve high precision and low
power.\\
Gain and Offset of the Temperature-sensor are controlled by the pins MC\_TEMPS\_7 ... MC\_TEMPS\_0 (gain)
and OC\_TEMPS\_7 ... OC\_TEMPS\_0 (offset) according to 

\begin{eqnarray*}
V_{out,TempSensor} & = & 29.835\frac{mV}{K} \cdot (T-50^{\circ} C) \cdot \frac{MC\_TEMPS\_i}{255} \\
& & {} + 25.4mV \cdot (-1)^{MC\_TEMPS\_7} \cdot \frac{OC\_TEMPS\_i}{127}
\end{eqnarray*}
 
The Temperature-sensor is designed to have its zero output voltage at 50$^{\circ}$C. However, due to offsets
this zero output must be adjusted by the OC\_TEMPS\_x-bits.
The adjustable gain factor allows to map a certain temperature range (symmetrical around 50$^{\circ}$C) 
to the input range of the ADC22 of
$\pm1V$/gain$_{MUX}$.\\
The operation of the Temperature-sensor is controlled by the pin EN\_TEMPS. EN\_TEMPS=1 activates
the Temperature-sensor that immediately starts its operation. EN\_TEMPS=0 sets the Temperature-sensor to
power-down-mode.\\
After the numbers of the multiplication and offset-cycles are performed (according to the settings of
MC\_TEMPS\_x and OC\_TEMPS\_x) the pin READY\_TEMPS=1 signalizes a valid temperature-signal at the outputs
of the Temperature-sensor. READY\_TEMPS stays 1 for 28 of the 4MHz clock cycles.\\
The analog MUX is not automatically triggered by READY\_TEMPS=1, but the START\_MUX-pin has to be set to 1
now by the TRAP immediately.\\
After EN\_TEMPS has been set to 1, the Temperature-sensor needs one measuring cycle until it reaches
full accuracy.\\
The settings of MC\_TEMPS\_x and OC\_TEMPS\_x must be held constant during a measurement. Changes are
allowed during EN\_TEMPS=0.

\subsection{Bandgap-circuit} \label{adc:22:bandgap}

The on-chip bandgap delivers a bandgap-voltage of 1.26V to the pad EXTREF. The bandgap-voltage is referred
to the ground-pad EXTREF\_GND.\\
The output resistance of the bandgap-voltage is 100K$\Omega$. On-chip exists a 16pF capacitor between EXTREF
and EXTREF\_GND.\\ 
The input of the differential reference generator of the ADCs, requiring constant 1.2V, is also connected to
the EXTREF-pad. If necessary, the bandgap-voltage can be externally overridden due to the 100K$\Omega$
output resistance.\\
Beside the constant 1.26V-voltage, the bandgap-circuit generates a differential 
temperatur-dependent voltage V$_{temp}$.
It is derived from a bipolar diode which is biased with constant current.\\
V$_{temp}$ is connected at port 5 of the analog MUX. At each of the two differential V$_{temp}$-lines a 5pF
capacitor is connected to EXTREF\_GND.\\

\subsection{On-chip PLL} \label{adc:22:pll}

Within the chip a VST-PLL is included to multiply the clock frequency by two and 
lower the jitter rate of the clock signal for the ADCs.\\
The 120MHz-input clock pin is CLK\_IN, the 240MHz output pin is CLK\_OUT. This output clock is used for the
ADCs, too.\\
The PLL owns four power pads VDDPLL, VDDPLL, GNDPLL, GNDPLL that have to be connected to the digital 1.8V
and ground, resp..\\
Applying no power to the PLL enables a bypass around the PLL: The pin CLK\_IN is connected to CLK\_OUT
directly then. However, this leads to a sample rate of 5MS/s only.








%-----------------------------------------------------------------------------
\section{Specification}
\label{adc:spec}


%-----------------------------------------------------------------------------
%\subsection{Analog Interface}
%\label{adc:spec:ana}


%-----------------------------------------------------------------------------
\subsection{Matching to PASA Interface}
\label{adc:spec:pasa}

\register{PASADEL}{0x3158}{PASA delay}
{PASA delay}
{---- ---- ---- ---- ---- ---- aaaa aaaa}
{---- ---- ---- ---- ---- ---- 1111 1111}
{a & delay between last bit shift out and the strobe in slow clocks (samples)\\
}

\register{PASAPHA}{0x3159}{PASA phase}
{PASA phase}
{---- ---- ---- ---- ---- ---- --aa aaaa}
{---- ---- ---- ---- ---- ---- --11 1111}
{a & additional delay between last bit shift out and the strobe in fast clocks\\
}

The actual delay between the last positive edge of the serial clock and the strobe pulse
is given by:

Delay = (PASADEL + 2) * T$_{slow}$ + (PASAPHA + 4) * T$_{fast}$,

where T$_{fast}$ is the period of the fast clock,

T$_{slow}$ is the period of the samples = 12 * T$_{fast}$ 

\register{PASAPRA}{0x315A}{Pretrigger advance}
{Pretrigger advance}
{---- ---- ---- ---- ---- ---- --aa aaaa}
{---- ---- ---- ---- ---- ---- --00 1111}
{a & advance of the pretrigger relative to the strobe pulse, recommended value\\
 & PASAPHA $>$ PASAPRA $>$ 0\\
}

\register{PASADAC}{0x315B}{PASA DAC for the amplitude of the test pulse}
{PASA DAC for the amplitude of the test pulse}
{---- ---- ---- ---- ---- ---- aaaa aaaa}
{---- ---- ---- ---- ---- ---- 1000 0000}
{a & Test pulse amplitude in PASA, 8-bit\\
}

\register{PASACHM}{0x315B}{PASA test pulse channel mask}
{PASA test pulse channel mask}
{---- ---- ---- -aaa aaaa aaaa aaaa aaab}
{---- ---- ---- -111 1111 1111 1111 1111}
{a & when the n-th bit is set, the corresponding channel will be fired by the strobe
(n=1..18)\\
 b & don't care, reserved for future changes in PASA\\
}

Note the correspondence between the PASA internal channel number $p$ and the TRAP ADC channel
number $t$ is given by:

$t = 20 - p$, for $p$ = 1..18

\register{PASASTL}{0x315D}{PASA strobe length}
{PASA strobe length}
{---- ---- ---- ---- ---- ---- aaaa aaaa}
{---- ---- ---- ---- ---- ---- 1111 1111}
{a & Strobe length in fast clocks, recommended $>$ acquisition time\\
}

\register{PASAPR1}{0x315E}{Program PASA serially and start}
{Program PASA serially and start}
{---- ---- ---- ---- ---- ---- ---- ---a}
{---- ---- ---- ---- ---- ---- ---- ---0}
{a & A low to high transition will start the serial shift out and the strobe\\
}

\register{PASAPR0}{0x315F}{Start PASA without programming serially}
{Start PASA without programming serially}
{---- ---- ---- ---- ---- ---- ---- ---a}
{---- ---- ---- ---- ---- ---- ---- ---0}
{a & A low to high transition will start the strobe without sending againg the DAC and
mask to the PASA\\
}



%-----------------------------------------------------------------------------
\subsection{Digital Interface}
\label{adc:spec:dig}

\register{ADCMSK}{0x3050}{ADC Mask}
{ADC Mask to mask the outputs of selected ADCs}
{---- ---- ---a aaaa aaaa aaaa aaaa aaaa}
{---- ---- ---1 1111 1111 1111 1111 1111}
{a & when set, the corresponding ADC channel is enabled, otherwise all bits of
the ADC channel are 0\\
}

\register{ADCINB}{0x3051}{ADC Invert Bits}
{ADC Invert Bits}
{---- ---- ---- ---- ---- ---- ---- --mo}
{---- ---- ---- ---- ---- ---- ---- --10}
{m & when set, the MSB of the ADC output will be inverted\\
 o & when set, all other bits (except for MSB) of the ADC output will be inverted\\
}

\register{ADCDAC}{0x3052}{ADC DAC}
{ADC DAC}
{---- ---- ---- ---- ---- ---- ---d dddd}
{---- ---- ---- ---- ---- ---- ---1 0000}
{d & DAC for ADC conv gain\\
}

\register{ADCPAR}{0x3053}{ADC parameters}
{ADC Parameters}
{---- ---- ---- --ii iiss ssbz hhhe appp}
{---- ---- ---- --01 1001 0101 1110 1111}
{b & enable input buffer in normal mode\\
 z & enable auto-zero in normal mode\\
 h & power in normal mode\\
 e & enable input buffer in power save mode\\
 a & enable auto-zero in power save mode\\
 p & power in power save mode\\
 s & sampling phase\\
 i & IRQ ADC phase\\
}

\register{ADCTST}{0x3054}{ADC test mode}
{ADC test mode}
{---- ---- ---- ---- ---- ---- ---- --tt}
{---- ---- ---- ---- ---- ---- ---- --00}
{t & ADC test mode, "00" normal, "01" +Vref, "10" -Vref, "11" 0.\\
}

\register{SADCAZ}{0x3055}{Slow control ADC auto zero}
{Slow control ADC auto zero}
{---- ---- ---- ---- ---- ---- ---- ---a}
{---- ---- ---- ---- ---- ---- ---- ---1}
{a & auto zero enable for slow control ADC\\
}

\register{SADCTRG}{0x3161}{Slow ADC channel trigger}
{Slow ADC channel trigger}
{---- ---- ---- ---- ---- ---- ---- ---a}
{---- ---- ---- ---- ---- ---- ---- ---0}
{a & any change here will start a complete measurement of the slow control voltages\\
}

\register{SADCRUN}{0x3162}{Slow ADC channel run}
{Slow ADC channel run}
{---- ---- ---- ---- ---- ---- ---- ---a}
{---- ---- ---- ---- ---- ---- ---- ---0}
{a & when 1, the new measurement will be started automatically, otherwise a trigger will
be necessary (SADCTRG)\\
}

\register{SADCPWR}{0x3163}{Slow ADC power}
{Slow ADC power}
{---- ---- ---- ---- ---- ---- ---- -aaa}
{---- ---- ---- ---- ---- ---- ---- -111}
{a & 000 means lowest power, 111 - highest. For TRAP the recommended value is 111\\
}

\register{SADCSTA}{0x3164}{Slow ADC channel status read only}
{Slow ADC channel status read only}
{---- ---- ---- ---- ---- ---- -ret aiii}
{---- ---- ---- ---- ---- ---- -100 0000}
{r & data ready from the ADC\\
 e & temperature sensor enable\\
 t & temperature sensor ready\\
 a & when 1, a measurement is running\\
 i & the present analog channel selected by the analog mux\\
}

\register{L0TSIM}{0x3165}{L0 time for simulation}
{L0 time for simulation}
{---- ---- ---- ---- --aa aaaa aaaa aaaa}
{---- ---- ---- ---- --00 0000 0101 0000}
{a & L0 time (in fast ADC clocks) used for the internal simulation mode\\
}

\register{SADCEC}{0x3166}{Slow ADC channel external control}
{Slow ADC channel external control}
{---- ---- ---- ---- ---- ---- -daa ates}
{---- ---- ---- ---- ---- ---- -000 0000}
{d & disable the internal state machine\\
 a & select for the analog mux, see Table \ref{tab:adcsch}\\
 t & temperature sensor enable\\
 e & enable slow ADC\\
 s & any change here starts the multiplexer and a sample\\
}

\register{SADCCn}{0x3168+n}{Slow ADC channel n, n=0..7}
{Slow ADC channel n, n=0..7}
{---- ---- ---- ---- ---- --AA AAAA AAAA}
{---- ---- ---- ---- ---- --xx xxxx xxxx}
{A & The last ADC value for channel n, where n is from 0 to 7 (read only)\\
}

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|l|l|}\hline
Binary code&Analog signal\\\hline\hline
000&1.8V digital\\\hline
001&1.8V analog\\\hline
010&3.3V\\\hline
011&AUX-pads\\\hline
100&V$_{temp}$ of bandgap\\\hline
101&not used\\\hline
110&direct the output of the slow ADC\\\hline
111&Temperature sensor\\\hline
\end{tabular}
\caption[Slow ADC analog channels]{Slow ADC analog channels}
\label{tab:adcsch}
\end{table}

\register{SADCMC}{0x3170}{Slow ADC measurement cycles}
{Slow ADC measurement cycles}
{---- ---- ---- ---- ---- ---- aaaa aaaa}
{---- ---- ---- ---- ---- ---- 1100 0000}
{a & Slow ADC measurement cycles\\
}

\register{SADCOC}{0x3171}{Slow ADC offset measurement cycles}
{Slow ADC offset measurement cycles}
{---- ---- ---- ---- ---- ---- aaaa aaaa}
{---- ---- ---- ---- ---- ---- 0001 1001}
{a & Slow ADC offset measurement cycles\\
}

\register{SADCGTB}{0x3172}{Slow ADC gain table}
{Slow ADC gain table}
{hhhh gggg ffff eeee dddd cccc bbbb aaaa}
{0011 0111 0111 0011 0111 0111 0000 0000}
{a & gain for channel 0, MSB = bypass analog mux\\
 b & gain for channel 1, MSB = bypass analog mux\\
 c & gain for channel 2, MSB = bypass analog mux\\
 d & gain for channel 3, MSB = bypass analog mux\\
 e & gain for channel 4, MSB = bypass analog mux\\
 f & gain for channel 5, MSB = bypass analog mux\\
 g & gain for channel 6, MSB = bypass analog mux\\
 h & gain for channel 7, MSB = bypass analog mux\\
}

\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|l|l|}\hline
Binary code&Attenuation\\\hline\hline
000&0.50\\\hline
001&0.66\\\hline
010&0.66\\\hline
011&0.75\\\hline
100&0.50\\\hline
101&0.33\\\hline
110&0.33\\\hline
111&0.25\\\hline
\end{tabular}
\caption[Slow ADC attenuation factors]{Slow ADC attenuation factors}
\label{tab:adcsgain}
\end{table}

The ADCs can be read directly by the CPUs using the {\bf Local IO bus}. For syncrhonization is
recommended to use the EOC (End Of Conversion) IRQ (See \ref{tp:intr} how to use
interrupts).

\register{ADCCPUn}{0x100+n}{Direct ADC to CPU interface}
{Direct ADC to CPU interface, see Table \ref{tab:adccpu} for details}
{---- ---- ---- ---- ---- -EAA AAAA AAAA}
{---- ---- ---- ---- ---- ---- ---- ----}
{A & 10 bit ADC data\\
 E & ADC data ready as it comes from the ADC block\\
}


\begin{table}[htb]
 \centering
 \scriptsize
\begin{tabular}{|c|c|c|c|c|}\hline
Local Address& ADC / CPU0 & ADC / CPU1 & ADC / CPU2 & ADC / CPU3\\\hline\hline
0x100 & 0 & 5 & 9 & 13\\\hline
0x101 & 1 & 6 & 10 & 14\\\hline
0x102 & 2 & 7 & 11 & 15\\\hline
0x103 & 3 & 8 & 12 & 16\\\hline
0x104 & 4 & 9 & 13 & 17\\\hline
0x105 & 5 & 10 & 14 & 18\\\hline
0x106 & 6 & 11 & 15 & 19\\\hline
0x107 & 7 & 12 & 16 & 20\\\hline
\end{tabular}
\caption[ADC to CPU direct interface in LIO]{ADC to CPU direct interface in LIO}
\label{tab:adccpu}
\end{table}

The 3 programmable I/O pins actually are not a part of the ADC design. Their configuration
is here only because the addresses are close to the configuration addresses of the ADCs.

\register{SEBDEN}{0x3178}{Single ended bidir output enables}
{Single ended bidir output enables}
{---- ---- ---- ---- ---- ---- ---- -eee}
{---- ---- ---- ---- ---- ---- ---- -000}
{e & output enable for I/O pins SEBD0..2\\
}

\register{SEBDOU}{0x3179}{Single ended bidir outputs}
{Single ended bidir outputs}
{---- ---- ---- ---- ---- ---- ---- -ooo}
{---- ---- ---- ---- ---- ---- ---- -000}
{e & output values for I/O pins SEBD0..2 (if the corresponding bit in SEBDEN set)\\
}

\register{SEBDIN}{0x317A}{Single ended bidir inputs (read only)}
{Single ended bidir inputs (read only)}
{---- ---- ---- ---- ---- ---- ---- -iii}
{---- ---- ---- ---- ---- ---- ---- ----}
{i & input values at I/O pins SEBD0..2\\
}
