SML0 = 0x0A00 # SSSS RRRR RR-- ---- -itt tttt tttt tttt # GSM level 0 time and ignore SML1 = 0x0A01 # SSSS RRRR RR-- ---- -itt tttt tttt tttt # GSM level 1 time and ignore SML2 = 0x0A02 # SSSS RRRR RR-- ---- -itt tttt tttt tttt # GSM level 2 time and ignore SMMODE = 0x0A03 # SSSS RRRR RR-- ---- pppp snme eeee dddd # GSM mode bits SMCMD = 0x0A04 # ---- ---- ---- ---- cccc cccc cccc cccc # GSM command register CPU0CLK = 0x0A20 # ---- ---- ---- ---- ---- ---- --St oamm # Configuration of the CPU 0 clock CPU0SS = 0x0A21 # ---- ---- ---- ---- ---- ---- ---- ---c # Switch the clock of CPU 0 CPU1CLK = 0x0A22 # ---- ---- ---- ---- ---- ---- --St oamm # Configuration of the CPU 1 clock CPU1SS = 0x0A23 # ---- ---- ---- ---- ---- ---- ---- ---c # Switch the clock of CPU 1 CPU2CLK = 0x0A24 # ---- ---- ---- ---- ---- ---- --St oamm # Configuration of the CPU 2 clock CPU2SS = 0x0A25 # ---- ---- ---- ---- ---- ---- ---- ---c # Switch the clock of CPU 2 CPU3CLK = 0x0A26 # ---- ---- ---- ---- ---- ---- --St oamm # Configuration of the CPU 3 clock CPU3SS = 0x0A27 # ---- ---- ---- ---- ---- ---- ---- ---c # Switch the clock of CPU 3 NICLK = 0x0A28 # ---- ---- ---- ---- ---- ---- --St oamm # Configuration of the NI clock NICLKSS = 0x0A29 # ---- ---- ---- ---- ---- ---- ---- ---c # Switch the clock of NI FILCLK = 0x0A2A # ---- ---- ---- ---- ---- ---- --St oamm # Configuration of the Filter clock FILCLKSS = 0x0A2B # ---- ---- ---- ---- ---- ---- ---- ---c # Switch the clock of Filter PRECLK = 0x0A2C # ---- ---- ---- ---- ---- ---- --St oamm # Configuration of the Preprocessor clock PRECLKSS = 0x0A2D # ---- ---- ---- ---- ---- ---- ---- ---c # Switch the clock of Preprocessor ADCEN = 0x0A2E # ---- ---- ---- ---- ---- ---- --St oamm # Configuration of the ADC Enable ADCENSS = 0x0A2F # ---- ---- ---- ---- ---- ---- ---- ---c # Switch the enable of the ADCs NIODE = 0x0A30 # ---- ---- ---- ---- ---- ---- --St oamm # Configuration of the NI output data port NIODESS = 0x0A31 # ---- ---- ---- ---- ---- ---- ---- ---c # Switch the NI output data port enable NIOCE = 0x0A32 # ---- ---- ---- ---- ---- ---- --St oamm # Configuration of the NI output control port NIOCESS = 0x0A33 # ---- ---- ---- ---- ---- ---- ---- ---c # Switch the NI output control port enable NIIDE = 0x0A34 # ---- ---- ---- ---- ---- ---- --St oamm # Configuration of the NI input data ports NIIDESS = 0x0A35 # ---- ---- ---- ---- ---- ---- ---- ---c # Switch the NI input data ports enable NIICE = 0x0A36 # ---- ---- ---- ---- ---- ---- --St oamm # Configuration of the NI input control ports NIICESS = 0x0A37 # ---- ---- ---- ---- ---- ---- ---- ---c # Switch the NI input control ports enable PASADEL = 0x3158 # ---- ---- ---- ---- ---- ---- aaaa aaaa # PASA delay PASAPHA = 0x3159 # ---- ---- ---- ---- ---- ---- --aa aaaa # PASA phase PASAPRA = 0x315A # ---- ---- ---- ---- ---- ---- --aa aaaa # Pretrigger advance PASADAC = 0x315B # ---- ---- ---- ---- ---- ---- aaaa aaaa # PASA DAC for the amplitude of the test pulse PASACHM = 0x315C # ---- ---- ---- -aaa aaaa aaaa aaaa aaab # PASA test pulse channel mask PASASTL = 0x315D # ---- ---- ---- ---- ---- ---- aaaa aaaa # PASA strobe length PASAPR1 = 0x315E # ---- ---- ---- ---- ---- ---- ---- ---a # Program PASA serially and start PASAPR0 = 0x315F # ---- ---- ---- ---- ---- ---- ---- ---a # Start PASA without programming serially ADCMSK = 0x3050 # ---- ---- ---a aaaa aaaa aaaa aaaa aaaa # ADC Mask ADCINB = 0x3051 # ---- ---- ---- ---- ---- ---- ---- --mo # ADC Invert Bits ADCDAC = 0x3052 # ---- ---- ---- ---- ---- ---- ---d dddd # ADC DAC ADCPAR = 0x3053 # ---- ---- ---- --ii iiss ssbz hhhe appp # ADC parameters ADCTST = 0x3054 # ---- ---- ---- ---- ---- ---- ---- --tt # ADC test mode SADCAZ = 0x3055 # ---- ---- ---- ---- ---- ---- ---- ---a # Slow control ADC auto zero SADCTRG = 0x3161 # ---- ---- ---- ---- ---- ---- ---- ---a # Slow ADC channel trigger SADCRUN = 0x3162 # ---- ---- ---- ---- ---- ---- ---- ---a # Slow ADC channel run SADCPWR = 0x3163 # ---- ---- ---- ---- ---- ---- ---- -aaa # Slow ADC power SADCSTA = 0x3164 # ---- ---- ---- ---- ---- ---- -ret aiii # Slow ADC channel status read only L0TSIM = 0x3165 # ---- ---- ---- ---- --aa aaaa aaaa aaaa # L0 time for simulation SADCEC = 0x3166 # ---- ---- ---- ---- ---- ---- -daa ates # Slow ADC channel external control (not in trap2) SADCC0 = 0x3168 # ---- ---- ---- ---- ---- --AA AAAA AAAA # Slow ADC channel 0 SADCC1 = 0x3169 # ---- ---- ---- ---- ---- --AA AAAA AAAA # Slow ADC channel 1 SADCC2 = 0x316A # ---- ---- ---- ---- ---- --AA AAAA AAAA # Slow ADC channel 2 SADCC3 = 0x316B # ---- ---- ---- ---- ---- --AA AAAA AAAA # Slow ADC channel 3 SADCC4 = 0x316C # ---- ---- ---- ---- ---- --AA AAAA AAAA # Slow ADC channel 4 SADCC5 = 0x316D # ---- ---- ---- ---- ---- --AA AAAA AAAA # Slow ADC channel 5 SADCC6 = 0x316E # ---- ---- ---- ---- ---- --AA AAAA AAAA # Slow ADC channel 6 SADCC7 = 0x316F # ---- ---- ---- ---- ---- --AA AAAA AAAA # Slow ADC channel 7 SADCMC = 0x3170 # ---- ---- ---- ---- ---- ---- aaaa aaaa # Slow ADC measurement cycles SADCOC = 0x3171 # ---- ---- ---- ---- ---- ---- aaaa aaaa # Slow ADC o峴et measurement cycles SADCGTB = 0x3172 # hhhh gggg ffff eeee dddd cccc bbbb aaaa # Slow ADC gain table SADCTC = 0x3173 # ---- ---- ---- ---- ---- ---- ---- -aaa # Slow ADC temperature measurement cycles ADCCPU = 0x0100 # ---- ---- ---- ---- ---- -eaa aaaa aaaa # Direct ADC to CPU interface SEBDEN = 0x3178 # ---- ---- ---- ---- ---- ---- ---- -eee # Single ended bidir output enables SEBDOU = 0x3179 # ---- ---- ---- ---- ---- ---- ---- -ooo # Single ended bidir outputs SEBDIN = 0x317A # ---- ---- ---- ---- ---- ---- ---- -iii # Single ended bidir inputs (read only) CHIPID = 0x3160 # ---- ---- ---- --AA AAAA AAAA AAAA AAAA # Chip ID read only TPPT0 = 0x3000 # ---- ---- ---- ---- ---- ---- -ddd dddd # Common Timer Delay TPPAE = 0x3004 # ---- ---- ---- ---- ---- ---- -ddd dddd # Event Bu容r DataAcquisition End TPPGR = 0x3003 # ---- ---- ---- ---- ---- ---- -ddd dddd # Response Time to GSM FLBY = 0x3018 # ---- ---- ---- ---- ---- ---- ---- ---b # Nonlinearity Correction Filter Bypass FLL = 0x3100 # ---- ---- ---- ---- ---- ---- --dd dddd # Nonlinearity Correction Filter Look Up Table FPBY = 0x3019 # ---- ---- ---- ---- ---- ---- ---- ---b # Pedestal Correction Filter Bypass FPTC = 0x3020 # ---- ---- ---- ---- ---- ---- ---- --dd # Pedestal Correction Time Constant FPNP = 0x3021 # ---- ---- ---- ---- ---- ---d dddd dddd # Pedestal Correction Additive FPCL = 0x3022 # ---- ---- ---- ---- ---- ---- ---- ---b # Pedestal Correction Filter Clear FPA = 0x3060 # --dd dddd dddd dddd dddd dddd dddd dddd # Pedestal Correction Filter Accumulators FGBY = 0x301A # ---- ---- ---- ---- ---- ---- ---- ---b # Gain Correction Filter Bypass FGFn = 0x3080 # ---- ---- ---- ---- ---- ---d dddd dddd # Gain Correction Filter Factors FGAn = 0x30A0 # ---- ---- ---- ---- ---- ---- --dd dddd # Gain Correction Filter Additive FGTA = 0x3028 # ---- ---- ---- ---- ---- dddd dddd dddd # Gain Correction Counter Threshold A FGTB = 0x3029 # ---- ---- ---- ---- ---- dddd dddd dddd # Gain Correction Counter Threshold B FGCL = 0x302A # ---- ---- ---- ---- ---- ---- ---- ---b # Gain Correction Filter Clear FGCAn = 0x30C0 # ---- --dd dddd dddd dddd dddd dddd dddd # Gain Correction Filter Counter A FGCBn = 0x30C0 # ---- --dd dddd dddd dddd dddd dddd dddd # Gain Correction Filter Counter B FTBY = 0x301B # ---- ---- ---- ---- ---- ---- ---- ---b # Tail Cancellation Filter Bypass FTAL = 0x3030 # ---- ---- ---- ---- ---- --dd dddd dddd # Tail Cancellation Long Decay Weight FTLL = 0x3031 # ---- ---- ---- ---- ---- --dd dddd dddd # Tail Cancellation Long Decay Parameter FTLS = 0x3032 # ---- ---- ---- ---- ---- --dd dddd dddd # Tail Cancellation Short Decay Parameter FCBY = 0x301C # ---- ---- ---- ---- ---- ---- ---- ---b # Crosstalk Cancellation Filter Bypass FCWn = 0x3038 # ---- ---- ---- ---- ---- ---- dddd dddd # Crosstalk Cancellation Filter Weights TPFS = 0x3001 # ---- ---- ---- ---- ---- ---- -ddd dddd # Preprocessor s Linear Fit Start TPFE = 0x3002 # ---- ---- ---- ---- ---- ---- -ddd dddd # Preprocessor s Linear Fit End TPQS0 = 0x3005 # ---- ---- ---- ---- ---- ---- -ddd dddd # Charge Accumulator 0 Start TPQE0 = 0x3006 # ---- ---- ---- ---- ---- ---- -ddd dddd # Charge Accumulator 0 End TPQS1 = 0x3007 # ---- ---- ---- ---- ---- ---- -ddd dddd # Charge Accumulator 1 Start TPQE1 = 0x3008 # ---- ---- ---- ---- ---- ---- -ddd dddd # Charge Accumulator 1 End TPHT = 0x3041 # ---- ---- ---- ---- --dd dddd dddd dddd # Cluster Charge Threshold TPVBY = 0x3043 # ---- ---- ---- ---- ---- ---- ---- ---b # Cluster Verification Bypass TPVT = 0x3042 # ---- ---- ---- ---- ---- ---- --dd dddd # Cluster Quality Threshold TPFP = 0x3040 # ---- ---- ---- ---- ---- ---- --dd dddd # Filtered Pedestal TPL = 0x3180 # ---- ---- ---- ---- ---- ---- ---d dddd # Position Correction Look Up Table TPCL = 0x3045 # ---- ---- ---- ---- ---- ---- ---d dddd # Tracklet Candidate Left Hit Number Threshold TPCT = 0x3044 # ---- ---- ---- ---- ---- ---- ---d dddd # Tracklet Candidate Total Hit Number Threshold TPD = 0x3047 # ---- ---- ---- ---- ---- ---- ---- dddd # Tracklet Candidate Latch Delay TPH = 0x3140 # ---- ---- ---- ---- ---- ---- ---d dddd # Number of Hits in Channel n TPCBY = 0x3046 # ---- ---- ---- ---- ---- ---- ---- ---b # Test Indices Flag TPCI0 = 0x3048 # ---- ---- ---- ---- ---- ---- ---d dddd # Test Index for CPU 0 TPCI1 = 0x3049 # ---- ---- ---- ---- ---- ---- ---d dddd # Test Index for CPU 1 TPCI2 = 0x304A # ---- ---- ---- ---- ---- ---- ---d dddd # Test Index for CPU 2 TPCI3 = 0x304B # ---- ---- ---- ---- ---- ---- ---d dddd # Test Index for CPU 3 EBD = 0x3009 # ---- ---- ---- ---- ---- ---- ---- -ddd # Event Bu容r Input Delay EBSF = 0x300C # ---- ---- ---- ---- ---- ---- ---- ---b # Event Bu容r Storage Mode EBAQA = 0x300A # ---- ---- ---- ---- ---- ---- -ddd dddd # Event Bu容r Acquisition O峴et Address EBSIM = 0x300D # ---- ---- ---- ---- ---- ---- ---- ---b # Event Bu容r Simulation Mode EBSIA = 0x300B # ---- ---- ---- ---- ---- ---- -ddd dddd # Event Bu容r Simulation O峴et Address EBR = 0x0800 # ---- ---- ---- ---- ---- -pdd dddd dddd # Event Bu容r Data Read (LIO) EBR0 = 0x0800 # ---- ---- ---- ---- ---- -pdd dddd dddd # Event Bu容r Data Read (LIO) channel 0 EBR1 = 0x0840 # ---- ---- ---- ---- ---- -pdd dddd dddd # Event Bu容r Data Read (LIO) channel 1 EBR2 = 0x0880 # ---- ---- ---- ---- ---- -pdd dddd dddd # Event Bu容r Data Read (LIO) channel 2 EBR3 = 0x08C0 # ---- ---- ---- ---- ---- -pdd dddd dddd # Event Bu容r Data Read (LIO) channel 3 EBR4 = 0x0900 # ---- ---- ---- ---- ---- -pdd dddd dddd # Event Bu容r Data Read (LIO) channel 4 EBR5 = 0x0940 # ---- ---- ---- ---- ---- -pdd dddd dddd # Event Bu容r Data Read (LIO) channel 5 EBW = 0x2000 # ---- ---- ---- ---- ---- --dd dddd dddd # Event Bu容r Data Write EBPP = 0x300E # ---- ---- ---- ---- ---- ---- ---- ---b # Event Bu容r Parity Bit Mask EBPC = 0x300F # ---- ---- ---- ---- ---- ---- ---- ---b # Event Bu容r Parity Violation Counters Clear EBP0 = 0x3010 # ---- ---- ---- ---- ---- ---d dddd dddd # Event Bu容r Parity Violation Counter 0 EBP1 = 0x3011 # ---- ---- ---- ---- ---- ---d dddd dddd # Event Bu容r Parity Violation Counter 1 EBP2 = 0x3012 # ---- ---- ---- ---- ---- ---d dddd dddd # Event Bu容r Parity Violation Counter 2 EBP3 = 0x3013 # ---- ---- ---- ---- ---- ---d dddd dddd # Event Bu容r Parity Violation Counter 3 EBIS = 0x3014 # ---- ---- ---- ---- ---- --dd dddd dddd # Event Bu容r Single Indicator Threshold EBIT = 0x3015 # ---- ---- ---- ---- ---- dddd dddd dddd # Event Bu容r SumIndicator Threshold EBIL = 0x3016 # ---- ---- ---- ---- ---- ---- dddd dddd # Event Bu容r Indicator Look-up Table EBIN = 0x3017 # ---- ---- ---- ---- ---- ---- ---- ---b # Event Bu容r Indicator Neighbor Sensitivity EBI = 0x0980 # dddd dddd dddd dddd dddd dddd dddd dddd # Event Bu容r Indicators (LIO) ARBTIM = 0x0A3F # ---- ---- ---- ---- ---- ---- ---- wwrr # Configuration of the timing on the global bus MEMRW = 0xD000 # ---- ---- ---- ---- ---- ---- -www wrri # Configuration Global bus access to IMEM/DMEM MEMCOR = 0xD001 # ---- ---- ---- ---- ---- ---b dddd iiii # Configuration hamming correction IMEM/DMEM DMDELA = 0xD002 # ---- ---- ---- ---- ---- ---- ---- aaaa # Configuration internal timing in DMEM address lines DMDELS = 0xD003 # ---- ---- ---- ---- ---- ---- ---- ssss # Configuration internal timing in DMEM sense amplifiers HCNTI0 = 0xD010 # O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNNN # Hamming counters IMEM0 HCNTI1 = 0xD011 # O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNNN # Hamming counters IMEM1 HCNTI2 = 0xD012 # O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNNN # Hamming counters IMEM2 HCNTI3 = 0xD013 # O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNNN # Hamming counters IMEM3 HCNTD0 = 0xD014 # O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNNN # Hamming counters DMEM0 HCNTD1 = 0xD015 # O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNNN # Hamming counters DMEM1 HCNTD2 = 0xD016 # O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNNN # Hamming counters DMEM2 HCNTD3 = 0xD017 # O0CC CCCC CCCC PPPP PPPP PPNN NNNN NNNN # Hamming counters DMEM3 IA0 = 0x0B00 # ---- ---- ---- ---- ---- aaaa aaaa aaaa # Interrupt address CPU 0 IA1 = 0x0B20 # ---- ---- ---- ---- ---- aaaa aaaa aaaa # Interrupt address CPU 1 IA2 = 0x0B40 # ---- ---- ---- ---- ---- aaaa aaaa aaaa # Interrupt address CPU 2 IA3 = 0x0B60 # ---- ---- ---- ---- ---- aaaa aaaa aaaa # Interrupt address CPU 3 IRQSW0 = 0x0B0D # ---- ---- ---- ---- ---m mmmm mmmm mmmm # Mask software interrupts CPU 0 IRQSW1 = 0x0B2D # ---- ---- ---- ---- ---m mmmm mmmm mmmm # Mask software interrupts CPU 1 IRQSW2 = 0x0B4D # ---- ---- ---- ---- ---m mmmm mmmm mmmm # Mask software interrupts CPU 2 IRQSW3 = 0x0B6D # ---- ---- ---- ---- ---m mmmm mmmm mmmm # Mask software interrupts CPU 3 IRQHW0 = 0x0B0E # ---- ---- ---- ---- ---m mmmm mmmm mmmm # Mask hardware interrupts CPU 0 IRQHW1 = 0x0B2E # ---- ---- ---- ---- ---m mmmm mmmm mmmm # Mask hardware interrupts CPU 1 IRQHW2 = 0x0B4E # ---- ---- ---- ---- ---m mmmm mmmm mmmm # Mask hardware interrupts CPU 2 IRQHW3 = 0x0B6E # ---- ---- ---- ---- ---m mmmm mmmm mmmm # Mask hardware interrupts CPU 3 IRQHL0 = 0x0B0F # ---- ---- ---- ---- ---m mmmm mmmm mmmm # Mask high-level interrupts CPU 0 IRQHL1 = 0x0B2F # ---- ---- ---- ---- ---m mmmm mmmm mmmm # Mask high-level interrupts CPU 1 IRQHL2 = 0x0B4F # ---- ---- ---- ---- ---m mmmm mmmm mmmm # Mask high-level interrupts CPU 2 IRQHL3 = 0x0B6F # ---- ---- ---- ---- ---m mmmm mmmm mmmm # Mask high-level interrupts CPU 3 NMOD = 0x0D40 # ---- ---- ---- ---- ---- ---- ---i cmmm # NI network mode control NTRO = 0x0D43 # ---- ---- ---- --ii iddd cccb bbaa afff # NI trigger readout order NES = 0x0D45 # rrrr rrrr rrrr rrrr tttt tttt tttt tttt # NI end signatures NCUT = 0x0D4C # dddd dddd cccc cccc bbbb bbbb aaaa aaaa # NI cut trigger stream NRRO = 0x0D44 # ---- ---- ---- --ii iddd cccb bbaa afff # NI raw data readout order NTP = 0x0D46 # pppp pppp pppp pppp pppp pppp pppp pppp # NI test pattern NP0 = 0x0D48 # ---- ---- ---- ---- ---- -ppp pfff fecs # NI input port 0 control NP1 = 0x0D49 # ---- ---- ---- ---- ---- -ppp pfff fecs # NI input port 1 control NP2 = 0x0D4A # ---- ---- ---- ---- ---- -ppp pfff fecs # NI input port 2 control NP3 = 0x0D4B # ---- ---- ---- ---- ---- -ppp pfff fecs # NI input port 3 control NLP = 0x00C1 # ---- ---- HHHH HHHH LLLL LLLL CCCC CCCC # NI (LIO) parity and word counter NED = 0x0D42 # ---- ---- ---- ---- orpp ppff ffcc csss # NI output excludes and ctrl delay NDLY = 0x0D41 # --jj jiii hhhg ggff feee dddc ccbb baaa # NI data delays NBND = 0x0D47 # ---- ---- ---- ---- hhhh hhhh llll llll # NI fifo bounds NLF = 0x00C0 # ---- ---- ---- ---- ---- -DSS EHLZ YXWV # NI (LIO) FIFO states NLE = 0x00C2 # ---- ---- ---- ---- ---- ---- EEEE EEEE # NI (LIO) FIFO entries NFE = 0x0DC1 # ---- ---- ---- ---- ---- ---- ---- DCBA # NI fifo errors NCTRL = 0x0DC0 # ---- ---- ---- ---- ---- ---- ---- ---C # NI control input NFSM = 0x0DC2 # ---- ---- ---- ---- ---- ---- ---S SSSS # NI FSM state NITM0 = 0x0A08 # ---- ---- ---- ---- --tt tttt tttt tttt # NI timer 0 NITM1 = 0x0A09 # ---- ---- ---- ---- --tt tttt tttt tttt # NI timer 1 NITM2 = 0x0A0A # ---- ---- ---- ---- --tt tttt tttt tttt # NI timer 2 NIP4D = 0x0A0B # ---- ---- ---- ---- --tt tttt tttt tttt # NI port 4 delay SMOFFON = 0x0A05 # ---- ---- dddd dddd dddd dddd dddd dddd # GSM command register for switching clock/enable, W/O SMON = 0x0A06 # ---- ---- ---- ---- ---- dddd dddd dddd # GSM command register for switching on clock/enable, W/O SMOFF = 0x0A07 # ---- ---- ---- ---- ---- dddd dddd dddd # GSM command register for switching off clock/enable, W/O NODP = 0x0000 # dddd dddd dddd dddd dddd dddd dddd dddd # NI output data port (LIO), W/O CMD_LP = 0x0012 # ---- ---- ---- ---- ---- ---- ---- ---- # go to low power state CMD_ACQ = 0x0112 # ---- ---- ---- ---- ---- ---- ---- ---- # go to acquisition state CMD_CHK_TST = 0x0212 # ---- ---- ---- ---- ---- ---- ---- ---- # go to test mode CMD_EXT_CLR = 0x0312 # ---- ---- ---- ---- ---- ---- ---- ---- # exit clear state CMD_CLEAR = 0x0412 # ---- ---- ---- ---- ---- ---- ---- ---- # go to clear state CMD_PRETRIGG = 0x0512 # ---- ---- ---- ---- ---- ---- ---- ---- # internally generate pretrigger CMD_SELFTP = 0x0612 # ---- ---- ---- ---- ---- ---- ---- ---- # start the self-test state machine CMD_CPU_DONE = 0x0712 # ---- ---- ---- ---- ---- ---- ---- ---- # CPU finished the tracklet processing or raw data compression