TDA  - Timing Driven Analyze 
Ver. 1.0, supported by Lattice Semiconductor
ispLEVER 5.00 Copyright 1992-2005 Lattice Semiconductor. All Rights Reserved.
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Summary for Timing Constraints:

Goal: Clock Period on clock domain "clk" of 8.00ns (125.00MHz) is met.
      Worst case path:
      From  : ni_nires_reg_data_out_17_.C
      to    : ni_reg_prty_bit_neg_r.D
      Actual: 7.95ns (125.79MHz)
      Slack : 0.05ns

Goal: Clock Period on clock domain "NI_STR" of 8.33ns (120.05MHz) is met.
      Worst case path:
      From  : ni_nires_reg_gray_cntf_0_.C
      to    : ni_nires_reg_data0neg_0_.CE
      Actual: 4.90ns (204.08MHz)
      Slack : 3.43ns

Goal: Clock Period on clock domain "jTCK" of 1000.00ns (1.00MHz) is met.
      Worst case path:
      From  : j2c_bitcnt_2_.C
      to    : j2c_reg_clear.CE
      Actual: 7.00ns (142.86MHz)
      Slack : 993.00ns

  Total constraints: 3, passed: 3, not passed: 0