Timing Report // Project = oase // Family = lc4k // Device = LC4256V // Speed = -3 // Voltage = 3.3 // Operating Condition = COM // Data sheet version = 3.2 // Pass Bidirection = OFF // Pass S/R = OFF // Pass Latch = OFF // Pass Clock = OFF // Maximum Paths = 20 // T_SU Endpoints D/T inputs = ON // T_SU Endpoints CE inputs = OFF // T_SU Endpoints S/R inputs = OFF // T_SU Endpoints RAM gated = ON // Fmax of CE = ON // Fmax of RAM = ON // Location(From => To) // Pin number: numeric number preceded by "p", BGA number as is // Macrocell number: Segment#,GLB#,Macrocell# // Segment#: starts from 0 (if applicable) // GLB#: starts from A..Z, AA..ZZ // Macrocell#: starts from 0 to 31 Summary for Timing Constraints: -- fMAX_0 = 7.95 ns ( 8.00) : passed with slack = 0.05 (125.79 MHz) -- fMAX_1 = 4.90 ns ( 8.33) : passed with slack = 3.43 (204.08 MHz) -- fMAX_2 = 7.00 ns (1000.00) : passed with slack = 993.00 (142.86 MHz) Total constraints: 3, passed: 3, not passed: 0 fMAX_0 = 8.00 , "clk ", "clk "; Slack Req. Delay Level Location(From => To) Source Destination Destination_Clock ===== ==== ===== ===== ==================== ====== =========== ================= 0.05 8.00 7.95 3 G10 => E2 ni_nires_reg_data_out_17_.C ni_reg_prty_bit_neg_r.D clk 0.10 8.00 7.90 3 H10 => O4 ni_nires_reg_data_out_4_.C ni_reg_prty_bit_pos_r.D clk 0.85 8.00 7.15 2 K11 => O9 TX_EN.C TXD_0_.CE clk 0.85 8.00 7.15 2 K11 => O10 TX_EN.C TXD_1_.CE clk 0.85 8.00 7.15 2 K11 => O1 TX_EN.C TXD_2_.CE clk 0.85 8.00 7.15 2 K11 => N12 TX_EN.C TXD_3_.CE clk 0.85 8.00 7.15 2 K11 => N10 TX_EN.C TXD_4_.CE clk 0.85 8.00 7.15 2 K11 => N6 TX_EN.C TXD_5_.CE clk 0.85 8.00 7.15 2 K11 => N4 TX_EN.C TXD_6_.CE clk 0.85 8.00 7.15 2 K11 => M0 TX_EN.C TXD_7_.CE clk 0.85 8.00 7.15 2 K11 => M12 TX_EN.C TXD_8_.CE clk 0.85 8.00 7.15 2 K11 => M4 TX_EN.C TXD_9_.CE clk 0.85 8.00 7.15 2 K11 => L6 TX_EN.C TXD_10_.CE clk 0.85 8.00 7.15 2 K11 => L9 TX_EN.C TXD_11_.CE clk 0.85 8.00 7.15 2 K11 => L10 TX_EN.C TXD_12_.CE clk 0.85 8.00 7.15 2 K11 => L3 TX_EN.C TXD_13_.CE clk 0.85 8.00 7.15 2 K11 => K2 TX_EN.C TXD_14_.CE clk 0.85 8.00 7.15 2 K11 => K12 TX_EN.C TXD_15_.CE clk 0.90 8.00 7.10 2 A14 => A14 ni_nires_reg_old_cnt_0_.C ni_nires_reg_old_cnt_0_.CE clk 0.90 8.00 7.10 2 A14 => A15 ni_nires_reg_old_cnt_0_.C ni_nires_reg_old_cnt_1_.CE clk fMAX_1 = 8.33 , "NI_STR ", "NI_STR "; Slack Req. Delay Level Location(From => To) Source Destination Destination_Clock ===== ==== ===== ===== ==================== ====== =========== ================= 3.43 8.33 4.90 1 M14 => L7 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_0_.CE NI_STR 3.43 8.33 4.90 1 M14 => M5 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_1_.CE NI_STR 3.43 8.33 4.90 1 M14 => G2 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_2_.CE NI_STR 3.43 8.33 4.90 1 M14 => F7 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_3_.CE NI_STR 3.43 8.33 4.90 1 M14 => L14 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_4_.CE NI_STR 3.43 8.33 4.90 1 M14 => P12 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_5_.CE NI_STR 3.43 8.33 4.90 1 M14 => O11 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_6_.CE NI_STR 3.43 8.33 4.90 1 M14 => O15 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_7_.CE NI_STR 3.43 8.33 4.90 1 M14 => G7 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_8_.CE NI_STR 3.43 8.33 4.90 1 M14 => M9 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_9_.CE NI_STR 3.43 8.33 4.90 1 M14 => L5 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_0_.CE NI_STR 3.43 8.33 4.90 1 M14 => M3 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_1_.CE NI_STR 3.43 8.33 4.90 1 M14 => G1 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_2_.CE NI_STR 3.43 8.33 4.90 1 M14 => F6 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_3_.CE NI_STR 3.43 8.33 4.90 1 M14 => L13 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_4_.CE NI_STR 3.43 8.33 4.90 1 M14 => P11 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_5_.CE NI_STR 3.43 8.33 4.90 1 M14 => O8 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_6_.CE NI_STR 3.43 8.33 4.90 1 M14 => O14 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_7_.CE NI_STR 3.43 8.33 4.90 1 M14 => G6 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_8_.CE NI_STR 3.43 8.33 4.90 1 M14 => M8 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_9_.CE NI_STR fMAX_2 = 1000.00 , "jTCK ", "jTCK "; Slack Req. Delay Level Location(From => To) Source Destination Destination_Clock ===== ==== ===== ===== ==================== ====== =========== ================= 993.00 1000.00 7.00 2 K15 => K1 j2c_bitcnt_2_.C j2c_reg_clear.CE jTCK 993.00 1000.00 7.00 2 K15 => K3 j2c_bitcnt_2_.C j2c_reg_rstout_n_i.CE jTCK 996.75 1000.00 3.25 1 K7 => K7 j2c_bitcnt_0_.C j2c_bitcnt_0_.D jTCK 996.75 1000.00 3.25 1 K4 => K4 j2c_bitcnt_1_.C j2c_bitcnt_1_.D jTCK 996.75 1000.00 3.25 1 K15 => K15 j2c_bitcnt_2_.C j2c_bitcnt_2_.D jTCK 996.75 1000.00 3.25 1 K15 => K1 j2c_bitcnt_2_.C j2c_reg_clear.D jTCK 996.75 1000.00 3.25 1 K15 => K3 j2c_bitcnt_2_.C j2c_reg_rstout_n_i.D jTCK 996.80 1000.00 3.20 1 P15 => N5 j2c_reg_shreg_7_.C j2c_reg_shreg_6_.D jTCK 996.85 1000.00 3.15 1 O6 => O7 j2c_reg_shreg_4_.C j2c_reg_shreg_3_.D jTCK 996.85 1000.00 3.15 1 I4 => O6 j2c_reg_shreg_5_.C j2c_reg_shreg_4_.D jTCK 996.90 1000.00 3.10 1 B15 => B7 j2c_reg_shreg_1_.C j2c_reg_shreg_0_.D jTCK 996.90 1000.00 3.10 1 B0 => B15 j2c_reg_shreg_2_.C j2c_reg_shreg_1_.D jTCK 996.90 1000.00 3.10 1 O7 => B0 j2c_reg_shreg_3_.C j2c_reg_shreg_2_.D jTCK 996.90 1000.00 3.10 1 N5 => I4 j2c_reg_shreg_6_.C j2c_reg_shreg_5_.D jTCK