[Device]
Family = lc4k;
PartNumber = LC4256V-3T100C;
Package = 100TQFP;
PartType = LC4256V;
Speed = -3;
Operating_condition = COM;
Status = Production;
EN_PinGLB = No;
EN_PinMacrocell = No;

[Revision]
Parent = lc4k256v.lci;
DATE = 05/17/2006;
TIME = 12:16:20;
Synthesis = Exemplar;
Source_Format = EDIF;

[Ignore Assignments]
Pin_Assignments = NO;
Pin_Keep_Block = NO;
Pin_Keep_Segment = NO;
Group_Assignments = NO;
Macrocell_Assignments = NO;
Macrocell_Keep_Block = NO;
Macrocell_Keep_Segment = NO;
Pin_Reservation = NO;
Timing_Constraints = NO;
IO_Types = NO;
All_Device_Constraints = NO;
Region = NO;

[Clear Assignments]

[Backannotate Assignments]
Pin_Block = NO;
Pin_Macrocell_Block = NO;
Pin_Assignments = YES;
IO_Types = NO;

[Global Constraints]

[Location Assignments]
layer = OFF;
NI_D_0_ = Pin, 20, -, F, 6;
NI_D_1_ = Pin, 19, -, F, 2;
NI_D_2_ = Pin, 17, -, E, 12;
NI_D_3_ = Pin, 16, -, E, 10;
NI_D_4_ = Pin, 15, -, E, 6;
NI_D_5_ = Pin, 14, -, E, 4;
NI_D_6_ = Pin, 11, -, D, 4;
NI_D_7_ = Pin, 10, -, D, 6;
NI_D_8_ = Pin, 9, -, D, 10;
NI_D_9_ = Pin, 8, -, D, 12;
NI_STR = Pin, 6, -, C, 2;
TXD_0_ = Pin, 80, -, O, 6;
TXD_1_ = Pin, 79, -, O, 10;
TXD_2_ = Pin, 78, -, O, 12;
TXD_3_ = Pin, 72, -, N, 12;
TXD_4_ = Pin, 71, -, N, 10;
TXD_5_ = Pin, 70, -, N, 6;
TXD_6_ = Pin, 69, -, N, 2;
TXD_7_ = Pin, 67, -, M, 12;
TXD_8_ = Pin, 65, -, M, 6;
TXD_9_ = Pin, 64, -, M, 4;
TXD_10_ = Pin, 61, -, L, 4;
TXD_11_ = Pin, 60, -, L, 6;
TXD_12_ = Pin, 59, -, L, 10;
TXD_13_ = Pin, 58, -, L, 12;
TXD_14_ = Pin, 56, -, K, 2;
TXD_15_ = Pin, 55, -, K, 6;
TX_EN = Pin, 54, -, K, 10;
LED_5_ = Pin, 92, -, A, 6;
LED_6_ = Pin, 93, -, A, 10;
LED_7_ = Pin, 94, -, A, 12;
LED_8_ = Pin, 41, -, I, 2;
LED_9_ = Pin, 42, -, I, 6;
LED_10_ = Pin, 43, -, I, 10;
LOOPEN = Pin, 53, -, K, 12;
PRBSEN = Pin, 47, -, J, 2;
TESTEN = Pin, 44, -, I, 12;
TX_ER = Pin, 50, -, J, 12;
EN = Pin, 84, -, P, 12;
ENABLE = Pin, 49, -, J, 10;
FAULT = Pin, 81, -, O, 2;
LCKREFN = Pin, 48, -, J, 6;
reset_n = Pin, 100, -, B, 12;
clk = Pin, 66, -, M, 10;
jTCK = Pin, 38, -, -, -;
jTMS = Pin, 87, -, P, 2;
jTDI = Pin, 88, -, -, -;
jTDO = Pin, 21, -, F, 10;
SCL = Pin, 98, -, B, 6;
SDA = Pin, 97, -, B, 2;
DIS_JTG = Pin, 99, -, B, 10;
SD2ANL = Pin, 3, -, C, 12;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;
PIN = 5, Input;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]

[IO Types]
layer = OFF;
LED_5_ = LVCMOS33, PIN, 0, -;
LED_6_ = LVCMOS33, PIN, 0, -;
LED_7_ = LVCMOS33, PIN, 0, -;
LED_8_ = LVCMOS33, PIN, 1, -;
LED_9_ = LVCMOS33, PIN, 1, -;
LED_10_ = LVCMOS33, PIN, 1, -;
LOOPEN = LVCMOS33, PIN, 1, -;
PRBSEN = LVCMOS33, PIN, 1, -;
TESTEN = LVCMOS33, PIN, 1, -;
TX_ER = LVCMOS33, PIN, 1, -;
EN = LVCMOS33, PIN, 1, -;
ENABLE = LVCMOS33, PIN, 1, -;
LCKREFN = LVCMOS33, PIN, 1, -;
jTDO = LVCMOS33, PIN, 0, -;
SCL = LVCMOS33, PIN, 0, -;
SDA = LVCMOS33, PIN, 0, -;
NI_D_0_ = LVCMOS33, PIN, 0, -;
NI_D_1_ = LVCMOS33, PIN, 0, -;
NI_D_2_ = LVCMOS33, PIN, 0, -;
NI_D_3_ = LVCMOS33, PIN, 0, -;
NI_D_4_ = LVCMOS33, PIN, 0, -;
NI_D_5_ = LVCMOS33, PIN, 0, -;
NI_D_6_ = LVCMOS33, PIN, 0, -;
NI_D_7_ = LVCMOS33, PIN, 0, -;
NI_D_8_ = LVCMOS33, PIN, 0, -;
NI_D_9_ = LVCMOS33, PIN, 0, -;
NI_STR = LVCMOS33, PIN, 0, -;
TXD_0_ = LVCMOS33, PIN, 1, -;
TXD_1_ = LVCMOS33, PIN, 1, -;
TXD_2_ = LVCMOS33, PIN, 1, -;
TXD_3_ = LVCMOS33, PIN, 1, -;
TXD_4_ = LVCMOS33, PIN, 1, -;
TXD_5_ = LVCMOS33, PIN, 1, -;
TXD_6_ = LVCMOS33, PIN, 1, -;
TXD_7_ = LVCMOS33, PIN, 1, -;
TXD_8_ = LVCMOS33, PIN, 1, -;
TXD_9_ = LVCMOS33, PIN, 1, -;
TXD_10_ = LVCMOS33, PIN, 1, -;
TXD_11_ = LVCMOS33, PIN, 1, -;
TXD_12_ = LVCMOS33, PIN, 1, -;
TXD_13_ = LVCMOS33, PIN, 1, -;
TXD_14_ = LVCMOS33, PIN, 1, -;
TXD_15_ = LVCMOS33, PIN, 1, -;
TX_EN = LVCMOS33, PIN, 1, -;
reset_n = LVCMOS33, PIN, 0, -;
clk = LVCMOS33, PIN, 1, -;
FAULT = LVCMOS33, PIN, 1, -;
jTCK = LVCMOS33, PIN, 0, -;
jTMS = LVCMOS33, PIN, 1, -;
jTDI = LVCMOS33, PIN, 1, -;
DIS_JTG = LVCMOS33, PIN, 0, -;
SD2ANL = LVCMOS33, PIN, 0, -;

[Pullup]

[Slewrate]
SLOW = LED_5_, LED_6_, LED_7_, LED_8_, LED_9_, LED_10_, LOOPEN, PRBSEN, TESTEN, 
	TX_ER, EN, ENABLE, LCKREFN, jTDO, SCL, SDA, SD2ANL;

[Region]

[Timing Constraints]
layer = OFF;
fMAX_0 = 7.6923, clk, clk;
fMAX_1 = 7.6923, NI_STR, NI_STR;
fMAX_2 = 1000.0000, jTCK, jTCK;

[HSI Attributes]

[Input Delay]

[opt global constraints list]

[Explorer User Settings]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[Pin attributes list]

[individual constraints list]

[Attributes list setting]

[Timing Analyzer]

[PLL Assignments]

[Register Powerup]
RESET = j2c_reg_creg0i_1_, j2c_reg_creg0i_2_, j2c_reg_creg0i_4_, j2c_reg_creg0i_5_, 
	j2c_reg_creg0i_6_;
SET = j2c_reg_creg0i_7_, j2c_reg_creg0i_0_, j2c_reg_creg0i_3_;

[global constraints list]

[Global Constraints Process Update]

[Explorer Results]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[Constraint Version]
version = 1.0;

[Node attribute]
layer = OFF;

[SYMBOL/MODULE attribute]
layer = OFF;

[Nodal Constraints]
layer = OFF;

[ORP Bypass]

[CPLD OPT Timing Constraints]
fMax_0 = clk, 2;
fMax_1 = NI_STR, 1;
fMax_2 = jTCK, 2;

[CPLD OPT Critical Paths]
ni_reg_prty_bit_neg_r = 80, 80, 36;
nx1967 = 80, 80, 36;
nx1999 = 80, 80, 36;