[DEVICE] Family = lc4k; PartType = LC4256V; Package = 100TQFP; PartNumber = LC4256V-3T100C; Speed = -3; Operating_condition = COM; EN_Segment = Yes; Pin_MC_1to1 = No; Default_Device_Io_Types = LVCMOS18, -; Voltage = 3.3; [REVISION] RCS = "$Header $"; Parent = lc4k256v.lci; Design = ; DATE = 09/05/2006; TIME = 11:22:48; Source_Format = EDIF; Type = ; Pre_Fit_Time = ; [IGNORE ASSIGNMENTS] Pin_Assignments = No; Pin_Keep_Block = No; Pin_Keep_Segment = No; Group_Assignments = No; Macrocell_Assignments = No; Macrocell_Keep_Block = No; Macrocell_Keep_Segment = No; Pin_Reservation = No; Block_Reservation = No; Segment_Reservation = No; Timing_Constraints = No; IO_Types = No; [CLEAR ASSIGNMENTS] Pin_Assignments = No; Pin_Keep_Block = No; Pin_Keep_Segment = No; Group_Assignments = No; Macrocell_Assignments = No; Macrocell_Keep_Block = No; Macrocell_Keep_Segment = No; Pin_Reservation = No; Block_Reservation = No; Segment_Reservation = No; Timing_Constraints = No; IO_Types = No; [BACKANNOTATE ASSIGNMENTS] Pin_Assignment = Yes; Pin_Block = No; Pin_Macrocell_Block = No; Routing = No; Io_Types = No; [GLOBAL CONSTRAINTS] Max_Fanin = 24; Max_PTerm_Split = 80; Max_PTerm_Collapse = 16; Max_Pin_Percent = 100; Max_Macrocell_Percent = 100; Max_GLB_Input_Percent = 100; Logic_Reduction = Yes; XOR_Synthesis = Yes; Keep_XOR = No; DT_Synthesis = Yes; Node_Collapse = Yes; Nodes_collapsing_mode = FMAX; Fmax_Logic_Level = 1; Use_CE = Yes; Use_Internal_COM_FB = Yes; Set_Reset_Swap = No; Clock_Optimize = No; EN_Set_Reset_Dont_Care = No; TOE_AS_IO = No; Set_Reset_Dont_Care = No; EN_In_Reg_Optimize = No; In_Reg_Optimize = Yes; Run_Time = 0; Routing_Attempts = 2; Balanced_Partitioning = Yes; Spread_Placement = Yes; Usercode = ; Usercode_Format = HEX; Vcc = ; Dual_Function_Macrocell = 1; Global_PTOE = Yes; Hard_Fast_Bypass = No; Fitter_Effort_Level = LOW; Auto_buffering_for_high_glb_fanin = Off; Auto_buffering_for_low_bonded_io = Off; User_max_glb_fanin = 36; Adjust_input_assignments = Off; [LOCATION ASSIGNMENTS] layer = OFF; ni_nires_reg_data_out_10_ = node, -, -, A, 4; ni_nires_reg_data_out_14_ = node, -, -, A, 5; ni_nires_reg_data3pos_5_ = node, -, -, A, 8; ni_nires_reg_data3pos_8_ = node, -, -, A, 9; ni_nires_reg_data1pos_8_ = node, -, -, A, 10; ni_nires_reg_data0pos_8_ = node, -, -, A, 11; ni_nires_reg_data2pos_8_ = node, -, -, A, 12; ni_nires_reg_old_cnt_0_ = node, -, -, A, 14; ni_nires_reg_old_cnt_1_ = node, -, -, A, 15; ni_nires_reg_data_out_1_ = node, -, -, A, 6; ID_2_2_ = node, -, -, A, 13; ID_2_1_ = node, -, -, A, 2; ID_2_0_ = node, -, -, A, 3; ni_nires_reg_data_out_9_ = node, -, -, A, 7; ni_nires_reg_gray_cnt_1_ = node, -, -, A, 0; ni_nires_reg_gray_cnt_0_ = node, -, -, A, 1; reset_n = pin, 100, -, B, 12; DIS_JTG = pin, 99, -, B, 10; SCL = pin, 98, -, B, 9; SDA = pin, 97, -, B, 8; ni_nires_reg_data_out_16_ = node, -, -, B, 10; ni_nires_reg_data_out_18_ = node, -, -, B, 11; j2c_reg_creg0hm_4_ = node, -, -, B, 14; j2c_reg_shreg_1_ = node, -, -, B, 15; j2c_reg_shreg_2_ = node, -, -, B, 0; j2c_reg_creg0hm_6_ = node, -, -, B, 4; j2c_reg_creg0hm_5_ = node, -, -, B, 5; j2c_reg_creg0hm_2_ = node, -, -, B, 6; j2c_reg_shreg_0_ = node, -, -, B, 7; j2c_reg_creg0hm_1_ = node, -, -, B, 1; j2c_reg_creg0hm_3_ = node, -, -, B, 2; j2c_reg_creg0hm_0_ = node, -, -, B, 3; ni_nires_reg_data_out_5_ = node, -, -, B, 12; ni_nires_reg_data_out_6_ = node, -, -, B, 13; NI_STR = pin, 6, -, C, 2; SD2ANL = pin, 3, -, C, 12; nx1195 = node, -, -, C, 4; ni_reg_ce_prty_bit_pos = node, -, -, C, 10; ID_0_6_ = node, -, -, C, 3; ID_0_5_ = node, -, -, C, 5; ID_0_4_ = node, -, -, C, 15; ID_0_2_ = node, -, -, C, 13; ID_0_1_ = node, -, -, C, 1; ID_0_7_ = node, -, -, C, 6; ID_1_4_ = node, -, -, C, 7; ID_1_3_ = node, -, -, C, 0; ID_1_2_ = node, -, -, C, 11; ID_1_1_ = node, -, -, C, 14; ID_1_0_ = node, -, -, C, 2; ID_1_5_ = node, -, -, C, 8; ID_1_6_ = node, -, -, C, 9; NI_D_9_ = pin, 8, -, D, 12; NI_D_8_ = pin, 9, -, D, 10; NI_D_7_ = pin, 10, -, D, 6; NI_D_6_ = pin, 11, -, D, 4; ID_3_5_ = node, -, -, D, 12; ID_3_6_ = node, -, -, D, 13; ID_3_4_ = node, -, -, D, 1; ID_3_3_ = node, -, -, D, 8; ID_3_2_ = node, -, -, D, 0; ID_3_1_ = node, -, -, D, 3; ID_3_0_ = node, -, -, D, 4; ID_2_5_ = node, -, -, D, 5; ID_2_6_ = node, -, -, D, 6; ID_2_4_ = node, -, -, D, 2; ID_2_3_ = node, -, -, D, 14; nx1912 = node, -, -, D, 9; ID_0_3_ = node, -, -, D, 15; ID_0_0_ = node, -, -, D, 7; ID_3_5__0 = node, -, -, D, 10; ID_2_5__0 = node, -, -, D, 11; NI_D_5_ = pin, 14, -, E, 4; NI_D_4_ = pin, 15, -, E, 6; NI_D_3_ = pin, 16, -, E, 10; NI_D_2_ = pin, 17, -, E, 12; ni_nires_reg_data0pos_1_ = node, -, -, E, 8; ni_nires_reg_data2pos_1_ = node, -, -, E, 9; ni_nires_reg_data3pos_9_ = node, -, -, E, 10; ni_nires_reg_data1pos_9_ = node, -, -, E, 11; ni_nires_reg_data0pos_9_ = node, -, -, E, 12; ni_nires_reg_data2pos_9_ = node, -, -, E, 13; ix1578 = node, -, -, E, 3; nx1595 = node, -, -, E, 4; ix1598 = node, -, -, E, 6; ix1610 = node, -, -, E, 7; nx1647 = node, -, -, E, 5; ni_reg_prty_bit_neg_r = node, -, -, E, 2; ix385 = node, -, -, E, 1; ni_nires_reg_data3pos_1_ = node, -, -, E, 14; ni_nires_reg_data1pos_1_ = node, -, -, E, 15; NI_D_1_ = pin, 19, -, F, 2; NI_D_0_ = pin, 20, -, F, 6; jTDO = pin, 21, -, F, 10; ni_nires_reg_data3pos_2_ = node, -, -, F, 8; ni_nires_reg_data1pos_2_ = node, -, -, F, 9; ni_nires_reg_data0pos_2_ = node, -, -, F, 11; ni_nires_reg_data2pos_2_ = node, -, -, F, 12; ni_nires_reg_data3pos_3_ = node, -, -, F, 13; ni_nires_reg_data1pos_3_ = node, -, -, F, 14; ni_nires_reg_data0pos_3_ = node, -, -, F, 15; ni_nires_reg_data2pos_3_ = node, -, -, F, 0; nx1519 = node, -, -, F, 3; ix1524 = node, -, -, F, 4; nx1717 = node, -, -, F, 1; nx1909 = node, -, -, F, 2; ni_nires_reg_data3neg_3_ = node, -, -, F, 5; ni_nires_reg_data1neg_3_ = node, -, -, F, 6; ni_nires_reg_data0neg_3_ = node, -, -, F, 7; ni_nires_reg_data_out_12_ = node, -, -, G, 9; ni_nires_reg_data_out_17_ = node, -, -, G, 10; ni_nires_reg_valid = node, -, -, G, 11; nx975 = node, -, -, G, 15; ni_nires_reg_data3neg_2_ = node, -, -, G, 0; ni_nires_reg_data1neg_2_ = node, -, -, G, 1; ni_nires_reg_data0neg_2_ = node, -, -, G, 2; ni_nires_reg_data2neg_2_ = node, -, -, G, 3; ni_nires_reg_data_out_3_ = node, -, -, G, 12; ni_nires_reg_data2neg_3_ = node, -, -, G, 4; ni_nires_reg_data_out_8_ = node, -, -, G, 13; ni_nires_reg_data3neg_8_ = node, -, -, G, 5; ni_nires_reg_data1neg_8_ = node, -, -, G, 6; ni_nires_reg_data0neg_8_ = node, -, -, G, 7; ni_nires_reg_data2neg_8_ = node, -, -, G, 8; ni_nires_reg_data_out_11_ = node, -, -, G, 14; ni_nires_reg_data3pos_0_ = node, -, -, H, 11; ni_nires_reg_data1pos_0_ = node, -, -, H, 12; ni_nires_reg_data0pos_0_ = node, -, -, H, 13; ni_nires_reg_data2pos_0_ = node, -, -, H, 14; ni_nires_reg_data3pos_4_ = node, -, -, H, 15; ni_nires_reg_data1pos_4_ = node, -, -, H, 0; ni_nires_reg_data0pos_4_ = node, -, -, H, 1; ni_nires_reg_data2pos_4_ = node, -, -, H, 2; ni_nires_reg_data_out_15_ = node, -, -, H, 7; ni_nires_reg_data1pos_5_ = node, -, -, H, 3; ni_nires_reg_data0pos_5_ = node, -, -, H, 4; ni_nires_reg_data2pos_5_ = node, -, -, H, 5; nx0 = node, -, -, H, 6; ni_nires_reg_data_out_19_ = node, -, -, H, 8; ni_nires_reg_data_out_0_ = node, -, -, H, 9; ni_nires_reg_data_out_4_ = node, -, -, H, 10; TESTEN = pin, 44, -, I, 12; nx1361 = node, -, -, I, 10; j2c_reg_creg1hm_2_ = node, -, -, I, 15; j2c_reg_cmdreg_0_ = node, -, -, I, 3; j2c_reg_shreg_5_ = node, -, -, I, 4; j2c_reg_cmdreg_3_ = node, -, -, I, 11; j2c_reg_creg1hm_5_ = node, -, -, I, 5; j2c_reg_creg1hm_4_ = node, -, -, I, 6; j2c_reg_creg1hm_3_ = node, -, -, I, 0; j2c_reg_creg1hm_1_ = node, -, -, I, 1; j2c_reg_creg1hm_0_ = node, -, -, I, 2; j2c_reg_cmdreg_2_ = node, -, -, I, 7; j2c_reg_cmdreg_1_ = node, -, -, I, 8; ni_reg_ce_prty_bit_neg = node, -, -, I, 13; nx244 = node, -, -, I, 9; ni_nires_reg_data_out_7_ = node, -, -, I, 14; PRBSEN = pin, 47, -, J, 2; LCKREFN = pin, 48, -, J, 6; ENABLE = pin, 49, -, J, 14; TX_ER = pin, 50, -, J, 15; nx2236 = node, -, -, J, 3; nx2272 = node, -, -, J, 5; nx1271 = node, -, -, J, 12; ni_nires_reg_data_out_13_ = node, -, -, J, 8; nx2294 = node, -, -, J, 9; ni_nires_reg_clear_n_i = node, -, -, J, 13; nx1759 = node, -, -, J, 4; nx1815 = node, -, -, J, 7; nx1851 = node, -, -, J, 10; ix373 = node, -, -, J, 0; ix397 = node, -, -, J, 1; ni_nires_reg_data_out_2_ = node, -, -, J, 11; LOOPEN = pin, 53, -, K, 13; TX_EN = pin, 54, -, K, 11; TXD_15_ = pin, 55, -, K, 12; TXD_14_ = pin, 56, -, K, 2; ni_pattcount_2_ = node, -, -, K, 5; ni_pattcount_1_ = node, -, -, K, 8; ni_pattcount_0_ = node, -, -, K, 10; ni_pattcount_4_ = node, -, -, K, 6; ni_pattcount_3_ = node, -, -, K, 0; j2c_reg_clear = node, -, -, K, 1; j2c_reg_rstout_n_i = node, -, -, K, 3; j2c_bitcnt_2_ = node, -, -, K, 15; j2c_bitcnt_1_ = node, -, -, K, 4; j2c_bitcnt_0_ = node, -, -, K, 7; ix1771 = node, -, -, K, 14; j2c_reg_clear_0 = node, -, -, K, 9; TXD_13_ = pin, 58, -, L, 3; TXD_12_ = pin, 59, -, L, 10; TXD_11_ = pin, 60, -, L, 9; TXD_10_ = pin, 61, -, L, 6; nx1725 = node, -, -, L, 2; ix1773 = node, -, -, L, 12; ix1775 = node, -, -, L, 1; ni_nires_reg_data3neg_0_ = node, -, -, L, 4; ni_nires_reg_data1neg_0_ = node, -, -, L, 5; ni_nires_reg_data0neg_0_ = node, -, -, L, 7; ni_nires_reg_data2neg_0_ = node, -, -, L, 8; ni_nires_reg_data3neg_4_ = node, -, -, L, 11; ni_nires_reg_data1neg_4_ = node, -, -, L, 13; ni_nires_reg_data0neg_4_ = node, -, -, L, 14; ni_nires_reg_data2neg_4_ = node, -, -, L, 15; ni_nires_reg_data3neg_6_ = node, -, -, L, 0; clk = pin, 66, -, M, 10; TXD_9_ = pin, 64, -, M, 4; TXD_8_ = pin, 65, -, M, 12; TXD_7_ = pin, 67, -, M, 0; ix1641 = node, -, -, M, 11; ni_nires_reg_new_cnt_0_ = node, -, -, M, 13; ni_nires_reg_gray_cntf_0_ = node, -, -, M, 14; ni_nires_reg_gray_cntf_1_ = node, -, -, M, 1; ni_nires_reg_new_cnt_1_ = node, -, -, M, 15; ni_nires_reg_data3neg_1_ = node, -, -, M, 2; ni_nires_reg_data1neg_1_ = node, -, -, M, 3; ni_nires_reg_data0neg_1_ = node, -, -, M, 5; ni_nires_reg_data2neg_1_ = node, -, -, M, 6; ni_nires_reg_data3neg_9_ = node, -, -, M, 7; ni_nires_reg_data1neg_9_ = node, -, -, M, 8; ni_nires_reg_data0neg_9_ = node, -, -, M, 9; ni_nires_reg_data2neg_9_ = node, -, -, M, 10; TXD_4_ = pin, 71, -, N, 10; TXD_3_ = pin, 72, -, N, 12; TXD_6_ = pin, 69, -, N, 4; TXD_5_ = pin, 70, -, N, 6; ni_nires_reg_data3pos_6_ = node, -, -, N, 7; ni_nires_reg_data1pos_6_ = node, -, -, N, 11; ni_nires_reg_data0pos_6_ = node, -, -, N, 13; ni_nires_reg_data2pos_6_ = node, -, -, N, 14; ni_nires_reg_data3pos_7_ = node, -, -, N, 15; ni_nires_reg_data1pos_7_ = node, -, -, N, 0; ni_nires_reg_data0pos_7_ = node, -, -, N, 1; ni_nires_reg_data2pos_7_ = node, -, -, N, 2; j2c_reg_shreg_6_ = node, -, -, N, 5; ix1647 = node, -, -, N, 3; nx1967 = node, -, -, N, 9; nx2210 = node, -, -, N, 8; FAULT = pin, 81, -, O, 2; TXD_2_ = pin, 78, -, O, 1; TXD_1_ = pin, 79, -, O, 10; TXD_0_ = pin, 80, -, O, 9; j2c_reg_shreg_4_ = node, -, -, O, 6; ni_reg_prty_bit_pos_r = node, -, -, O, 4; j2c_reg_shreg_3_ = node, -, -, O, 7; nx1949 = node, -, -, O, 2; ni_nires_reg_data1neg_6_ = node, -, -, O, 8; ni_nires_reg_data0neg_6_ = node, -, -, O, 11; ni_nires_reg_data2neg_6_ = node, -, -, O, 12; ni_nires_reg_data3neg_7_ = node, -, -, O, 13; ni_nires_reg_data1neg_7_ = node, -, -, O, 14; ni_nires_reg_data0neg_7_ = node, -, -, O, 15; ni_nires_reg_data2neg_7_ = node, -, -, O, 3; jTMS = pin, 87, -, P, 2; EN = pin, 84, -, P, 0; WP_EEP = pin, 86, -, P, 6; ix1266 = node, -, -, P, 5; nx194 = node, -, -, P, 14; j2c_reg_shreg_7_ = node, -, -, P, 15; j2c_reg_creg1hm_6_ = node, -, -, P, 4; ix47 = node, -, -, P, 1; ix59 = node, -, -, P, 2; ix71 = node, -, -, P, 3; ni_nires_reg_data3neg_5_ = node, -, -, P, 10; ni_nires_reg_data1neg_5_ = node, -, -, P, 11; ni_nires_reg_data0neg_5_ = node, -, -, P, 12; ni_nires_reg_data2neg_5_ = node, -, -, P, 13; ix1084 = node, -, -, P, 7; ix1160 = node, -, -, P, 8; ix1164 = node, -, -, P, 9; jTCK = pin, 38, -, -, -; jTDI = pin, 88, -, -, -; [PTOE ASSIGNMENTS] [FAST BYPASS] Default = NONE; BYPASS = ; [ORP BYPASS] default = NONE; [INPUT REGISTERS] Default = NONE; [IO TYPES] NI_D_9_ = LVCMOS33, pin, -, -; NI_STR = LVCMOS33, pin, -, -; reset_n = LVCMOS33, pin, -, -; clk = LVCMOS33, pin, -, -; DIS_JTG = LVCMOS33, pin, -, -; FAULT = LVCMOS33, pin, -, -; jTCK = LVCMOS33, pin, -, -; jTDI = LVCMOS33, pin, -, -; jTMS = LVCMOS33, pin, -, -; NI_D_8_ = LVCMOS33, pin, -, -; NI_D_7_ = LVCMOS33, pin, -, -; NI_D_6_ = LVCMOS33, pin, -, -; NI_D_5_ = LVCMOS33, pin, -, -; NI_D_4_ = LVCMOS33, pin, -, -; NI_D_3_ = LVCMOS33, pin, -, -; NI_D_2_ = LVCMOS33, pin, -, -; NI_D_1_ = LVCMOS33, pin, -, -; NI_D_0_ = LVCMOS33, pin, -, -; TESTEN = LVCMOS33, pin, 1, -; PRBSEN = LVCMOS33, pin, 1, -; LCKREFN = LVCMOS33, pin, 1, -; ENABLE = LVCMOS33, pin, 1, -; LOOPEN = LVCMOS33, pin, 1, -; TX_ER = LVCMOS33, pin, 1, -; EN = LVCMOS33, pin, 1, -; SD2ANL = LVCMOS33, pin, 0, -; WP_EEP = LVCMOS33, pin, 1, -; SCL = LVCMOS33, pin, 0, -; SDA = LVCMOS33, pin, 0, -; jTDO = LVCMOS33, pin, 0, -; TXD_4_ = LVCMOS33, pin, 1, -; TXD_3_ = LVCMOS33, pin, 1, -; TXD_2_ = LVCMOS33, pin, 1, -; TXD_1_ = LVCMOS33, pin, 1, -; TXD_0_ = LVCMOS33, pin, 1, -; TX_EN = LVCMOS33, pin, 1, -; TXD_15_ = LVCMOS33, pin, 1, -; TXD_14_ = LVCMOS33, pin, 1, -; TXD_13_ = LVCMOS33, pin, 1, -; TXD_12_ = LVCMOS33, pin, 1, -; TXD_11_ = LVCMOS33, pin, 1, -; TXD_10_ = LVCMOS33, pin, 1, -; TXD_9_ = LVCMOS33, pin, 1, -; TXD_8_ = LVCMOS33, pin, 1, -; TXD_7_ = LVCMOS33, pin, 1, -; TXD_6_ = LVCMOS33, pin, 1, -; TXD_5_ = LVCMOS33, pin, 1, -; [PLL ASSIGNMENTS] [RESOURCE RESERVATIONS] layer = OFF; PIN = 5, Input; [SLEWRATE] SLOW = LOOPEN, PRBSEN, TESTEN, TX_ER, EN, ENABLE, LCKREFN, jTDO, SCL, SDA, SD2ANL, WP_EEP; Default = FAST; [PULLUP] Default = UP; [FITTER RESULTS] I/O_pin_util = 70; I/O_pin = 45; Logic_PT_util = 68; Logic_PT = 877; Occupied_MC_util = 99; Occupied_MC = 255; Occupied_PT_util = 85; Occupied_PT = 1129; GLB_input_util = 85; GLB_input = 495; [TIMING CONSTRAINTS] layer = OFF; fMAX_0 = 8.0000, clk, clk; fMAX_1 = 8.3333, NI_STR, NI_STR; fMAX_2 = 1000.0000, jTCK, jTCK; [FITTER REPORT FORMAT] Fitter_Options = Yes; Pinout_Diagram = No; Pinout_Listing = Yes; Detailed_Block_Segment_Summary = Yes; Input_Signal_List = Yes; Output_Signal_List = Yes; Bidir_Signal_List = Yes; Node_Signal_List = Yes; Signal_Fanout_List = Yes; Block_Segment_Fanin_List = Yes; Postfit_Eqn = Yes; Page_Break = Yes; Detailed = No; [POWER] Default = HIGH; [SOURCE_CONSTRAINT_OPTION] [HARDWARE DEVICE OPTIONS] Zero_Hold_Time = No; Signature_Word = ; Pullup = No; Slew_Rate = FAST; [TIMING ANALYZER] Last_source = ; Last_source_type = Fmax; [opt global constraints list] [Explorer User Settings] [LOCATION ASSIGNMENTS LIST] [GROUP ASSIGNMENTS] [RESOURCE RESERVATIONS LIST] [Pin attributes list] [individual constraints list] [Attributes list setting] [Source Constraint Option] [NETLIST/DELAY FORMAT] [OSM Bypass] [Register Powerup] [global constraints list] [Global Constraints Process Update] [Explorer Results] [VHDL synplify constraints] [VHDL spectrum constraints] [verilog synplify constraints] [verilog spectrum constraints] [VHDL synplify constraints list] [VHDL spectrum constraints list] [verilog synplify constraints list] [verilog spectrum constraints list] [Timing Results] Fmax = 69.44; Logic_level = 5;