TDA  - Timing Driven Analyze 
Ver. 1.0, supported by Lattice Semiconductor
ispLEVER 5.00 Copyright 1992-2005 Lattice Semiconductor. All Rights Reserved.
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Summary for Timing Constraints:

Goal: Clock Period on clock domain "clk" of 8.00ns (125.00MHz) is met.
      Worst case path:
      From  : reg_cdata_14_.C
      to    : reg_sm_0_.T
      Actual: 5.95ns (168.07MHz)
      Slack : 2.05ns

  Total constraints: 1, passed: 1, not passed: 0