ispLEVER 5.0.01.73.31.05_Starter Fitter Report File
Copyright(C), 1992-2005, Lattice Semiconductor Corporation
All Rights Reserved
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Project Name : oase Project Path : U:\REFERENCE\SIM\PROJECTS\ORI\lattice_tg Project Fitted on : Wed Sep 27 18:33:15 2006 Device : M4256_64 Package : 100 GLB Input Mux Size : 33 Available Blocks : 16 Speed : -3 Part Number : LC4256V-3T100C Source Format : EDIF Project 'oase' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.11 secs Partition Time 0.31 secs Place Time 0.01 secs Route Time 0.00 secs Total Fit Time 00:00:01 Design_Summary
Total Input Pins 20 Total Logic Functions 71 Total Output Pins 25 Total Bidir I/O Pins 3 Total Buried Nodes 43 Total Flip-Flops 56 Total D Flip-Flops 27 Total T Flip-Flops 29 Total Latches 0 Total Product Terms 398 Total Reserved Pins 17 Total Locked Pins 48 Total Locked Nodes 0 Total Unique Output Enables 1 Total Unique Clocks 1 Total Unique Clock Enables 1 Total Unique Resets 1 Total Unique Presets 0 Fmax Logic Levels 2 Device_Resource_Summary
Device Total Used Not Used Utilization ----------------------------------------------------------------------- Dedicated Pins Clock/Input Pins 4 3 1 --> 75 Input-Only Pins 6 0 6 --> 0 I/O / Enable Pins 2 1 1 --> 50 I/O Pins 62 44 18 --> 70 Logic Functions 256 71 185 --> 27 Input Registers 64 0 64 --> 0 GLB Inputs 576 279 297 --> 48 Logical Product Terms 1280 286 994 --> 22 Occupied GLBs 16 16 0 --> 100 Macrocells 256 71 185 --> 27 Product Terms 1316 238 1078 --> 18 Control Product Terms: GLB Clock/Clock Enables 16 16 0 --> 100 GLB Reset/Presets 16 0 16 --> 0 Macrocell Clocks 256 19 237 --> 7 Macrocell Clock Enables 256 8 248 --> 3 Macrocell Enables 256 0 256 --> 0 Macrocell Resets 256 0 256 --> 0 Macrocell Presets 256 0 256 --> 0 Global Routing Pool 324 58 266 --> 17 GRP from IFB .. 3 .. --> .. (from input signals) .. 3 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 0 .. --> .. GRP from MFB .. 55 .. --> .. ---------------------------------------------------------------------- <Note> 1 : The available PT is the product term that has not been used. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT --- Fanin --- I/O Input Macrocells Macrocells Logic clusters Unique Shared Total Pins Regs Used Inaccessible available PTs used ------------------------------------------------------------------------------------------- Maximum GLB 36 *(1) 8 -- -- 16 80 16 ------------------------------------------------------------------------------------------- GLB A 0 21 21 0/4 0 3 0 13 16 5 GLB B 0 21 21 4/4 0 4 0 12 18 6 GLB C 1 20 21 3/4 0 8 0 8 26 8 GLB D 0 11 11 4/4 0 6 0 10 16 6 ------------------------------------------------------------------------------------------- GLB E 11 14 25 4/4 0 3 0 13 17 5 GLB F 0 21 21 3/4 0 4 0 12 22 7 GLB G 2 21 23 0/4 0 3 0 13 16 5 GLB H 0 21 21 0/4 0 2 0 14 14 4 ------------------------------------------------------------------------------------------- GLB I 2 13 15 1/4 0 5 0 11 17 5 GLB J 3 12 15 4/4 0 9 0 7 18 9 GLB K 2 21 23 4/4 0 8 0 8 22 10 GLB L 1 17 18 4/4 0 4 0 12 16 6 ------------------------------------------------------------------------------------------- GLB M 1 15 16 4/4 0 3 0 13 20 6 GLB N 1 12 13 4/4 0 4 0 12 30 8 GLB O 1 8 9 4/4 0 3 0 13 15 5 GLB P 6 0 6 1/4 0 2 0 14 3 2 ------------------------------------------------------------------------------------------- TOTALS: 31 248 279 44/64 0 71 0 185 286 97 <Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Rst/Pr | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 16 16 16 16 16 ============================================================================== GLB A 1 0 2 0 0 0 0 GLB B 1 0 2 0 0 0 0 GLB C 1 0 0 0 0 0 0 GLB D 1 0 0 0 0 0 0 ------------------------------------------------------------------------------ GLB E 1 0 0 2 0 0 0 GLB F 1 0 3 0 0 0 0 GLB G 1 0 0 2 0 0 0 GLB H 1 0 2 0 0 0 0 ------------------------------------------------------------------------------ GLB I 1 0 0 0 0 0 0 GLB J 1 0 0 0 0 0 0 GLB K 1 0 0 2 0 0 0 GLB L 1 0 0 2 0 0 0 ------------------------------------------------------------------------------ GLB M 1 0 3 0 0 0 0 GLB N 1 0 4 0 0 0 0 GLB O 1 0 3 0 0 0 0 GLB P 1 0 0 0 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : Yes @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : Yes Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : Yes Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : FMAX Fmax_Logic_Level : 1 D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 80 Max Symbols : 24 @Utilization_options Max. % of Macrocells used : 100 @Usercode (HEX) @IO_Types Default = LVCMOS18 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_UP (2) @Fast_Bypass Default = None (2) @ORP_Bypass Default = None @Input_Registers Default = None (2) @Register_Powerup Default = None Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal| Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name ------------------------------------------------------------------------------ 1 | GND | - | | | | | 2 | TDI | - | | | | | 3 | I_O | 0 |C12 | * |LVCMOS33 | Output|SD2ANL 4 | I_O | 0 |C10 | | | | 5 | I_O | 0 |C6 | * |LVCMOS18 | Input |Reserved_Pin_83 6 | I_O | 0 |C2 | * |LVCMOS18 | Input |Reserved_Pin_87 7 |GNDIO0 | - | | | | | 8 | I_O | 0 |D12 | * |LVCMOS18 | Input |Reserved_Pin_88 9 | I_O | 0 |D10 | * |LVCMOS18 | Input |Reserved_Pin_89 10 | I_O | 0 |D6 | * |LVCMOS18 | Input |Reserved_Pin_90 11 | I_O | 0 |D4 | * |LVCMOS18 | Input |Reserved_Pin_91 12 | IN0 | 0 | | | | | 13 |VCCIO0 | - | | | | | 14 | I_O | 0 |E4 | * |LVCMOS18 | Input |Reserved_Pin_92 15 | I_O | 0 |E6 | * |LVCMOS18 | Input |Reserved_Pin_93 16 | I_O | 0 |E10 | * |LVCMOS18 | Input |Reserved_Pin_94 17 | I_O | 0 |E12 | * |LVCMOS18 | Input |Reserved_Pin_95 18 |GNDIO0 | - | | | | | 19 | I_O | 0 |F2 | * |LVCMOS18 | Input |Reserved_Pin_96 20 | I_O | 0 |F6 | * |LVCMOS18 | Input |Reserved_Pin_97 21 | I_O | 0 |F10 | * |LVCMOS33 |Tri-Out|jTDO 22 | I_O | 0 |F12 | | | | 23 | IN1 | 0 | | | | | 24 | TCK | - | | | | | 25 | VCC | - | | | | | 26 | GND | - | | | | | 27 | IN2 | 0 | | | | | 28 | I_O | 0 |G12 | | | | 29 | I_O | 0 |G10 | | | | 30 | I_O | 0 |G6 | | | | 31 | I_O | 0 |G2 | | | | 32 |GNDIO0 | - | | | | | 33 |VCCIO0 | - | | | | | 34 | I_O | 0 |H12 | | | | 35 | I_O | 0 |H10 | | | | 36 | I_O | 0 |H6 | | | | 37 | I_O | 0 |H2 | | | | 38 |INCLK1 | 0 | | * |LVCMOS18 | Input |Reserved_Pin_98 39 |INCLK2 | 1 | | | | | 40 | VCC | - | | | | | 41 | I_O | 1 |I2 | | | | 42 | I_O | 1 |I6 | | | | 43 | I_O | 1 |I10 | | | | 44 | I_O | 1 |I12 | * |LVCMOS33 | Output|TESTEN 45 |VCCIO1 | - | | | | | 46 |GNDIO1 | - | | | | | 47 | I_O | 1 |J2 | * |LVCMOS33 | Output|PRBSEN 48 | I_O | 1 |J6 | * |LVCMOS33 | Output|LCKREFN 49 | I_O | 1 |J10 | * |LVCMOS33 | Output|ENABLE 50 | I_O | 1 |J12 | * |LVCMOS33 | Output|TX_ER 51 | GND | - | | | | | 52 | TMS | - | | | | | 53 | I_O | 1 |K12 | * |LVCMOS33 | Output|LOOPEN 54 | I_O | 1 |K10 | * |LVCMOS33 | Output|TX_EN 55 | I_O | 1 |K6 | * |LVCMOS33 | Output|TXD_15_ 56 | I_O | 1 |K2 | * |LVCMOS33 | Output|TXD_14_ 57 |GNDIO1 | - | | | | | 58 | I_O | 1 |L12 | * |LVCMOS33 | Output|TXD_13_ 59 | I_O | 1 |L10 | * |LVCMOS33 | Output|TXD_12_ 60 | I_O | 1 |L6 | * |LVCMOS33 | Output|TXD_11_ 61 | I_O | 1 |L4 | * |LVCMOS33 | Output|TXD_10_ 62 | IN3 | 1 | | | | | 63 |VCCIO1 | - | | | | | 64 | I_O | 1 |M4 | * |LVCMOS33 | Output|TXD_9_ 65 | I_O | 1 |M6 | * |LVCMOS33 | Output|TXD_8_ 66 | I_O | 1 |M10 | * |LVCMOS33 | Input |clk 67 | I_O | 1 |M12 | * |LVCMOS33 | Output|TXD_7_ 68 |GNDIO1 | - | | | | | 69 | I_O | 1 |N2 | * |LVCMOS33 | Output|TXD_6_ 70 | I_O | 1 |N6 | * |LVCMOS33 | Output|TXD_5_ 71 | I_O | 1 |N10 | * |LVCMOS33 | Output|TXD_4_ 72 | I_O | 1 |N12 | * |LVCMOS33 | Output|TXD_3_ 73 | IN4 | 1 | | | | | 74 | TDO | - | | | | | 75 | VCC | - | | | | | 76 | GND | - | | | | | 77 | IN5 | 1 | | | | | 78 | I_O | 1 |O12 | * |LVCMOS33 | Output|TXD_2_ 79 | I_O | 1 |O10 | * |LVCMOS33 | Output|TXD_1_ 80 | I_O | 1 |O6 | * |LVCMOS33 | Output|TXD_0_ 81 | I_O | 1 |O2 | * |LVCMOS18 | Input |Reserved_Pin_84 82 |GNDIO1 | - | | | | | 83 |VCCIO1 | - | | | | | 84 | I_O | 1 |P12 | * |LVCMOS33 | Output|EN 85 | I_O | 1 |P10 | | | | 86 | I_O | 1 |P6 | | | | 87 | I_O/OE| 1 |P2 | * |LVCMOS18 | Input |Reserved_Pin_85 88 |INCLK3 | 1 | | * |LVCMOS18 | Input |Reserved_Pin_86 89 |INCLK0 | 0 | | * |LVCMOS33 | Input |start 90 | VCC | - | | | | | 91 | I_O/OE| 0 |A2 | | | | 92 | I_O | 0 |A6 | | | | 93 | I_O | 0 |A10 | | | | 94 | I_O | 0 |A12 | | | | 95 |VCCIO0 | - | | | | | 96 |GNDIO0 | - | | | | | 97 | I_O | 0 |B2 | * |LVCMOS33 |Tri-Out|SDA 98 | I_O | 0 |B6 | * |LVCMOS33 |Tri-Out|SCL 99 | I_O | 0 |B10 | * |LVCMOS18 | Input |Reserved_Pin_99 100 | I_O | 0 |B12 | * |LVCMOS33 | Input |reset_n ------------------------------------------------------------------------------ <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal --------------------------------------------------------- 5 C I/O ---------------- Up Reserved_Pin_83 81 O I/O ---------------- Up Reserved_Pin_84 87 P I/O ---------------- Up Reserved_Pin_85 88 -- INCLK ---------------- Up Reserved_Pin_86 6 C I/O ---------------- Up Reserved_Pin_87 8 D I/O ---------------- Up Reserved_Pin_88 9 D I/O ---------------- Up Reserved_Pin_89 10 D I/O ---------------- Up Reserved_Pin_90 11 D I/O ---------------- Up Reserved_Pin_91 14 E I/O ---------------- Up Reserved_Pin_92 15 E I/O ---------------- Up Reserved_Pin_93 16 E I/O ---------------- Up Reserved_Pin_94 17 E I/O ---------------- Up Reserved_Pin_95 19 F I/O ---------------- Up Reserved_Pin_96 20 F I/O ---------------- Up Reserved_Pin_97 38 -- INCLK ---------------- Up Reserved_Pin_98 99 B I/O ---------------- Up Reserved_Pin_99 66 M I/O 16 ABCDEFGHIJKLMNOP Up clk 100 B I/O 16 ABCDEFGHIJKLMNOP Up reset_n 89 -- INCLK 1 ---------J------ Up start --------------------------------------------------------- Output_Signal_List
I C P R P O Output N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal -------------------------------------------------------------------------------- 84 P 0 - 1 1 COM ---------------- Slow Up EN 49 J 0 - 1 1 COM ---------------- Slow Up ENABLE 48 J 0 - 0 1 COM ---------------- Slow Up LCKREFN 53 K 0 - 0 1 COM ---------------- Slow Up LOOPEN 47 J 0 - 0 1 COM ---------------- Slow Up PRBSEN 98 B 0 - 0 1 COM * ---------------- Slow Up SCL 3 C 0 - 1 1 COM ---------------- Slow Up SD2ANL 97 B 0 - 0 1 COM * ---------------- Slow Up SDA 44 I 0 - 0 1 COM ---------------- Slow Up TESTEN 80 O 7 1 3 1 DFF * R * 4 -----------LMNO- Fast Up TXD_0_ 61 L 17 1 6 2 TFF * R * 1 -----------L---- Fast Up TXD_10_ 60 L 18 1 7 2 TFF * R * 1 -----------L---- Fast Up TXD_11_ 59 L 5 1 2 1 DFF * R ---------------- Fast Up TXD_12_ 58 L 4 1 1 1 DFF * R ---------------- Fast Up TXD_13_ 56 K 0 - 0 1 COM ---------------- Fast Up TXD_14_ 55 K 4 1 1 1 DFF * R ---------------- Fast Up TXD_15_ 79 O 8 1 6 2 DFF * R * 4 -----------LMNO- Fast Up TXD_1_ 78 O 9 1 6 2 TFF * R * 4 -----------LMNO- Fast Up TXD_2_ 72 N 10 1 8 2 DFF * R * 3 -----------LMN-- Fast Up TXD_3_ 71 N 11 1 6 2 TFF * R * 3 -----------LMN-- Fast Up TXD_4_ 70 N 12 1 10 2 DFF * R * 3 -----------LMN-- Fast Up TXD_5_ 69 N 13 1 6 2 TFF * R * 3 -----------LMN-- Fast Up TXD_6_ 67 M 14 1 7 2 TFF * R * 2 -----------LM--- Fast Up TXD_7_ 65 M 15 1 6 2 TFF * R * 2 -----------LM--- Fast Up TXD_8_ 64 M 16 1 7 2 TFF * R * 2 -----------LM--- Fast Up TXD_9_ 54 K 21 1 5 1 DFF * R ---------------- Fast Up TX_EN 50 J 0 - 0 1 COM ---------------- Slow Up TX_ER 21 F 0 - 0 1 COM * ---------------- Slow Up jTDO -------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Bidir_Signal_List
I C P R P O Bidir N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Buried_Signal_List
I C P R P Node N L Mc R E U C I F Fanout Mc GLB P LL PTs S Type E S P E R P Signal ---------------------------------------------------------------------- 12 C 15 - 1 1 COM 2 ----E-G--------- nx1854 12 K 15 - 1 1 COM 1 ----E----------- nx1934 10 A 15 - 1 1 COM 2 --C-E----------- nx1988 9 F 21 1 6 2 DFF * R * 7 AB--EFGH--K----- reg_cdata_0_ 2 G 21 1 7 2 TFF * R * 7 AB--EFGH--K----- reg_cdata_10_ 9 B 21 1 7 2 TFF * R * 7 AB--EFGH--K----- reg_cdata_11_ 3 K 19 1 6 2 TFF * R * 7 AB--EFGH--K----- reg_cdata_12_ 5 A 21 1 7 2 TFF * R * 7 AB--EFGH--K----- reg_cdata_13_ 3 H 21 1 7 2 TFF * R * 7 AB--EFGH--K----- reg_cdata_14_ 10 E 8 1 5 1 DFF * R * 7 AB--EFGH--K----- reg_cdata_1_ 6 F 9 1 6 2 DFF * R * 7 AB--EFGH--K----- reg_cdata_2_ 2 A 21 1 8 2 DFF * R * 7 AB--EFGH--K----- reg_cdata_3_ 5 G 11 1 6 2 TFF * R * 7 AB--EFGH--K----- reg_cdata_4_ 3 F 21 1 10 2 DFF * R * 7 AB--EFGH--K----- reg_cdata_5_ 1 B 21 1 11 3 DFF * R * 7 AB--EFGH--K----- reg_cdata_6_ 2 E 14 1 6 2 TFF * R * 7 AB--EFGH--K----- reg_cdata_7_ 7 H 21 1 7 2 TFF * R * 7 AB--EFGH--K----- reg_cdata_8_ 5 K 16 1 6 2 TFF * R * 7 AB--EFGH--K----- reg_cdata_9_ 9 D 7 1 1 1 DFF * R 12 AB-DEFGH--KLMNO- reg_dis_next 12 D 7 1 1 1 DFF * R 1 ---D------------ reg_i_data_0_ 7 D 8 1 2 1 DFF * R 1 ---D------------ reg_i_data_1_ 5 D 9 1 3 1 DFF * R 1 ---D------------ reg_i_data_2_ 3 D 10 1 4 1 DFF * R 1 ---D------------ reg_i_data_3_ 1 D 11 1 5 1 DFF * R 1 ---D------------ reg_i_data_4_ 5 E 25 2 6 2 TFF * R 16 ABCDEFGHIJKLMNOP reg_sm_0_ 1 C 21 2 4 1 DFF * R 16 ABCDEFGHIJKLMNOP reg_sm_1_ 10 G 22 2 3 1 DFF * R 16 ABCDEFGHIJKLMNOP reg_sm_2_ 12 J 3 - 1 1 DFF * R 2 ----E-G--------- reg_start_s 9 P 6 1 2 1 DFF * R 5 --C-----IJK----P timer_0_ 9 C 16 1 4 1 TFF * R 1 --C------------- timer_10_ 7 C 17 1 4 1 TFF * R 1 --C------------- timer_11_ 5 C 18 1 4 1 TFF * R 1 --C------------- timer_12_ 3 C 19 1 4 1 TFF * R 1 --C------------- timer_13_ 2 C 20 1 4 1 TFF * R 1 --C------------- timer_14_ 9 K 7 1 3 1 DFF * R 4 --C-----IJK----- timer_1_ 9 J 8 1 4 1 DFF * R 3 --C-----IJ------ timer_2_ 3 I 9 1 5 1 DFF * R 3 --C-----IJ------ timer_3_ 5 J 10 1 4 1 TFF * R 3 --C-----IJ------ timer_4_ 11 I 11 1 4 1 TFF * R 3 --C-----IJ------ timer_5_ 4 J 12 1 4 1 TFF * R 3 --C-----IJ------ timer_6_ 7 I 13 1 4 1 TFF * R 3 --C-----IJ------ timer_7_ 3 J 14 1 4 1 TFF * R 3 --C-----IJ------ timer_8_ 5 I 15 1 4 1 TFF * R 2 --C-----I------- timer_9_ ---------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used OBP = ORP bypass used PostFit_Equations
EN = 1 ; (1 pterm, 0 signal) ENABLE = 1 ; (1 pterm, 0 signal) LCKREFN = 0 ; (0 pterm, 0 signal) LOOPEN = 0 ; (0 pterm, 0 signal) PRBSEN = 0 ; (0 pterm, 0 signal) SCL = 0 ; (0 pterm, 0 signal) SCL.OE = 0 ; (0 pterm, 0 signal) SD2ANL = 1 ; (1 pterm, 0 signal) SDA = 0 ; (0 pterm, 0 signal) SDA.OE = 0 ; (0 pterm, 0 signal) TESTEN = 0 ; (0 pterm, 0 signal) TXD_0_.D = !TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # !TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q ; (2 pterms, 4 signals) TXD_0_.C = clk ; (1 pterm, 1 signal) TXD_0_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_0_.AR = !reset_n ; (1 pterm, 1 signal) TXD_10_.T = TXD_9_.Q & TXD_8_.Q & TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_9_.Q & TXD_8_.Q & TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_10_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # TXD_10_.Q & reg_sm_1_.Q # TXD_10_.Q & reg_sm_2_.Q & reg_sm_0_.Q ; (5 pterms, 14 signals) TXD_10_.C = clk ; (1 pterm, 1 signal) TXD_10_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_10_.AR = !reset_n ; (1 pterm, 1 signal) TXD_11_.T = TXD_10_.Q & TXD_9_.Q & TXD_8_.Q & TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_10_.Q & TXD_9_.Q & TXD_8_.Q & TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # !TXD_11_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # !TXD_11_.Q & reg_sm_1_.Q & !reg_sm_0_.Q # TXD_11_.Q & reg_sm_2_.Q & reg_sm_0_.Q # TXD_11_.Q & reg_sm_1_.Q & reg_sm_0_.Q ; (6 pterms, 15 signals) TXD_11_.C = clk ; (1 pterm, 1 signal) TXD_11_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_11_.AR = !reset_n ; (1 pterm, 1 signal) TXD_12_.D = !( !reg_sm_1_.Q & reg_sm_2_.Q & reg_sm_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q ) ; (2 pterms, 3 signals) TXD_12_.C = clk ; (1 pterm, 1 signal) TXD_12_.AR = !reset_n ; (1 pterm, 1 signal) TXD_13_.D = reg_sm_1_.Q & !reg_sm_0_.Q ; (1 pterm, 2 signals) TXD_13_.C = clk ; (1 pterm, 1 signal) TXD_13_.AR = !reset_n ; (1 pterm, 1 signal) TXD_14_ = 0 ; (0 pterm, 0 signal) TXD_15_.D = reg_sm_1_.Q & !reg_sm_0_.Q ; (1 pterm, 2 signals) TXD_15_.C = clk ; (1 pterm, 1 signal) TXD_15_.AR = !reset_n ; (1 pterm, 1 signal) TXD_1_.D = TXD_1_.Q & !TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # !TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_1_.Q & !TXD_0_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # !TXD_1_.Q & TXD_0_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q ; (5 pterms, 5 signals) TXD_1_.C = clk ; (1 pterm, 1 signal) TXD_1_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_1_.AR = !reset_n ; (1 pterm, 1 signal) TXD_2_.T = TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_2_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # TXD_2_.Q & reg_sm_1_.Q # TXD_2_.Q & reg_sm_2_.Q & reg_sm_0_.Q ; (5 pterms, 6 signals) TXD_2_.C = clk ; (1 pterm, 1 signal) TXD_2_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_2_.AR = !reset_n ; (1 pterm, 1 signal) TXD_3_.D = !( TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q # !TXD_3_.Q & !TXD_0_.Q & !reg_sm_1_.Q # !TXD_3_.Q & !TXD_1_.Q & !reg_sm_1_.Q # !TXD_3_.Q & !TXD_2_.Q & !reg_sm_1_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_2_.Q & reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q ) ; (7 pterms, 7 signals) TXD_3_.C = clk ; (1 pterm, 1 signal) TXD_3_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_3_.AR = !reset_n ; (1 pterm, 1 signal) TXD_4_.T = TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_4_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # TXD_4_.Q & reg_sm_1_.Q # TXD_4_.Q & reg_sm_2_.Q & reg_sm_0_.Q ; (5 pterms, 8 signals) TXD_4_.C = clk ; (1 pterm, 1 signal) TXD_4_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_4_.AR = !reset_n ; (1 pterm, 1 signal) TXD_5_.D = !( TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q # !TXD_5_.Q & !TXD_0_.Q & !reg_sm_1_.Q # !TXD_5_.Q & !TXD_1_.Q & !reg_sm_1_.Q # !TXD_5_.Q & !TXD_2_.Q & !reg_sm_1_.Q # !TXD_5_.Q & !TXD_3_.Q & !reg_sm_1_.Q # !TXD_5_.Q & !TXD_4_.Q & !reg_sm_1_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_2_.Q & reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q ) ; (9 pterms, 9 signals) TXD_5_.C = clk ; (1 pterm, 1 signal) TXD_5_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_5_.AR = !reset_n ; (1 pterm, 1 signal) TXD_6_.T = TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_6_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # TXD_6_.Q & reg_sm_1_.Q # TXD_6_.Q & reg_sm_2_.Q & reg_sm_0_.Q ; (5 pterms, 10 signals) TXD_6_.C = clk ; (1 pterm, 1 signal) TXD_6_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_6_.AR = !reset_n ; (1 pterm, 1 signal) TXD_7_.T = TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_7_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # !TXD_7_.Q & reg_sm_1_.Q & !reg_sm_0_.Q # TXD_7_.Q & reg_sm_2_.Q & reg_sm_0_.Q # TXD_7_.Q & reg_sm_1_.Q & reg_sm_0_.Q ; (6 pterms, 11 signals) TXD_7_.C = clk ; (1 pterm, 1 signal) TXD_7_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_7_.AR = !reset_n ; (1 pterm, 1 signal) TXD_8_.T = TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_8_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # TXD_8_.Q & reg_sm_1_.Q # TXD_8_.Q & reg_sm_2_.Q & reg_sm_0_.Q ; (5 pterms, 12 signals) TXD_8_.C = clk ; (1 pterm, 1 signal) TXD_8_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_8_.AR = !reset_n ; (1 pterm, 1 signal) TXD_9_.T = TXD_8_.Q & TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_8_.Q & TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # !TXD_9_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # !TXD_9_.Q & reg_sm_1_.Q & !reg_sm_0_.Q # TXD_9_.Q & reg_sm_2_.Q & reg_sm_0_.Q # TXD_9_.Q & reg_sm_1_.Q & reg_sm_0_.Q ; (6 pterms, 13 signals) TXD_9_.C = clk ; (1 pterm, 1 signal) TXD_9_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_9_.AR = !reset_n ; (1 pterm, 1 signal) TX_EN.D = !( !reg_cdata_14_.Q & !reg_sm_2_.Q & reg_sm_0_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # !reg_sm_1_.Q & !reg_sm_0_.Q & reg_dis_next.Q # reg_sm_1_.Q & reg_sm_0_.Q ) ; (5 pterms, 19 signals) TX_EN.C = clk ; (1 pterm, 1 signal) TX_EN.AR = !reset_n ; (1 pterm, 1 signal) TX_ER = 0 ; (0 pterm, 0 signal) jTDO = 0 ; (0 pterm, 0 signal) jTDO.OE = 0 ; (0 pterm, 0 signal) nx1854 = !timer_14_.Q & !timer_13_.Q & !timer_12_.Q & !timer_11_.Q & !timer_10_.Q & !timer_9_.Q & timer_8_.Q & !timer_7_.Q & !timer_6_.Q & !timer_5_.Q & !timer_4_.Q & !timer_3_.Q & !timer_2_.Q & timer_1_.Q & !timer_0_.Q ; (1 pterm, 15 signals) nx1934 = reg_cdata_14_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q ; (1 pterm, 15 signals) nx1988 = !reg_cdata_14_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q ; (1 pterm, 15 signals) reg_cdata_0_.D = !( !reg_cdata_14_.Q & !reg_sm_2_.Q & reg_sm_0_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q # reg_cdata_0_.Q ) ; (5 pterms, 18 signals) reg_cdata_0_.C = clk ; (1 pterm, 1 signal) reg_cdata_0_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_0_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_10_.T = reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_10_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_10_.Q ; (6 pterms, 18 signals) reg_cdata_10_.C = clk ; (1 pterm, 1 signal) reg_cdata_10_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_10_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_11_.T = reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_11_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_11_.Q ; (6 pterms, 18 signals) reg_cdata_11_.C = clk ; (1 pterm, 1 signal) reg_cdata_11_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_11_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_12_.T = !reg_sm_1_.Q & reg_sm_2_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_12_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_12_.Q ; (5 pterms, 16 signals) reg_cdata_12_.C = clk ; (1 pterm, 1 signal) reg_cdata_12_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_12_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_13_.T = reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_13_.Q ; (6 pterms, 18 signals) reg_cdata_13_.C = clk ; (1 pterm, 1 signal) reg_cdata_13_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_13_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_14_.T = reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_13_.Q & reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_cdata_14_.Q & reg_sm_0_.Q ; (6 pterms, 18 signals) reg_cdata_14_.C = clk ; (1 pterm, 1 signal) reg_cdata_14_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_14_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_1_.D = !( !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q # !reg_cdata_1_.Q & !reg_cdata_0_.Q # reg_cdata_1_.Q & reg_cdata_0_.Q ) ; (4 pterms, 5 signals) reg_cdata_1_.C = clk ; (1 pterm, 1 signal) reg_cdata_1_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_1_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_2_.D = !( !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q # !reg_cdata_2_.Q & !reg_cdata_1_.Q # !reg_cdata_2_.Q & !reg_cdata_0_.Q ) ; (5 pterms, 6 signals) reg_cdata_2_.C = clk ; (1 pterm, 1 signal) reg_cdata_2_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_2_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_3_.D = !( !reg_cdata_14_.Q & !reg_sm_2_.Q & reg_sm_0_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q # !reg_cdata_3_.Q & !reg_cdata_1_.Q # !reg_cdata_3_.Q & !reg_cdata_2_.Q # !reg_cdata_3_.Q & !reg_cdata_0_.Q ) ; (7 pterms, 18 signals) reg_cdata_3_.C = clk ; (1 pterm, 1 signal) reg_cdata_3_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_3_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_4_.T = !reg_sm_1_.Q & reg_sm_2_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_4_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_4_.Q ; (5 pterms, 8 signals) reg_cdata_4_.C = clk ; (1 pterm, 1 signal) reg_cdata_4_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_4_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_5_.D = !( !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q # !reg_cdata_5_.Q & !reg_cdata_1_.Q # !reg_cdata_5_.Q & !reg_cdata_2_.Q # !reg_cdata_5_.Q & !reg_cdata_3_.Q # !reg_cdata_5_.Q & !reg_cdata_4_.Q # !reg_cdata_5_.Q & !reg_cdata_0_.Q ) ; (9 pterms, 18 signals) reg_cdata_5_.C = clk ; (1 pterm, 1 signal) reg_cdata_5_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_5_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_6_.D = !( !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q # !reg_cdata_6_.Q & !reg_cdata_5_.Q # !reg_cdata_6_.Q & !reg_cdata_1_.Q # !reg_cdata_6_.Q & !reg_cdata_2_.Q # !reg_cdata_6_.Q & !reg_cdata_3_.Q # !reg_cdata_6_.Q & !reg_cdata_4_.Q # !reg_cdata_6_.Q & !reg_cdata_0_.Q ) ; (10 pterms, 18 signals) reg_cdata_6_.C = clk ; (1 pterm, 1 signal) reg_cdata_6_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_6_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_7_.T = !reg_sm_1_.Q & reg_sm_2_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_7_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_7_.Q ; (5 pterms, 11 signals) reg_cdata_7_.C = clk ; (1 pterm, 1 signal) reg_cdata_7_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_7_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_8_.T = reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_8_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_8_.Q ; (6 pterms, 18 signals) reg_cdata_8_.C = clk ; (1 pterm, 1 signal) reg_cdata_8_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_8_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_9_.T = reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_9_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_9_.Q ; (5 pterms, 13 signals) reg_cdata_9_.C = clk ; (1 pterm, 1 signal) reg_cdata_9_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_9_.AR = !reset_n ; (1 pterm, 1 signal) reg_dis_next.D = !reg_i_data_4_.Q & !reg_i_data_3_.Q & !reg_i_data_2_.Q & !reg_i_data_1_.Q & !reg_i_data_0_.Q ; (1 pterm, 5 signals) reg_dis_next.C = clk ; (1 pterm, 1 signal) reg_dis_next.AR = !reset_n ; (1 pterm, 1 signal) reg_i_data_0_.D = !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_0_.Q ; (1 pterm, 5 signals) reg_i_data_0_.C = clk ; (1 pterm, 1 signal) reg_i_data_0_.AR = !reset_n ; (1 pterm, 1 signal) reg_i_data_1_.D = !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_1_.Q & !reg_i_data_0_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & reg_i_data_1_.Q & reg_i_data_0_.Q ; (2 pterms, 6 signals) reg_i_data_1_.C = clk ; (1 pterm, 1 signal) reg_i_data_1_.AR = !reset_n ; (1 pterm, 1 signal) reg_i_data_2_.D = !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_2_.Q & !reg_i_data_1_.Q & !reg_i_data_0_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & reg_i_data_2_.Q & reg_i_data_1_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & reg_i_data_2_.Q & reg_i_data_0_.Q ; (3 pterms, 7 signals) reg_i_data_2_.C = clk ; (1 pterm, 1 signal) reg_i_data_2_.AR = !reset_n ; (1 pterm, 1 signal) reg_i_data_3_.D = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & reg_i_data_3_.Q & !reg_i_data_2_.Q & !reg_i_data_1_.Q & !reg_i_data_0_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_3_.Q & reg_i_data_1_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_3_.Q & reg_i_data_2_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_3_.Q & reg_i_data_0_.Q ) ; (4 pterms, 8 signals) reg_i_data_3_.C = clk ; (1 pterm, 1 signal) reg_i_data_3_.AR = !reset_n ; (1 pterm, 1 signal) reg_i_data_4_.D = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & reg_i_data_4_.Q & !reg_i_data_3_.Q & !reg_i_data_2_.Q & !reg_i_data_1_.Q & !reg_i_data_0_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_4_.Q & reg_i_data_1_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_4_.Q & reg_i_data_2_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_4_.Q & reg_i_data_3_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_4_.Q & reg_i_data_0_.Q ) ; (5 pterms, 9 signals) reg_i_data_4_.C = clk ; (1 pterm, 1 signal) reg_i_data_4_.AR = !reset_n ; (1 pterm, 1 signal) reg_sm_0_.T = !reg_sm_1_.Q & !reg_cdata_14_.Q & reg_sm_2_.Q & reg_sm_0_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_cdata_14_.Q & !reg_sm_0_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & nx1934 # !reg_sm_1_.Q & !reg_sm_2_.Q & reg_start_s.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q & nx1854 # !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q & nx1988 ; (6 pterms, 23 signals) reg_sm_0_.C = clk ; (1 pterm, 1 signal) reg_sm_0_.AR = !reset_n ; (1 pterm, 1 signal) reg_sm_1_.D = !( reg_sm_1_.Q & reg_sm_0_.Q & !timer_14_.Q & !timer_13_.Q & !timer_12_.Q & !timer_11_.Q & !timer_10_.Q & !timer_9_.Q & timer_8_.Q & !timer_7_.Q & !timer_6_.Q & !timer_5_.Q & !timer_4_.Q & !timer_3_.Q & !timer_2_.Q & timer_1_.Q & !timer_0_.Q # !reg_sm_1_.Q & !reg_sm_0_.Q # !reg_sm_1_.Q & reg_sm_2_.Q # !reg_sm_1_.Q & !nx1988 ) ; (4 pterms, 19 signals) reg_sm_1_.C = clk ; (1 pterm, 1 signal) reg_sm_1_.AR = !reset_n ; (1 pterm, 1 signal) reg_sm_2_.D.X1 = !reg_sm_1_.Q & reg_sm_2_.Q # reg_sm_1_.Q & reg_start_s.Q & reg_sm_0_.Q & nx1854 ; (2 pterms, 5 signals) reg_sm_2_.D.X2 = !reg_sm_1_.Q & !reg_cdata_14_.Q & reg_sm_2_.Q & reg_sm_0_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q ; (1 pterm, 18 signals) reg_sm_2_.C = clk ; (1 pterm, 1 signal) reg_sm_2_.AR = !reset_n ; (1 pterm, 1 signal) reg_start_s.D = start ; (1 pterm, 1 signal) reg_start_s.C = clk ; (1 pterm, 1 signal) reg_start_s.AR = !reset_n ; (1 pterm, 1 signal) timer_0_.D = !( !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # timer_0_.Q ) ; (2 pterms, 4 signals) timer_0_.C = clk ; (1 pterm, 1 signal) timer_0_.AR = !reset_n ; (1 pterm, 1 signal) timer_10_.T = reg_sm_0_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_10_.Q ; (4 pterms, 14 signals) timer_10_.C = clk ; (1 pterm, 1 signal) timer_10_.AR = !reset_n ; (1 pterm, 1 signal) timer_11_.T = reg_sm_0_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_11_.Q ; (4 pterms, 15 signals) timer_11_.C = clk ; (1 pterm, 1 signal) timer_11_.AR = !reset_n ; (1 pterm, 1 signal) timer_12_.T = reg_sm_0_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_12_.Q ; (4 pterms, 16 signals) timer_12_.C = clk ; (1 pterm, 1 signal) timer_12_.AR = !reset_n ; (1 pterm, 1 signal) timer_13_.T = reg_sm_0_.Q & timer_12_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_12_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_12_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_13_.Q ; (4 pterms, 17 signals) timer_13_.C = clk ; (1 pterm, 1 signal) timer_13_.AR = !reset_n ; (1 pterm, 1 signal) timer_14_.T = reg_sm_0_.Q & timer_13_.Q & timer_12_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_13_.Q & timer_12_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_13_.Q & timer_12_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_14_.Q ; (4 pterms, 18 signals) timer_14_.C = clk ; (1 pterm, 1 signal) timer_14_.AR = !reset_n ; (1 pterm, 1 signal) timer_1_.D = !( !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # !timer_1_.Q & !timer_0_.Q # timer_1_.Q & timer_0_.Q ) ; (3 pterms, 5 signals) timer_1_.C = clk ; (1 pterm, 1 signal) timer_1_.AR = !reset_n ; (1 pterm, 1 signal) timer_2_.D = !( !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # timer_2_.Q & timer_1_.Q & timer_0_.Q # !timer_2_.Q & !timer_1_.Q # !timer_2_.Q & !timer_0_.Q ) ; (4 pterms, 6 signals) timer_2_.C = clk ; (1 pterm, 1 signal) timer_2_.AR = !reset_n ; (1 pterm, 1 signal) timer_3_.D = !( timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # !timer_3_.Q & !timer_1_.Q # !timer_3_.Q & !timer_2_.Q # !timer_3_.Q & !timer_0_.Q ) ; (5 pterms, 7 signals) timer_3_.C = clk ; (1 pterm, 1 signal) timer_3_.AR = !reset_n ; (1 pterm, 1 signal) timer_4_.T = !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_4_.Q # reg_sm_0_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q ; (4 pterms, 8 signals) timer_4_.C = clk ; (1 pterm, 1 signal) timer_4_.AR = !reset_n ; (1 pterm, 1 signal) timer_5_.T = !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_5_.Q # reg_sm_0_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q ; (4 pterms, 9 signals) timer_5_.C = clk ; (1 pterm, 1 signal) timer_5_.AR = !reset_n ; (1 pterm, 1 signal) timer_6_.T = !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_6_.Q # reg_sm_0_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q ; (4 pterms, 10 signals) timer_6_.C = clk ; (1 pterm, 1 signal) timer_6_.AR = !reset_n ; (1 pterm, 1 signal) timer_7_.T = reg_sm_0_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_7_.Q ; (4 pterms, 11 signals) timer_7_.C = clk ; (1 pterm, 1 signal) timer_7_.AR = !reset_n ; (1 pterm, 1 signal) timer_8_.T = reg_sm_0_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_8_.Q ; (4 pterms, 12 signals) timer_8_.C = clk ; (1 pterm, 1 signal) timer_8_.AR = !reset_n ; (1 pterm, 1 signal) timer_9_.T = reg_sm_0_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_9_.Q ; (4 pterms, 13 signals) timer_9_.C = clk ; (1 pterm, 1 signal) timer_9_.AR = !reset_n ; (1 pterm, 1 signal)