Timing Report

//  Project = oase
//  Family  = lc4k
//  Device  = LC4256V
//  Speed   = -3
//  Voltage = 3.3
//  Operating Condition = COM
//  Data sheet version  = 3.2

//  Pass Bidirection = OFF
//  Pass S/R = OFF
//  Pass Latch = OFF
//  Pass Clock = OFF
//  Maximum Paths = 20
//  T_SU Endpoints D/T inputs = ON
//  T_SU Endpoints CE inputs = OFF
//  T_SU Endpoints S/R inputs = OFF
//  T_SU Endpoints RAM gated = ON
//  Fmax of CE = ON
//  Fmax of RAM = ON

//  Location(From => To)
//    Pin number: numeric number preceded by "p", BGA number as is
//    Macrocell number: Segment#,GLB#,Macrocell#
//                      Segment#: starts from 0 (if applicable)
//                      GLB#: starts from A..Z, AA..ZZ
//                      Macrocell#: starts from 0 to 31
Summary for Timing Constraints:
  -- fMAX_0 =   5.95 ns (  8.00) :  passed with slack =   2.05 (168.07 MHz)
  Total constraints: 1, passed: 1, not passed: 0


fMAX_0 =  8.00 , "clk ", "clk ";
  Slack  Req.    Delay         Level   Location(From => To)    Source                        Destination                   Destination_Clock
  =====  ====    =====         =====   ====================    ======                        ===========                   =================
  2.05   8.00     5.95           2      H3       =>  E5        reg_cdata_14_.C               reg_sm_0_.T                   clk
  2.05   8.00     5.95           2      H3       =>  C1        reg_cdata_14_.C               reg_sm_1_.D                   clk
  2.15   8.00     5.85           2      P9       =>  G10       timer_0_.C                    reg_sm_2_.D.X1                clk
  2.35   8.00     5.65           1      C1       =>  O7        reg_sm_1_.C                   TXD_0_.CE                     clk
  2.35   8.00     5.65           1      C1       =>  O11       reg_sm_1_.C                   TXD_1_.CE                     clk
  2.35   8.00     5.65           1      C1       =>  O2        reg_sm_1_.C                   TXD_2_.CE                     clk
  2.35   8.00     5.65           1      C1       =>  N1        reg_sm_1_.C                   TXD_3_.CE                     clk
  2.35   8.00     5.65           1      C1       =>  N11       reg_sm_1_.C                   TXD_4_.CE                     clk
  2.35   8.00     5.65           1      C1       =>  N6        reg_sm_1_.C                   TXD_5_.CE                     clk
  2.35   8.00     5.65           1      C1       =>  N3        reg_sm_1_.C                   TXD_6_.CE                     clk
  2.35   8.00     5.65           1      C1       =>  M2        reg_sm_1_.C                   TXD_7_.CE                     clk
  2.35   8.00     5.65           1      C1       =>  M8        reg_sm_1_.C                   TXD_8_.CE                     clk
  2.35   8.00     5.65           1      C1       =>  M5        reg_sm_1_.C                   TXD_9_.CE                     clk
  2.35   8.00     5.65           1      C1       =>  F9        reg_sm_1_.C                   reg_cdata_0_.CE               clk
  2.35   8.00     5.65           1      C1       =>  F6        reg_sm_1_.C                   reg_cdata_2_.CE               clk
  2.35   8.00     5.65           1      C1       =>  A2        reg_sm_1_.C                   reg_cdata_3_.CE               clk
  2.35   8.00     5.65           1      C1       =>  F3        reg_sm_1_.C                   reg_cdata_5_.CE               clk
  2.35   8.00     5.65           1      C1       =>  B1        reg_sm_1_.C                   reg_cdata_6_.CE               clk
  2.35   8.00     5.65           1      C1       =>  H7        reg_sm_1_.C                   reg_cdata_8_.CE               clk
  2.35   8.00     5.65           1      C1       =>  B9        reg_sm_1_.C                   reg_cdata_11_.CE              clk