// Node Statistic Information File
// Tool:  ispLEVER 5.0.01.73.31.05_Starter

// Design 'top_ni' created   Fri Aug 11 13:49:18 2006


// Fmax Logic Level: 2.

// Path: timer_9_.Q
//    -> nx2606
//    -> reg_sm_1_.D

// Signal Name: TESTEN
// Type: Output
BEGIN TESTEN
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: PRBSEN
// Type: Output
BEGIN PRBSEN
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: LCKREFN
// Type: Output
BEGIN LCKREFN
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ENABLE
// Type: Output
BEGIN ENABLE
Fanin Number		0
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: LOOPEN
// Type: Output
BEGIN LOOPEN
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TX_ER
// Type: Output
BEGIN TX_ER
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: EN
// Type: Output
BEGIN EN
Fanin Number		0
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: SD2ANL
// Type: Output
BEGIN SD2ANL
Fanin Number		0
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: SCL
// Type: Tri
BEGIN SCL
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: SCL.OE
// Type: Tri
BEGIN SCL.OE
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: SDA
// Type: Tri
BEGIN SDA
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: SDA.OE
// Type: Tri
BEGIN SDA.OE
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: jTDO
// Type: Tri
BEGIN jTDO
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: jTDO.OE
// Type: Tri
BEGIN jTDO.OE
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_5_.D
// Type: Output_reg
BEGIN TXD_5_.D
Fanin Number		9
Pterm Number		9
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TXD_5_.Q            	9
Fanin Output    	TXD_4_.Q            	5
Fanin Output    	TXD_3_.Q            	7
Fanin Output    	TXD_2_.Q            	5
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Signal Name: TXD_5_.C
// Type: Output_reg
BEGIN TXD_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_5_.CE-
// Type: Output_reg
BEGIN TXD_5_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_5_.AR
// Type: Output_reg
BEGIN TXD_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_4_.T
// Type: Output_reg
BEGIN TXD_4_.T
Fanin Number		8
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TXD_4_.Q            	5
Fanin Output    	TXD_3_.Q            	7
Fanin Output    	TXD_2_.Q            	5
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Signal Name: TXD_4_.C
// Type: Output_reg
BEGIN TXD_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_4_.CE-
// Type: Output_reg
BEGIN TXD_4_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_4_.AR
// Type: Output_reg
BEGIN TXD_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_3_.D
// Type: Output_reg
BEGIN TXD_3_.D
Fanin Number		7
Pterm Number		7
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TXD_3_.Q            	7
Fanin Output    	TXD_2_.Q            	5
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Signal Name: TXD_3_.C
// Type: Output_reg
BEGIN TXD_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_3_.CE-
// Type: Output_reg
BEGIN TXD_3_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_3_.AR
// Type: Output_reg
BEGIN TXD_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_2_.T
// Type: Output_reg
BEGIN TXD_2_.T
Fanin Number		6
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TXD_2_.Q            	5
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Signal Name: TXD_2_.C
// Type: Output_reg
BEGIN TXD_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_2_.CE-
// Type: Output_reg
BEGIN TXD_2_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_2_.AR
// Type: Output_reg
BEGIN TXD_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_1_.D
// Type: Output_reg
BEGIN TXD_1_.D
Fanin Number		5
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Signal Name: TXD_1_.C
// Type: Output_reg
BEGIN TXD_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_1_.CE-
// Type: Output_reg
BEGIN TXD_1_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_1_.AR
// Type: Output_reg
BEGIN TXD_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_0_.D
// Type: Output_reg
BEGIN TXD_0_.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TXD_0_.Q            	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Signal Name: TXD_0_.C
// Type: Output_reg
BEGIN TXD_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_0_.CE-
// Type: Output_reg
BEGIN TXD_0_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_0_.AR
// Type: Output_reg
BEGIN TXD_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TX_EN.D
// Type: Output_reg
BEGIN TX_EN.D
Fanin Number		20
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx2639.BLIF         	1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	nx2719.BLIF         	1
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
Fanin Node      	reg_cdata_9_.Q      	5
Fanin Node      	reg_cdata_8_.Q      	5
Fanin Node      	reg_cdata_11_.Q     	8
Fanin Node      	reg_cdata_10_.Q     	7
END

// Signal Name: TX_EN.C
// Type: Output_reg
BEGIN TX_EN.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TX_EN.AR
// Type: Output_reg
BEGIN TX_EN.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_15_.D
// Type: Output_reg
BEGIN TXD_15_.D
Fanin Number		5
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Output    	TXD_15_.Q           	5
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	nx3133.BLIF         	1
END

// Signal Name: TXD_15_.C
// Type: Output_reg
BEGIN TXD_15_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_15_.CE-
// Type: Output_reg
BEGIN TXD_15_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_15_.AR
// Type: Output_reg
BEGIN TXD_15_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_14_.T
// Type: Output_reg
BEGIN TXD_14_.T
Fanin Number		11
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Output    	TXD_14_.Q           	5
Fanin Output    	TXD_13_.Q           	10
Fanin Output    	TXD_12_.Q           	5
Fanin Output    	TXD_11_.Q           	6
Fanin Output    	TXD_10_.Q           	5
Fanin Output    	TXD_9_.Q            	6
Fanin Output    	TXD_8_.Q            	5
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	nx3078.BLIF         	1
END

// Signal Name: TXD_14_.C
// Type: Output_reg
BEGIN TXD_14_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_14_.CE-
// Type: Output_reg
BEGIN TXD_14_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_14_.AR
// Type: Output_reg
BEGIN TXD_14_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_13_.D
// Type: Output_reg
BEGIN TXD_13_.D
Fanin Number		10
Pterm Number		10
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Output    	TXD_13_.Q           	10
Fanin Output    	TXD_12_.Q           	5
Fanin Output    	TXD_11_.Q           	6
Fanin Output    	TXD_10_.Q           	5
Fanin Output    	TXD_9_.Q            	6
Fanin Output    	TXD_8_.Q            	5
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	nx3078.BLIF         	1
END

// Signal Name: TXD_13_.C
// Type: Output_reg
BEGIN TXD_13_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_13_.CE-
// Type: Output_reg
BEGIN TXD_13_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_13_.AR
// Type: Output_reg
BEGIN TXD_13_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_12_.T
// Type: Output_reg
BEGIN TXD_12_.T
Fanin Number		9
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Output    	TXD_12_.Q           	5
Fanin Output    	TXD_11_.Q           	6
Fanin Output    	TXD_10_.Q           	5
Fanin Output    	TXD_9_.Q            	6
Fanin Output    	TXD_8_.Q            	5
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	nx3078.BLIF         	1
END

// Signal Name: TXD_12_.C
// Type: Output_reg
BEGIN TXD_12_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_12_.CE-
// Type: Output_reg
BEGIN TXD_12_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_12_.AR
// Type: Output_reg
BEGIN TXD_12_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_11_.T
// Type: Output_reg
BEGIN TXD_11_.T
Fanin Number		15
Pterm Number		6
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TXD_11_.Q           	6
Fanin Output    	TXD_10_.Q           	5
Fanin Output    	TXD_9_.Q            	6
Fanin Output    	TXD_8_.Q            	5
Fanin Output    	TXD_7_.Q            	6
Fanin Output    	TXD_6_.Q            	5
Fanin Output    	TXD_5_.Q            	9
Fanin Output    	TXD_4_.Q            	5
Fanin Output    	TXD_3_.Q            	7
Fanin Output    	TXD_2_.Q            	5
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Signal Name: TXD_11_.C
// Type: Output_reg
BEGIN TXD_11_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_11_.CE-
// Type: Output_reg
BEGIN TXD_11_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_11_.AR
// Type: Output_reg
BEGIN TXD_11_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_10_.T
// Type: Output_reg
BEGIN TXD_10_.T
Fanin Number		14
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TXD_10_.Q           	5
Fanin Output    	TXD_9_.Q            	6
Fanin Output    	TXD_8_.Q            	5
Fanin Output    	TXD_7_.Q            	6
Fanin Output    	TXD_6_.Q            	5
Fanin Output    	TXD_5_.Q            	9
Fanin Output    	TXD_4_.Q            	5
Fanin Output    	TXD_3_.Q            	7
Fanin Output    	TXD_2_.Q            	5
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Signal Name: TXD_10_.C
// Type: Output_reg
BEGIN TXD_10_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_10_.CE-
// Type: Output_reg
BEGIN TXD_10_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_10_.AR
// Type: Output_reg
BEGIN TXD_10_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_9_.T
// Type: Output_reg
BEGIN TXD_9_.T
Fanin Number		13
Pterm Number		6
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TXD_9_.Q            	6
Fanin Output    	TXD_8_.Q            	5
Fanin Output    	TXD_7_.Q            	6
Fanin Output    	TXD_6_.Q            	5
Fanin Output    	TXD_5_.Q            	9
Fanin Output    	TXD_4_.Q            	5
Fanin Output    	TXD_3_.Q            	7
Fanin Output    	TXD_2_.Q            	5
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Signal Name: TXD_9_.C
// Type: Output_reg
BEGIN TXD_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_9_.CE-
// Type: Output_reg
BEGIN TXD_9_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_9_.AR
// Type: Output_reg
BEGIN TXD_9_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_8_.T
// Type: Output_reg
BEGIN TXD_8_.T
Fanin Number		12
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TXD_8_.Q            	5
Fanin Output    	TXD_7_.Q            	6
Fanin Output    	TXD_6_.Q            	5
Fanin Output    	TXD_5_.Q            	9
Fanin Output    	TXD_4_.Q            	5
Fanin Output    	TXD_3_.Q            	7
Fanin Output    	TXD_2_.Q            	5
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Signal Name: TXD_8_.C
// Type: Output_reg
BEGIN TXD_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_8_.CE-
// Type: Output_reg
BEGIN TXD_8_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_8_.AR
// Type: Output_reg
BEGIN TXD_8_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_7_.T
// Type: Output_reg
BEGIN TXD_7_.T
Fanin Number		11
Pterm Number		6
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TXD_7_.Q            	6
Fanin Output    	TXD_6_.Q            	5
Fanin Output    	TXD_5_.Q            	9
Fanin Output    	TXD_4_.Q            	5
Fanin Output    	TXD_3_.Q            	7
Fanin Output    	TXD_2_.Q            	5
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Signal Name: TXD_7_.C
// Type: Output_reg
BEGIN TXD_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_7_.CE-
// Type: Output_reg
BEGIN TXD_7_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_7_.AR
// Type: Output_reg
BEGIN TXD_7_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TXD_6_.T
// Type: Output_reg
BEGIN TXD_6_.T
Fanin Number		10
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TXD_6_.Q            	5
Fanin Output    	TXD_5_.Q            	9
Fanin Output    	TXD_4_.Q            	5
Fanin Output    	TXD_3_.Q            	7
Fanin Output    	TXD_2_.Q            	5
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Signal Name: TXD_6_.C
// Type: Output_reg
BEGIN TXD_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_6_.CE-
// Type: Output_reg
BEGIN TXD_6_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: TXD_6_.AR
// Type: Output_reg
BEGIN TXD_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: nx2639
// Type: Node
BEGIN nx2639
Fanin Number		8
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	reg_cdata_7_.Q      	5
Fanin Node      	reg_cdata_6_.Q      	5
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
END

// Signal Name: nx2704
// Type: Node
BEGIN nx2704
Fanin Number		15
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_7_.Q      	5
Fanin Node      	reg_cdata_6_.Q      	5
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
Fanin Node      	reg_cdata_9_.Q      	5
Fanin Node      	reg_cdata_8_.Q      	5
Fanin Node      	reg_cdata_11_.Q     	8
Fanin Node      	reg_cdata_10_.Q     	7
END

// Signal Name: reg_sm_1_.D
// Type: Node_reg
BEGIN reg_sm_1_.D
Fanin Number		16
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_7_.Q      	5
Fanin Node      	reg_cdata_6_.Q      	5
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
Fanin Node      	reg_cdata_9_.Q      	5
Fanin Node      	reg_cdata_8_.Q      	5
Fanin Node      	reg_cdata_11_.Q     	8
Fanin Node      	reg_cdata_10_.Q     	7
Fanin Node      	nx2606.BLIF         	1
END

// Signal Name: reg_sm_1_.C
// Type: Node_reg
BEGIN reg_sm_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_sm_1_.AR
// Type: Node_reg
BEGIN reg_sm_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_sm_0_.D.X1
// Type: Node_reg
BEGIN reg_sm_0_.D.X1
Fanin Number		23
Pterm Number		9
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx2639.BLIF         	1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_start_s.Q       	1
Fanin Node      	nx2719.BLIF         	1
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
Fanin Node      	reg_cdata_9_.Q      	5
Fanin Node      	reg_cdata_8_.Q      	5
Fanin Node      	reg_cdata_11_.Q     	8
Fanin Node      	reg_cdata_10_.Q     	7
Fanin Node      	nx2606.BLIF         	1
Fanin Node      	nx2616.BLIF         	1
END

// Signal Name: reg_sm_0_.D.X2
// Type: Node_reg
BEGIN reg_sm_0_.D.X2
Fanin Number		5
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx2639.BLIF         	1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_8_.Q      	5
END

// Signal Name: reg_sm_0_.C
// Type: Node_reg
BEGIN reg_sm_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_sm_0_.AR
// Type: Node_reg
BEGIN reg_sm_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: timer_9_.T
// Type: Node_reg
BEGIN timer_9_.T
Fanin Number		13
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	timer_9_.Q          	4
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	timer_8_.Q          	4
Fanin Node      	timer_7_.Q          	4
Fanin Node      	timer_6_.Q          	4
Fanin Node      	timer_5_.Q          	4
Fanin Node      	timer_4_.Q          	4
Fanin Node      	timer_3_.Q          	5
Fanin Node      	timer_2_.Q          	4
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
END

// Signal Name: timer_9_.C
// Type: Node_reg
BEGIN timer_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: timer_9_.AR
// Type: Node_reg
BEGIN timer_9_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_sm_2_.D
// Type: Node_reg
BEGIN reg_sm_2_.D
Fanin Number		17
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	timer_9_.Q          	4
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_start_s.Q       	1
Fanin Node      	timer_8_.Q          	4
Fanin Node      	timer_7_.Q          	4
Fanin Node      	timer_6_.Q          	4
Fanin Node      	timer_5_.Q          	4
Fanin Node      	timer_4_.Q          	4
Fanin Node      	timer_3_.Q          	5
Fanin Node      	timer_2_.Q          	4
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
Fanin Node      	timer_11_.Q         	4
Fanin Node      	timer_10_.Q         	4
Fanin Node      	nx2616.BLIF         	1
END

// Signal Name: reg_sm_2_.C
// Type: Node_reg
BEGIN reg_sm_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_sm_2_.AR
// Type: Node_reg
BEGIN reg_sm_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_start_s.D
// Type: Node_reg
BEGIN reg_start_s.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	start.BLIF          	0
END

// Signal Name: reg_start_s.C
// Type: Node_reg
BEGIN reg_start_s.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_start_s.AR
// Type: Node_reg
BEGIN reg_start_s.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: nx2719
// Type: Node
BEGIN nx2719
Fanin Number		12
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	reg_cdata_7_.Q      	5
Fanin Node      	reg_cdata_6_.Q      	5
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
Fanin Node      	reg_cdata_9_.Q      	5
Fanin Node      	reg_cdata_8_.Q      	5
Fanin Node      	reg_cdata_11_.Q     	8
Fanin Node      	reg_cdata_10_.Q     	7
END

// Signal Name: reg_cdata_7_.T
// Type: Node_reg
BEGIN reg_cdata_7_.T
Fanin Number		11
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_7_.Q      	5
Fanin Node      	reg_cdata_6_.Q      	5
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
END

// Signal Name: reg_cdata_7_.C
// Type: Node_reg
BEGIN reg_cdata_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_cdata_7_.CE-
// Type: Node_reg
BEGIN reg_cdata_7_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_cdata_7_.AR
// Type: Node_reg
BEGIN reg_cdata_7_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_31_.T
// Type: Node_reg
BEGIN reg_i_data_31_.T
Fanin Number		13
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_i_data_31_.C
// Type: Node_reg
BEGIN reg_i_data_31_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_31_.CE
// Type: Node_reg
BEGIN reg_i_data_31_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_31_.AR
// Type: Node_reg
BEGIN reg_i_data_31_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_30_.T
// Type: Node_reg
BEGIN reg_i_data_30_.T
Fanin Number		12
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_i_data_30_.C
// Type: Node_reg
BEGIN reg_i_data_30_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_30_.CE
// Type: Node_reg
BEGIN reg_i_data_30_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_30_.AR
// Type: Node_reg
BEGIN reg_i_data_30_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_29_.T
// Type: Node_reg
BEGIN reg_i_data_29_.T
Fanin Number		11
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_i_data_29_.C
// Type: Node_reg
BEGIN reg_i_data_29_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_29_.CE
// Type: Node_reg
BEGIN reg_i_data_29_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_29_.AR
// Type: Node_reg
BEGIN reg_i_data_29_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_28_.T
// Type: Node_reg
BEGIN reg_i_data_28_.T
Fanin Number		8
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	nx2965.BLIF         	1
END

// Signal Name: reg_i_data_28_.C
// Type: Node_reg
BEGIN reg_i_data_28_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_28_.CE
// Type: Node_reg
BEGIN reg_i_data_28_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_28_.AR
// Type: Node_reg
BEGIN reg_i_data_28_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_27_.T
// Type: Node_reg
BEGIN reg_i_data_27_.T
Fanin Number		7
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	nx2965.BLIF         	1
END

// Signal Name: reg_i_data_27_.C
// Type: Node_reg
BEGIN reg_i_data_27_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_27_.CE
// Type: Node_reg
BEGIN reg_i_data_27_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_27_.AR
// Type: Node_reg
BEGIN reg_i_data_27_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_26_.D.X1
// Type: Node_reg
BEGIN reg_i_data_26_.D.X1
Fanin Number		6
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	nx2965.BLIF         	1
END

// Signal Name: reg_i_data_26_.D.X2
// Type: Node_reg
BEGIN reg_i_data_26_.D.X2
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	nx2965.BLIF         	1
END

// Signal Name: reg_i_data_26_.C
// Type: Node_reg
BEGIN reg_i_data_26_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_26_.CE
// Type: Node_reg
BEGIN reg_i_data_26_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_26_.AR
// Type: Node_reg
BEGIN reg_i_data_26_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_25_.D
// Type: Node_reg
BEGIN reg_i_data_25_.D
Fanin Number		5
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	nx2965.BLIF         	1
END

// Signal Name: reg_i_data_25_.C
// Type: Node_reg
BEGIN reg_i_data_25_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_25_.CE
// Type: Node_reg
BEGIN reg_i_data_25_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_25_.AR
// Type: Node_reg
BEGIN reg_i_data_25_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_24_.D
// Type: Node_reg
BEGIN reg_i_data_24_.D
Fanin Number		4
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	nx2965.BLIF         	1
END

// Signal Name: reg_i_data_24_.C
// Type: Node_reg
BEGIN reg_i_data_24_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_24_.CE
// Type: Node_reg
BEGIN reg_i_data_24_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_24_.AR
// Type: Node_reg
BEGIN reg_i_data_24_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_23_.D
// Type: Node_reg
BEGIN reg_i_data_23_.D
Fanin Number		5
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_i_data_23_.C
// Type: Node_reg
BEGIN reg_i_data_23_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_23_.CE
// Type: Node_reg
BEGIN reg_i_data_23_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_23_.AR
// Type: Node_reg
BEGIN reg_i_data_23_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_22_.D
// Type: Node_reg
BEGIN reg_i_data_22_.D
Fanin Number		25
Pterm Number		46
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	reg_i_data_21_.Q    	3
Fanin Node      	reg_i_data_20_.Q    	3
Fanin Node      	reg_i_data_19_.Q    	3
Fanin Node      	reg_i_data_18_.Q    	3
Fanin Node      	reg_i_data_17_.Q    	3
Fanin Node      	reg_i_data_16_.Q    	3
Fanin Node      	reg_i_data_15_.Q    	3
Fanin Node      	reg_i_data_14_.Q    	3
Fanin Node      	reg_i_data_13_.Q    	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_22_.C
// Type: Node_reg
BEGIN reg_i_data_22_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_22_.CE
// Type: Node_reg
BEGIN reg_i_data_22_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_22_.AR
// Type: Node_reg
BEGIN reg_i_data_22_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_21_.T
// Type: Node_reg
BEGIN reg_i_data_21_.T
Fanin Number		24
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_21_.Q    	3
Fanin Node      	reg_i_data_20_.Q    	3
Fanin Node      	reg_i_data_19_.Q    	3
Fanin Node      	reg_i_data_18_.Q    	3
Fanin Node      	reg_i_data_17_.Q    	3
Fanin Node      	reg_i_data_16_.Q    	3
Fanin Node      	reg_i_data_15_.Q    	3
Fanin Node      	reg_i_data_14_.Q    	3
Fanin Node      	reg_i_data_13_.Q    	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_21_.C
// Type: Node_reg
BEGIN reg_i_data_21_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_21_.CE
// Type: Node_reg
BEGIN reg_i_data_21_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_21_.AR
// Type: Node_reg
BEGIN reg_i_data_21_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_20_.T
// Type: Node_reg
BEGIN reg_i_data_20_.T
Fanin Number		23
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_20_.Q    	3
Fanin Node      	reg_i_data_19_.Q    	3
Fanin Node      	reg_i_data_18_.Q    	3
Fanin Node      	reg_i_data_17_.Q    	3
Fanin Node      	reg_i_data_16_.Q    	3
Fanin Node      	reg_i_data_15_.Q    	3
Fanin Node      	reg_i_data_14_.Q    	3
Fanin Node      	reg_i_data_13_.Q    	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_20_.C
// Type: Node_reg
BEGIN reg_i_data_20_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_20_.CE
// Type: Node_reg
BEGIN reg_i_data_20_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_20_.AR
// Type: Node_reg
BEGIN reg_i_data_20_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_19_.T
// Type: Node_reg
BEGIN reg_i_data_19_.T
Fanin Number		22
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_19_.Q    	3
Fanin Node      	reg_i_data_18_.Q    	3
Fanin Node      	reg_i_data_17_.Q    	3
Fanin Node      	reg_i_data_16_.Q    	3
Fanin Node      	reg_i_data_15_.Q    	3
Fanin Node      	reg_i_data_14_.Q    	3
Fanin Node      	reg_i_data_13_.Q    	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_19_.C
// Type: Node_reg
BEGIN reg_i_data_19_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_19_.CE
// Type: Node_reg
BEGIN reg_i_data_19_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_19_.AR
// Type: Node_reg
BEGIN reg_i_data_19_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_18_.T
// Type: Node_reg
BEGIN reg_i_data_18_.T
Fanin Number		21
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_18_.Q    	3
Fanin Node      	reg_i_data_17_.Q    	3
Fanin Node      	reg_i_data_16_.Q    	3
Fanin Node      	reg_i_data_15_.Q    	3
Fanin Node      	reg_i_data_14_.Q    	3
Fanin Node      	reg_i_data_13_.Q    	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_18_.C
// Type: Node_reg
BEGIN reg_i_data_18_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_18_.CE
// Type: Node_reg
BEGIN reg_i_data_18_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_18_.AR
// Type: Node_reg
BEGIN reg_i_data_18_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_17_.T
// Type: Node_reg
BEGIN reg_i_data_17_.T
Fanin Number		20
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_17_.Q    	3
Fanin Node      	reg_i_data_16_.Q    	3
Fanin Node      	reg_i_data_15_.Q    	3
Fanin Node      	reg_i_data_14_.Q    	3
Fanin Node      	reg_i_data_13_.Q    	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_17_.C
// Type: Node_reg
BEGIN reg_i_data_17_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_17_.CE
// Type: Node_reg
BEGIN reg_i_data_17_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_17_.AR
// Type: Node_reg
BEGIN reg_i_data_17_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_16_.T
// Type: Node_reg
BEGIN reg_i_data_16_.T
Fanin Number		19
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_16_.Q    	3
Fanin Node      	reg_i_data_15_.Q    	3
Fanin Node      	reg_i_data_14_.Q    	3
Fanin Node      	reg_i_data_13_.Q    	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_16_.C
// Type: Node_reg
BEGIN reg_i_data_16_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_16_.CE
// Type: Node_reg
BEGIN reg_i_data_16_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_16_.AR
// Type: Node_reg
BEGIN reg_i_data_16_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_15_.T
// Type: Node_reg
BEGIN reg_i_data_15_.T
Fanin Number		18
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_15_.Q    	3
Fanin Node      	reg_i_data_14_.Q    	3
Fanin Node      	reg_i_data_13_.Q    	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_15_.C
// Type: Node_reg
BEGIN reg_i_data_15_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_15_.CE
// Type: Node_reg
BEGIN reg_i_data_15_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_15_.AR
// Type: Node_reg
BEGIN reg_i_data_15_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_14_.T
// Type: Node_reg
BEGIN reg_i_data_14_.T
Fanin Number		17
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_14_.Q    	3
Fanin Node      	reg_i_data_13_.Q    	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_14_.C
// Type: Node_reg
BEGIN reg_i_data_14_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_14_.CE
// Type: Node_reg
BEGIN reg_i_data_14_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_14_.AR
// Type: Node_reg
BEGIN reg_i_data_14_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_13_.T
// Type: Node_reg
BEGIN reg_i_data_13_.T
Fanin Number		16
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_13_.Q    	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_13_.C
// Type: Node_reg
BEGIN reg_i_data_13_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_13_.CE
// Type: Node_reg
BEGIN reg_i_data_13_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_13_.AR
// Type: Node_reg
BEGIN reg_i_data_13_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_12_.T
// Type: Node_reg
BEGIN reg_i_data_12_.T
Fanin Number		15
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_12_.C
// Type: Node_reg
BEGIN reg_i_data_12_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_12_.CE
// Type: Node_reg
BEGIN reg_i_data_12_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_12_.AR
// Type: Node_reg
BEGIN reg_i_data_12_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_11_.T
// Type: Node_reg
BEGIN reg_i_data_11_.T
Fanin Number		14
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_11_.C
// Type: Node_reg
BEGIN reg_i_data_11_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_11_.CE
// Type: Node_reg
BEGIN reg_i_data_11_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_11_.AR
// Type: Node_reg
BEGIN reg_i_data_11_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_10_.T
// Type: Node_reg
BEGIN reg_i_data_10_.T
Fanin Number		13
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_10_.C
// Type: Node_reg
BEGIN reg_i_data_10_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_10_.CE
// Type: Node_reg
BEGIN reg_i_data_10_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_10_.AR
// Type: Node_reg
BEGIN reg_i_data_10_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_9_.T
// Type: Node_reg
BEGIN reg_i_data_9_.T
Fanin Number		12
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_9_.C
// Type: Node_reg
BEGIN reg_i_data_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_9_.CE
// Type: Node_reg
BEGIN reg_i_data_9_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_9_.AR
// Type: Node_reg
BEGIN reg_i_data_9_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_8_.T
// Type: Node_reg
BEGIN reg_i_data_8_.T
Fanin Number		11
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_8_.C
// Type: Node_reg
BEGIN reg_i_data_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_8_.CE
// Type: Node_reg
BEGIN reg_i_data_8_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_8_.AR
// Type: Node_reg
BEGIN reg_i_data_8_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_7_.T
// Type: Node_reg
BEGIN reg_i_data_7_.T
Fanin Number		10
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_7_.C
// Type: Node_reg
BEGIN reg_i_data_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_7_.CE
// Type: Node_reg
BEGIN reg_i_data_7_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_7_.AR
// Type: Node_reg
BEGIN reg_i_data_7_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_6_.T
// Type: Node_reg
BEGIN reg_i_data_6_.T
Fanin Number		9
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_6_.C
// Type: Node_reg
BEGIN reg_i_data_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_6_.CE
// Type: Node_reg
BEGIN reg_i_data_6_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_6_.AR
// Type: Node_reg
BEGIN reg_i_data_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_5_.T
// Type: Node_reg
BEGIN reg_i_data_5_.T
Fanin Number		8
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_5_.C
// Type: Node_reg
BEGIN reg_i_data_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_5_.CE
// Type: Node_reg
BEGIN reg_i_data_5_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_5_.AR
// Type: Node_reg
BEGIN reg_i_data_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_4_.T
// Type: Node_reg
BEGIN reg_i_data_4_.T
Fanin Number		7
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_4_.C
// Type: Node_reg
BEGIN reg_i_data_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_4_.CE
// Type: Node_reg
BEGIN reg_i_data_4_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_4_.AR
// Type: Node_reg
BEGIN reg_i_data_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_3_.D
// Type: Node_reg
BEGIN reg_i_data_3_.D
Fanin Number		6
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_3_.C
// Type: Node_reg
BEGIN reg_i_data_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_3_.CE
// Type: Node_reg
BEGIN reg_i_data_3_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_3_.AR
// Type: Node_reg
BEGIN reg_i_data_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_2_.D
// Type: Node_reg
BEGIN reg_i_data_2_.D
Fanin Number		5
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_2_.C
// Type: Node_reg
BEGIN reg_i_data_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_2_.CE
// Type: Node_reg
BEGIN reg_i_data_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_2_.AR
// Type: Node_reg
BEGIN reg_i_data_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_1_.D
// Type: Node_reg
BEGIN reg_i_data_1_.D
Fanin Number		4
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_1_.C
// Type: Node_reg
BEGIN reg_i_data_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_1_.CE
// Type: Node_reg
BEGIN reg_i_data_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_1_.AR
// Type: Node_reg
BEGIN reg_i_data_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_i_data_0_.D
// Type: Node_reg
BEGIN reg_i_data_0_.D
Fanin Number		3
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_i_data_0_.C
// Type: Node_reg
BEGIN reg_i_data_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_i_data_0_.CE
// Type: Node_reg
BEGIN reg_i_data_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_i_data_31__0.BLIF	2
END

// Signal Name: reg_i_data_0_.AR
// Type: Node_reg
BEGIN reg_i_data_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: nx2953
// Type: Node
BEGIN nx2953
Fanin Number		22
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	reg_i_data_21_.Q    	3
Fanin Node      	reg_i_data_20_.Q    	3
Fanin Node      	reg_i_data_19_.Q    	3
Fanin Node      	reg_i_data_18_.Q    	3
Fanin Node      	reg_i_data_17_.Q    	3
Fanin Node      	reg_i_data_16_.Q    	3
Fanin Node      	reg_i_data_15_.Q    	3
Fanin Node      	reg_i_data_14_.Q    	3
Fanin Node      	reg_i_data_13_.Q    	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: nx2965
// Type: Node
BEGIN nx2965
Fanin Number		24
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	reg_i_data_21_.Q    	3
Fanin Node      	reg_i_data_20_.Q    	3
Fanin Node      	reg_i_data_19_.Q    	3
Fanin Node      	reg_i_data_18_.Q    	3
Fanin Node      	reg_i_data_17_.Q    	3
Fanin Node      	reg_i_data_16_.Q    	3
Fanin Node      	reg_i_data_15_.Q    	3
Fanin Node      	reg_i_data_14_.Q    	3
Fanin Node      	reg_i_data_13_.Q    	3
Fanin Node      	reg_i_data_12_.Q    	3
Fanin Node      	reg_i_data_11_.Q    	3
Fanin Node      	reg_i_data_10_.Q    	3
Fanin Node      	reg_i_data_9_.Q     	3
Fanin Node      	reg_i_data_8_.Q     	3
Fanin Node      	reg_i_data_7_.Q     	3
Fanin Node      	reg_i_data_6_.Q     	3
Fanin Node      	reg_i_data_5_.Q     	3
Fanin Node      	reg_i_data_4_.Q     	3
Fanin Node      	reg_i_data_3_.Q     	5
Fanin Node      	reg_i_data_2_.Q     	4
Fanin Node      	reg_i_data_1_.Q     	3
Fanin Node      	reg_i_data_0_.Q     	2
END

// Signal Name: reg_cdata_6_.T
// Type: Node_reg
BEGIN reg_cdata_6_.T
Fanin Number		10
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_6_.Q      	5
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
END

// Signal Name: reg_cdata_6_.C
// Type: Node_reg
BEGIN reg_cdata_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_cdata_6_.CE-
// Type: Node_reg
BEGIN reg_cdata_6_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_cdata_6_.AR
// Type: Node_reg
BEGIN reg_cdata_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_cdata_5_.T
// Type: Node_reg
BEGIN reg_cdata_5_.T
Fanin Number		9
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
END

// Signal Name: reg_cdata_5_.C
// Type: Node_reg
BEGIN reg_cdata_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_cdata_5_.CE-
// Type: Node_reg
BEGIN reg_cdata_5_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_cdata_5_.AR
// Type: Node_reg
BEGIN reg_cdata_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_cdata_4_.T
// Type: Node_reg
BEGIN reg_cdata_4_.T
Fanin Number		8
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
END

// Signal Name: reg_cdata_4_.C
// Type: Node_reg
BEGIN reg_cdata_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_cdata_4_.CE-
// Type: Node_reg
BEGIN reg_cdata_4_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_cdata_4_.AR
// Type: Node_reg
BEGIN reg_cdata_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_cdata_3_.D
// Type: Node_reg
BEGIN reg_cdata_3_.D
Fanin Number		15
Pterm Number		7
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_7_.Q      	5
Fanin Node      	reg_cdata_6_.Q      	5
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
Fanin Node      	reg_cdata_9_.Q      	5
Fanin Node      	reg_cdata_8_.Q      	5
Fanin Node      	reg_cdata_11_.Q     	8
Fanin Node      	reg_cdata_10_.Q     	7
END

// Signal Name: reg_cdata_3_.C
// Type: Node_reg
BEGIN reg_cdata_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_cdata_3_.CE-
// Type: Node_reg
BEGIN reg_cdata_3_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_cdata_3_.AR
// Type: Node_reg
BEGIN reg_cdata_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_cdata_2_.D
// Type: Node_reg
BEGIN reg_cdata_2_.D
Fanin Number		6
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
END

// Signal Name: reg_cdata_2_.C
// Type: Node_reg
BEGIN reg_cdata_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_cdata_2_.CE-
// Type: Node_reg
BEGIN reg_cdata_2_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_cdata_2_.AR
// Type: Node_reg
BEGIN reg_cdata_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: nx3078
// Type: Node
BEGIN nx3078
Fanin Number		8
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_7_.Q            	6
Fanin Output    	TXD_6_.Q            	5
Fanin Output    	TXD_5_.Q            	9
Fanin Output    	TXD_4_.Q            	5
Fanin Output    	TXD_3_.Q            	7
Fanin Output    	TXD_2_.Q            	5
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
END

// Signal Name: reg_cdata_1_.D
// Type: Node_reg
BEGIN reg_cdata_1_.D
Fanin Number		15
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_7_.Q      	5
Fanin Node      	reg_cdata_6_.Q      	5
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
Fanin Node      	reg_cdata_9_.Q      	5
Fanin Node      	reg_cdata_8_.Q      	5
Fanin Node      	reg_cdata_11_.Q     	8
Fanin Node      	reg_cdata_10_.Q     	7
END

// Signal Name: reg_cdata_1_.C
// Type: Node_reg
BEGIN reg_cdata_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_cdata_1_.CE-
// Type: Node_reg
BEGIN reg_cdata_1_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_cdata_1_.AR
// Type: Node_reg
BEGIN reg_cdata_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_cdata_0_.D
// Type: Node_reg
BEGIN reg_cdata_0_.D
Fanin Number		15
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_7_.Q      	5
Fanin Node      	reg_cdata_6_.Q      	5
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
Fanin Node      	reg_cdata_9_.Q      	5
Fanin Node      	reg_cdata_8_.Q      	5
Fanin Node      	reg_cdata_11_.Q     	8
Fanin Node      	reg_cdata_10_.Q     	7
END

// Signal Name: reg_cdata_0_.C
// Type: Node_reg
BEGIN reg_cdata_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_cdata_0_.CE-
// Type: Node_reg
BEGIN reg_cdata_0_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_cdata_0_.AR
// Type: Node_reg
BEGIN reg_cdata_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_cdata_9_.T
// Type: Node_reg
BEGIN reg_cdata_9_.T
Fanin Number		13
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_7_.Q      	5
Fanin Node      	reg_cdata_6_.Q      	5
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
Fanin Node      	reg_cdata_9_.Q      	5
Fanin Node      	reg_cdata_8_.Q      	5
END

// Signal Name: reg_cdata_9_.C
// Type: Node_reg
BEGIN reg_cdata_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_cdata_9_.CE-
// Type: Node_reg
BEGIN reg_cdata_9_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_cdata_9_.AR
// Type: Node_reg
BEGIN reg_cdata_9_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_cdata_8_.T
// Type: Node_reg
BEGIN reg_cdata_8_.T
Fanin Number		12
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_7_.Q      	5
Fanin Node      	reg_cdata_6_.Q      	5
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
Fanin Node      	reg_cdata_8_.Q      	5
END

// Signal Name: reg_cdata_8_.C
// Type: Node_reg
BEGIN reg_cdata_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_cdata_8_.CE-
// Type: Node_reg
BEGIN reg_cdata_8_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_cdata_8_.AR
// Type: Node_reg
BEGIN reg_cdata_8_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_cdata_11_.D
// Type: Node_reg
BEGIN reg_cdata_11_.D
Fanin Number		9
Pterm Number		8
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx2639.BLIF         	1
Fanin Node      	nx2704.BLIF         	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_9_.Q      	5
Fanin Node      	reg_cdata_8_.Q      	5
Fanin Node      	reg_cdata_11_.Q     	8
Fanin Node      	reg_cdata_10_.Q     	7
END

// Signal Name: reg_cdata_11_.C
// Type: Node_reg
BEGIN reg_cdata_11_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_cdata_11_.CE-
// Type: Node_reg
BEGIN reg_cdata_11_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_cdata_11_.AR
// Type: Node_reg
BEGIN reg_cdata_11_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: reg_cdata_10_.D
// Type: Node_reg
BEGIN reg_cdata_10_.D
Fanin Number		8
Pterm Number		7
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx2639.BLIF         	1
Fanin Node      	nx2704.BLIF         	4
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_cdata_9_.Q      	5
Fanin Node      	reg_cdata_8_.Q      	5
Fanin Node      	reg_cdata_10_.Q     	7
END

// Signal Name: reg_cdata_10_.C
// Type: Node_reg
BEGIN reg_cdata_10_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: reg_cdata_10_.CE-
// Type: Node_reg
BEGIN reg_cdata_10_.CE
Fanin Number		14
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	reg_i_data_31_.Q    	3
Fanin Node      	reg_i_data_30_.Q    	3
Fanin Node      	reg_i_data_29_.Q    	3
Fanin Node      	reg_i_data_28_.Q    	3
Fanin Node      	reg_i_data_27_.Q    	3
Fanin Node      	reg_i_data_26_.Q    	3
Fanin Node      	reg_i_data_25_.Q    	4
Fanin Node      	reg_i_data_24_.Q    	3
Fanin Node      	reg_i_data_23_.Q    	4
Fanin Node      	reg_i_data_22_.Q    	46
Fanin Node      	nx2953.BLIF         	1
END

// Signal Name: reg_cdata_10_.AR
// Type: Node_reg
BEGIN reg_cdata_10_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: nx3133
// Type: Node
BEGIN nx3133
Fanin Number		15
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_14_.Q           	5
Fanin Output    	TXD_13_.Q           	10
Fanin Output    	TXD_12_.Q           	5
Fanin Output    	TXD_11_.Q           	6
Fanin Output    	TXD_10_.Q           	5
Fanin Output    	TXD_9_.Q            	6
Fanin Output    	TXD_8_.Q            	5
Fanin Output    	TXD_7_.Q            	6
Fanin Output    	TXD_6_.Q            	5
Fanin Output    	TXD_5_.Q            	9
Fanin Output    	TXD_4_.Q            	5
Fanin Output    	TXD_3_.Q            	7
Fanin Output    	TXD_2_.Q            	5
Fanin Output    	TXD_1_.Q            	5
Fanin Output    	TXD_0_.Q            	4
END

// Signal Name: timer_8_.T
// Type: Node_reg
BEGIN timer_8_.T
Fanin Number		12
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	timer_8_.Q          	4
Fanin Node      	timer_7_.Q          	4
Fanin Node      	timer_6_.Q          	4
Fanin Node      	timer_5_.Q          	4
Fanin Node      	timer_4_.Q          	4
Fanin Node      	timer_3_.Q          	5
Fanin Node      	timer_2_.Q          	4
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
END

// Signal Name: timer_8_.C
// Type: Node_reg
BEGIN timer_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: timer_8_.AR
// Type: Node_reg
BEGIN timer_8_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: timer_7_.T
// Type: Node_reg
BEGIN timer_7_.T
Fanin Number		11
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	timer_7_.Q          	4
Fanin Node      	timer_6_.Q          	4
Fanin Node      	timer_5_.Q          	4
Fanin Node      	timer_4_.Q          	4
Fanin Node      	timer_3_.Q          	5
Fanin Node      	timer_2_.Q          	4
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
END

// Signal Name: timer_7_.C
// Type: Node_reg
BEGIN timer_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: timer_7_.AR
// Type: Node_reg
BEGIN timer_7_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: timer_6_.T
// Type: Node_reg
BEGIN timer_6_.T
Fanin Number		10
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	timer_6_.Q          	4
Fanin Node      	timer_5_.Q          	4
Fanin Node      	timer_4_.Q          	4
Fanin Node      	timer_3_.Q          	5
Fanin Node      	timer_2_.Q          	4
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
END

// Signal Name: timer_6_.C
// Type: Node_reg
BEGIN timer_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: timer_6_.AR
// Type: Node_reg
BEGIN timer_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: timer_5_.T
// Type: Node_reg
BEGIN timer_5_.T
Fanin Number		9
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	timer_5_.Q          	4
Fanin Node      	timer_4_.Q          	4
Fanin Node      	timer_3_.Q          	5
Fanin Node      	timer_2_.Q          	4
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
END

// Signal Name: timer_5_.C
// Type: Node_reg
BEGIN timer_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: timer_5_.AR
// Type: Node_reg
BEGIN timer_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: timer_4_.T
// Type: Node_reg
BEGIN timer_4_.T
Fanin Number		8
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	timer_4_.Q          	4
Fanin Node      	timer_3_.Q          	5
Fanin Node      	timer_2_.Q          	4
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
END

// Signal Name: timer_4_.C
// Type: Node_reg
BEGIN timer_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: timer_4_.AR
// Type: Node_reg
BEGIN timer_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: timer_3_.D
// Type: Node_reg
BEGIN timer_3_.D
Fanin Number		7
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	timer_3_.Q          	5
Fanin Node      	timer_2_.Q          	4
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
END

// Signal Name: timer_3_.C
// Type: Node_reg
BEGIN timer_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: timer_3_.AR
// Type: Node_reg
BEGIN timer_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: timer_2_.D
// Type: Node_reg
BEGIN timer_2_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	timer_2_.Q          	4
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
END

// Signal Name: timer_2_.C
// Type: Node_reg
BEGIN timer_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: timer_2_.AR
// Type: Node_reg
BEGIN timer_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: timer_1_.D
// Type: Node_reg
BEGIN timer_1_.D
Fanin Number		5
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
END

// Signal Name: timer_1_.C
// Type: Node_reg
BEGIN timer_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: timer_1_.AR
// Type: Node_reg
BEGIN timer_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: timer_0_.D
// Type: Node_reg
BEGIN timer_0_.D
Fanin Number		4
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	timer_0_.Q          	2
END

// Signal Name: timer_0_.C
// Type: Node_reg
BEGIN timer_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: timer_0_.AR
// Type: Node_reg
BEGIN timer_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: timer_11_.T
// Type: Node_reg
BEGIN timer_11_.T
Fanin Number		15
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	timer_9_.Q          	4
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	timer_8_.Q          	4
Fanin Node      	timer_7_.Q          	4
Fanin Node      	timer_6_.Q          	4
Fanin Node      	timer_5_.Q          	4
Fanin Node      	timer_4_.Q          	4
Fanin Node      	timer_3_.Q          	5
Fanin Node      	timer_2_.Q          	4
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
Fanin Node      	timer_11_.Q         	4
Fanin Node      	timer_10_.Q         	4
END

// Signal Name: timer_11_.C
// Type: Node_reg
BEGIN timer_11_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: timer_11_.AR
// Type: Node_reg
BEGIN timer_11_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: timer_10_.T
// Type: Node_reg
BEGIN timer_10_.T
Fanin Number		14
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	timer_9_.Q          	4
Fanin Node      	reg_sm_2_.Q         	3
Fanin Node      	timer_8_.Q          	4
Fanin Node      	timer_7_.Q          	4
Fanin Node      	timer_6_.Q          	4
Fanin Node      	timer_5_.Q          	4
Fanin Node      	timer_4_.Q          	4
Fanin Node      	timer_3_.Q          	5
Fanin Node      	timer_2_.Q          	4
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
Fanin Node      	timer_10_.Q         	4
END

// Signal Name: timer_10_.C
// Type: Node_reg
BEGIN timer_10_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: timer_10_.AR
// Type: Node_reg
BEGIN timer_10_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: nx2606
// Type: Node
BEGIN nx2606
Fanin Number		12
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	timer_9_.Q          	4
Fanin Node      	timer_8_.Q          	4
Fanin Node      	timer_7_.Q          	4
Fanin Node      	timer_6_.Q          	4
Fanin Node      	timer_5_.Q          	4
Fanin Node      	timer_4_.Q          	4
Fanin Node      	timer_3_.Q          	5
Fanin Node      	timer_2_.Q          	4
Fanin Node      	timer_1_.Q          	3
Fanin Node      	timer_0_.Q          	2
Fanin Node      	timer_11_.Q         	4
Fanin Node      	timer_10_.Q         	4
END

// Signal Name: nx2616
// Type: Node
BEGIN nx2616
Fanin Number		12
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	reg_cdata_7_.Q      	5
Fanin Node      	reg_cdata_6_.Q      	5
Fanin Node      	reg_cdata_5_.Q      	5
Fanin Node      	reg_cdata_4_.Q      	5
Fanin Node      	reg_cdata_3_.Q      	7
Fanin Node      	reg_cdata_2_.Q      	5
Fanin Node      	reg_cdata_1_.Q      	5
Fanin Node      	reg_cdata_0_.Q      	4
Fanin Node      	reg_cdata_9_.Q      	5
Fanin Node      	reg_cdata_8_.Q      	5
Fanin Node      	reg_cdata_11_.Q     	8
Fanin Node      	reg_cdata_10_.Q     	7
END

// Signal Name: reg_i_data_31__0
// Type: Node
BEGIN reg_i_data_31__0
Fanin Number		3
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	reg_sm_1_.Q         	3
Fanin Node      	reg_sm_0_.Q         	9
Fanin Node      	reg_sm_2_.Q         	3
END

// Design 'top_ni' used clock signal list:
CLOCK	clk