[DEVICE]
Family = lc4k;
PartType = LC4256V;
Package = 100TQFP;
PartNumber = LC4256V-3T100C;
Speed = -3;
Operating_condition = COM;
EN_Segment = Yes;
Pin_MC_1to1 = No;
Default_Device_Io_Types = LVCMOS18, -;
Voltage = 3.3;

[REVISION]
RCS = "$Header $";
Parent = lc4k256v.lci;
Design = ;
DATE = 08/11/2006;
TIME = 14:00:38;
Source_Format = EDIF;
Type = ;
Pre_Fit_Time = ;

[IGNORE ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;
IO_Types = No;

[CLEAR ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;
IO_Types = No;

[BACKANNOTATE ASSIGNMENTS]
Pin_Assignment = Yes;
Pin_Block = No;
Pin_Macrocell_Block = No;
Routing = No;
Io_Types = No;

[GLOBAL CONSTRAINTS]
Max_Fanin = 24;
Max_PTerm_Split = 80;
Max_PTerm_Collapse = 16;
Max_Pin_Percent = 100;
Max_Macrocell_Percent = 100;
Max_GLB_Input_Percent = 100;
Logic_Reduction = Yes;
XOR_Synthesis = Yes;
Keep_XOR = No;
DT_Synthesis = Yes;
Node_Collapse = Yes;
Nodes_collapsing_mode = FMAX;
Fmax_Logic_Level = 1;
Use_CE = Yes;
Use_Internal_COM_FB = Yes;
Set_Reset_Swap = No;
Clock_Optimize = No;
EN_Set_Reset_Dont_Care = No;
TOE_AS_IO = No;
Set_Reset_Dont_Care = No;
EN_In_Reg_Optimize = No;
In_Reg_Optimize = Yes;
Run_Time = 0;
Routing_Attempts = 2;
Balanced_Partitioning = Yes;
Spread_Placement = Yes;
Usercode = ;
Usercode_Format = HEX;
Vcc = ;
Dual_Function_Macrocell = 1;
Global_PTOE = Yes;
Hard_Fast_Bypass = No;
Fitter_Effort_Level = LOW;
Auto_buffering_for_high_glb_fanin = Off;
Auto_buffering_for_low_bonded_io = Off;
User_max_glb_fanin = 36;
Adjust_input_assignments = Off;

[LOCATION ASSIGNMENTS]
layer = OFF;
reg_cdata_13_ = node, -, -, A, 5;
reg_cdata_3_ = node, -, -, A, 2;
nx1988 = node, -, -, A, 10;
reset_n = pin, 100, -, B, 12;
SCL = pin, 98, -, B, 6;
SDA = pin, 97, -, B, 3;
reg_cdata_11_ = node, -, -, B, 9;
reg_cdata_6_ = node, -, -, B, 1;
SD2ANL = pin, 3, -, C, 0;
reg_sm_1_ = node, -, -, C, 1;
timer_14_ = node, -, -, C, 2;
timer_13_ = node, -, -, C, 3;
timer_12_ = node, -, -, C, 5;
timer_11_ = node, -, -, C, 7;
timer_10_ = node, -, -, C, 9;
nx1854 = node, -, -, C, 12;
reg_dis_next = node, -, -, D, 9;
reg_i_data_4_ = node, -, -, D, 1;
reg_i_data_3_ = node, -, -, D, 3;
reg_i_data_2_ = node, -, -, D, 5;
reg_i_data_1_ = node, -, -, D, 7;
reg_i_data_0_ = node, -, -, D, 12;
reg_sm_0_ = node, -, -, E, 5;
reg_cdata_7_ = node, -, -, E, 2;
reg_cdata_1_ = node, -, -, E, 10;
jTDO = pin, 21, -, F, 1;
reg_cdata_5_ = node, -, -, F, 3;
reg_cdata_2_ = node, -, -, F, 6;
reg_cdata_0_ = node, -, -, F, 9;
reg_sm_2_ = node, -, -, G, 10;
reg_cdata_10_ = node, -, -, G, 2;
reg_cdata_4_ = node, -, -, G, 5;
reg_cdata_14_ = node, -, -, H, 3;
reg_cdata_8_ = node, -, -, H, 7;
TESTEN = pin, 44, -, I, 1;
timer_9_ = node, -, -, I, 5;
timer_7_ = node, -, -, I, 7;
timer_5_ = node, -, -, I, 11;
timer_3_ = node, -, -, I, 3;
PRBSEN = pin, 47, -, J, 2;
LCKREFN = pin, 48, -, J, 7;
ENABLE = pin, 49, -, J, 0;
TX_ER = pin, 50, -, J, 1;
reg_start_s = node, -, -, J, 12;
timer_8_ = node, -, -, J, 3;
timer_6_ = node, -, -, J, 4;
timer_4_ = node, -, -, J, 5;
timer_2_ = node, -, -, J, 9;
TXD_14_ = pin, 56, -, K, 2;
LOOPEN = pin, 53, -, K, 1;
TXD_15_ = pin, 55, -, K, 7;
TX_EN = pin, 54, -, K, 0;
reg_cdata_12_ = node, -, -, K, 3;
reg_cdata_9_ = node, -, -, K, 5;
timer_1_ = node, -, -, K, 9;
nx1934 = node, -, -, K, 12;
TXD_13_ = pin, 58, -, L, 3;
TXD_12_ = pin, 59, -, L, 1;
TXD_11_ = pin, 60, -, L, 6;
TXD_10_ = pin, 61, -, L, 9;
clk = pin, 66, -, M, 10;
TXD_9_ = pin, 64, -, M, 5;
TXD_8_ = pin, 65, -, M, 8;
TXD_7_ = pin, 67, -, M, 2;
TXD_6_ = pin, 69, -, N, 3;
TXD_5_ = pin, 70, -, N, 6;
TXD_4_ = pin, 71, -, N, 11;
TXD_3_ = pin, 72, -, N, 1;
TXD_2_ = pin, 78, -, O, 2;
TXD_1_ = pin, 79, -, O, 11;
TXD_0_ = pin, 80, -, O, 7;
EN = pin, 84, -, P, 3;
timer_0_ = node, -, -, P, 9;
start = pin, 89, -, -, -;
Reserved_Pin_98 = pin, 38, -, -, -;
Reserved_Pin_86 = pin, 88, -, -, -;

[PTOE ASSIGNMENTS]

[FAST BYPASS]
Default = NONE;
BYPASS = ;

[ORP BYPASS]
default = NONE;

[INPUT REGISTERS]
Default = NONE;

[IO TYPES]
reset_n = LVCMOS33, pin, -, -;
start = LVCMOS33, pin, -, -;
clk = LVCMOS33, pin, -, -;
TESTEN = LVCMOS33, pin, 1, -;
TXD_14_ = LVCMOS33, pin, 1, -;
PRBSEN = LVCMOS33, pin, 1, -;
TXD_13_ = LVCMOS33, pin, 1, -;
LCKREFN = LVCMOS33, pin, 1, -;
ENABLE = LVCMOS33, pin, 1, -;
LOOPEN = LVCMOS33, pin, 1, -;
TX_ER = LVCMOS33, pin, 1, -;
TXD_15_ = LVCMOS33, pin, 1, -;
EN = LVCMOS33, pin, 1, -;
SD2ANL = LVCMOS33, pin, 0, -;
SCL = LVCMOS33, pin, 0, -;
SDA = LVCMOS33, pin, 0, -;
jTDO = LVCMOS33, pin, 0, -;
TXD_12_ = LVCMOS33, pin, 1, -;
TXD_11_ = LVCMOS33, pin, 1, -;
TXD_10_ = LVCMOS33, pin, 1, -;
TXD_9_ = LVCMOS33, pin, 1, -;
TX_EN = LVCMOS33, pin, 1, -;
TXD_8_ = LVCMOS33, pin, 1, -;
TXD_7_ = LVCMOS33, pin, 1, -;
TXD_6_ = LVCMOS33, pin, 1, -;
TXD_5_ = LVCMOS33, pin, 1, -;
TXD_4_ = LVCMOS33, pin, 1, -;
TXD_3_ = LVCMOS33, pin, 1, -;
TXD_2_ = LVCMOS33, pin, 1, -;
TXD_1_ = LVCMOS33, pin, 1, -;
TXD_0_ = LVCMOS33, pin, 1, -;

[PLL ASSIGNMENTS]

[RESOURCE RESERVATIONS]
layer = OFF;
PIN = 5, Input;
PIN = 81, Input;
PIN = 87, Input;
PIN = 88, Input;
PIN = 6, Input;
PIN = 8, Input;
PIN = 9, Input;
PIN = 10, Input;
PIN = 11, Input;
PIN = 14, Input;
PIN = 15, Input;
PIN = 16, Input;
PIN = 17, Input;
PIN = 19, Input;
PIN = 20, Input;
PIN = 38, Input;
PIN = 99, Input;

[SLEWRATE]
SLOW = LOOPEN, PRBSEN, TESTEN, TX_ER, EN, ENABLE, LCKREFN, jTDO, SCL, SDA, SD2ANL;
Default = FAST;

[PULLUP]
Default = UP;

[FITTER RESULTS]
I/O_pin_util = 68;
I/O_pin = 44;
Logic_PT_util = 22;
Logic_PT = 286;
Occupied_MC_util = 37;
Occupied_MC = 97;
Occupied_PT_util = 35;
Occupied_PT = 465;
GLB_input_util = 48;
GLB_input = 279;

[TIMING CONSTRAINTS]
layer = OFF;
fMAX_0 = 8.0000, clk, clk;

[FITTER REPORT FORMAT]
Fitter_Options = Yes;
Pinout_Diagram = No;
Pinout_Listing = Yes;
Detailed_Block_Segment_Summary = Yes;
Input_Signal_List = Yes;
Output_Signal_List = Yes;
Bidir_Signal_List = Yes;
Node_Signal_List = Yes;
Signal_Fanout_List = Yes;
Block_Segment_Fanin_List = Yes;
Postfit_Eqn = Yes;
Page_Break = Yes;
Detailed = No;

[POWER]
Default = HIGH;

[SOURCE_CONSTRAINT_OPTION]

[HARDWARE DEVICE OPTIONS]
Zero_Hold_Time = No;
Signature_Word = ;
Pullup = No;
Slew_Rate = FAST;

[TIMING ANALYZER]
Last_source = ;
Last_source_type = Fmax;

[opt global constraints list]

[Explorer User Settings]

[LOCATION ASSIGNMENTS LIST]

[GROUP ASSIGNMENTS]

[RESOURCE RESERVATIONS LIST]

[Pin attributes list]

[individual constraints list]

[Attributes list setting]

[Source Constraint Option]

[NETLIST/DELAY FORMAT]

[OSM Bypass]

[Register Powerup]

[global constraints list]

[Global Constraints Process Update]

[Explorer Results]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[Timing Results]
Fmax = 168.07;
Logic_level = 2;