[Device]
Family = lc4k;
PartNumber = LC4256V-3T100C;
Package = 100TQFP;
PartType = LC4256V;
Speed = -3;
Operating_condition = COM;
Status = Production;
EN_PinGLB = No;
EN_PinMacrocell = No;

[Revision]
Parent = lc4k256v.lci;
DATE = 05/17/2006;
TIME = 12:16:20;
Synthesis = Exemplar;
Source_Format = EDIF;

[Ignore Assignments]
Pin_Assignments = NO;
Pin_Keep_Block = NO;
Pin_Keep_Segment = NO;
Group_Assignments = NO;
Macrocell_Assignments = NO;
Macrocell_Keep_Block = NO;
Macrocell_Keep_Segment = NO;
Pin_Reservation = NO;
Timing_Constraints = NO;
IO_Types = NO;
All_Device_Constraints = NO;
Region = NO;

[Clear Assignments]

[Backannotate Assignments]
Pin_Block = NO;
Pin_Macrocell_Block = NO;
Pin_Assignments = YES;
IO_Types = NO;

[Global Constraints]

[Location Assignments]
layer = OFF;
reset_n = pin, 100, -, B, *;
DIS_JTG = pin, 99, -, B, *;
SCL = pin, 98, -, B, *;
SDA = pin, 97, -, B, *;
NI_STR = pin, 6, -, C, *;
SD2ANL = pin, 3, -, C, *;
NI_D_9_ = pin, 8, -, D, *;
NI_D_8_ = pin, 9, -, D, *;
NI_D_7_ = pin, 10, -, D, *;
NI_D_6_ = pin, 11, -, D, *;
NI_D_5_ = pin, 14, -, E, *;
NI_D_4_ = pin, 15, -, E, *;
NI_D_3_ = pin, 16, -, E, *;
NI_D_2_ = pin, 17, -, E, *;
NI_D_1_ = pin, 19, -, F, *;
NI_D_0_ = pin, 20, -, F, *;
jTDO = pin, 21, -, F, *;
TESTEN = pin, 44, -, I, *;
PRBSEN = pin, 47, -, J, *;
LCKREFN = pin, 48, -, J, *;
ENABLE = pin, 49, -, J, *;
TX_ER = pin, 50, -, J, *;
LOOPEN = pin, 53, -, K, *;
TX_EN = pin, 54, -, K, *;
TXD_15_ = pin, 55, -, K, *;
TXD_14_ = pin, 56, -, K, *;
TXD_13_ = pin, 58, -, L, *;
TXD_12_ = pin, 59, -, L, *;
TXD_11_ = pin, 60, -, L, *;
TXD_10_ = pin, 61, -, L, *;
clk = pin, 66, -, M, *;
TXD_9_ = pin, 64, -, M, *;
TXD_8_ = pin, 65, -, M, *;
TXD_7_ = pin, 67, -, M, *;
TXD_6_ = pin, 69, -, N, *;
TXD_5_ = pin, 70, -, N, *;
TXD_4_ = pin, 71, -, N, *;
TXD_3_ = pin, 72, -, N, *;
FAULT = pin, 81, -, O, *;
TXD_2_ = pin, 78, -, O, *;
TXD_1_ = pin, 79, -, O, *;
TXD_0_ = pin, 80, -, O, *;
jTMS = pin, 87, -, P, *;
EN = pin, 84, -, P, *;
jTCK = pin, 38, -, -, *;
jTDI = pin, 88, -, -, *;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;
PIN = 5, Input;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]

[IO Types]
layer = OFF;
NI_D_9_ = LVCMOS33, pin, -, -;
NI_STR = LVCMOS33, pin, -, -;
reset_n = LVCMOS33, pin, -, -;
clk = LVCMOS33, pin, -, -;
DIS_JTG = LVCMOS33, pin, -, -;
FAULT = LVCMOS33, pin, -, -;
NI_D_8_ = LVCMOS33, pin, -, -;
NI_D_7_ = LVCMOS33, pin, -, -;
NI_D_6_ = LVCMOS33, pin, -, -;
NI_D_5_ = LVCMOS33, pin, -, -;
jTCK = LVCMOS33, pin, -, -;
NI_D_4_ = LVCMOS33, pin, -, -;
jTDI = LVCMOS33, pin, -, -;
NI_D_3_ = LVCMOS33, pin, -, -;
NI_D_2_ = LVCMOS33, pin, -, -;
jTMS = LVCMOS33, pin, -, -;
NI_D_1_ = LVCMOS33, pin, -, -;
NI_D_0_ = LVCMOS33, pin, -, -;
TESTEN = LVCMOS33, pin, 1, -;
PRBSEN = LVCMOS33, pin, 1, -;
LCKREFN = LVCMOS33, pin, 1, -;
ENABLE = LVCMOS33, pin, 1, -;
LOOPEN = LVCMOS33, pin, 1, -;
TX_ER = LVCMOS33, pin, 1, -;
EN = LVCMOS33, pin, 1, -;
SD2ANL = LVCMOS33, pin, 0, -;
SCL = LVCMOS33, pin, 0, -;
SDA = LVCMOS33, pin, 0, -;
jTDO = LVCMOS33, pin, 0, -;
TX_EN = LVCMOS33, pin, 1, -;
TXD_15_ = LVCMOS33, pin, 1, -;
TXD_14_ = LVCMOS33, pin, 1, -;
TXD_13_ = LVCMOS33, pin, 1, -;
TXD_12_ = LVCMOS33, pin, 1, -;
TXD_11_ = LVCMOS33, pin, 1, -;
TXD_10_ = LVCMOS33, pin, 1, -;
TXD_9_ = LVCMOS33, pin, 1, -;
TXD_8_ = LVCMOS33, pin, 1, -;
TXD_7_ = LVCMOS33, pin, 1, -;
TXD_6_ = LVCMOS33, pin, 1, -;
TXD_5_ = LVCMOS33, pin, 1, -;
TXD_4_ = LVCMOS33, pin, 1, -;
TXD_3_ = LVCMOS33, pin, 1, -;
TXD_2_ = LVCMOS33, pin, 1, -;
TXD_1_ = LVCMOS33, pin, 1, -;
TXD_0_ = LVCMOS33, pin, 1, -;

[Pullup]

[Slewrate]
SLOW = LED_5_, LED_6_, LED_7_, LED_8_, LED_9_, LED_10_, LOOPEN, PRBSEN, TESTEN, 
	TX_ER, EN, ENABLE, LCKREFN, jTDO, SCL, SDA, SD2ANL;

[Region]

[Timing Constraints]
layer = OFF;
fMAX_0 = 7.6923, clk, clk;
fMAX_1 = 7.6923, NI_STR, NI_STR;
fMAX_2 = 1000.0000, jTCK, jTCK;

[HSI Attributes]

[Input Delay]

[opt global constraints list]

[Explorer User Settings]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[Pin attributes list]

[individual constraints list]

[Attributes list setting]

[Timing Analyzer]

[PLL Assignments]

[Register Powerup]
RESET = j2c_reg_creg0i_1_, j2c_reg_creg0i_2_, j2c_reg_creg0i_4_, j2c_reg_creg0i_5_, 
	j2c_reg_creg0i_6_;
SET = j2c_reg_creg0i_7_, j2c_reg_creg0i_0_, j2c_reg_creg0i_3_;

[global constraints list]

[Global Constraints Process Update]

[Explorer Results]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[Constraint Version]
version = 1.0;

[Node attribute]
layer = OFF;

[SYMBOL/MODULE attribute]
layer = OFF;

[Nodal Constraints]
layer = OFF;

[ORP Bypass]