|--------------------------------------------------- ----------| |- ispLEVER 5.0.01.73.31.05_Starter Equations File -| |- Copyright(C), 1992-2001, Lattice Semiconductor Corporation -| |- All Rights Reserved. -| |--------------------------------------------------------------| Equations: EN = 1 ; (1 pterm, 0 signal) ENABLE = 1 ; (1 pterm, 0 signal) LCKREFN = 0 ; (0 pterm, 0 signal) LOOPEN = 0 ; (0 pterm, 0 signal) PRBSEN = 0 ; (0 pterm, 0 signal) SCL = 0 ; (0 pterm, 0 signal) SCL.OE = 0 ; (0 pterm, 0 signal) SD2ANL = 1 ; (1 pterm, 0 signal) SDA = 0 ; (0 pterm, 0 signal) SDA.OE = 0 ; (0 pterm, 0 signal) TESTEN = 0 ; (0 pterm, 0 signal) TXD_0_.D = !TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # !TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q ; (2 pterms, 4 signals) TXD_0_.C = clk ; (1 pterm, 1 signal) TXD_0_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_0_.AR = !reset_n ; (1 pterm, 1 signal) TXD_10_.T = TXD_9_.Q & TXD_8_.Q & TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_9_.Q & TXD_8_.Q & TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_10_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # TXD_10_.Q & reg_sm_1_.Q # TXD_10_.Q & reg_sm_2_.Q & reg_sm_0_.Q ; (5 pterms, 14 signals) TXD_10_.C = clk ; (1 pterm, 1 signal) TXD_10_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_10_.AR = !reset_n ; (1 pterm, 1 signal) TXD_11_.T = TXD_10_.Q & TXD_9_.Q & TXD_8_.Q & TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_10_.Q & TXD_9_.Q & TXD_8_.Q & TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # !TXD_11_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # !TXD_11_.Q & reg_sm_1_.Q & !reg_sm_0_.Q # TXD_11_.Q & reg_sm_2_.Q & reg_sm_0_.Q # TXD_11_.Q & reg_sm_1_.Q & reg_sm_0_.Q ; (6 pterms, 15 signals) TXD_11_.C = clk ; (1 pterm, 1 signal) TXD_11_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_11_.AR = !reset_n ; (1 pterm, 1 signal) TXD_12_.D = !( !reg_sm_1_.Q & reg_sm_2_.Q & reg_sm_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q ) ; (2 pterms, 3 signals) TXD_12_.C = clk ; (1 pterm, 1 signal) TXD_12_.AR = !reset_n ; (1 pterm, 1 signal) TXD_13_.D = reg_sm_1_.Q & !reg_sm_0_.Q ; (1 pterm, 2 signals) TXD_13_.C = clk ; (1 pterm, 1 signal) TXD_13_.AR = !reset_n ; (1 pterm, 1 signal) TXD_14_ = 0 ; (0 pterm, 0 signal) TXD_15_.D = reg_sm_1_.Q & !reg_sm_0_.Q ; (1 pterm, 2 signals) TXD_15_.C = clk ; (1 pterm, 1 signal) TXD_15_.AR = !reset_n ; (1 pterm, 1 signal) TXD_1_.D = TXD_1_.Q & !TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # !TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_1_.Q & !TXD_0_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # !TXD_1_.Q & TXD_0_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q ; (5 pterms, 5 signals) TXD_1_.C = clk ; (1 pterm, 1 signal) TXD_1_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_1_.AR = !reset_n ; (1 pterm, 1 signal) TXD_2_.T = TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_2_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # TXD_2_.Q & reg_sm_1_.Q # TXD_2_.Q & reg_sm_2_.Q & reg_sm_0_.Q ; (5 pterms, 6 signals) TXD_2_.C = clk ; (1 pterm, 1 signal) TXD_2_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_2_.AR = !reset_n ; (1 pterm, 1 signal) TXD_3_.D = !( TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q # !TXD_3_.Q & !TXD_0_.Q & !reg_sm_1_.Q # !TXD_3_.Q & !TXD_1_.Q & !reg_sm_1_.Q # !TXD_3_.Q & !TXD_2_.Q & !reg_sm_1_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_2_.Q & reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q ) ; (7 pterms, 7 signals) TXD_3_.C = clk ; (1 pterm, 1 signal) TXD_3_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_3_.AR = !reset_n ; (1 pterm, 1 signal) TXD_4_.T = TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_4_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # TXD_4_.Q & reg_sm_1_.Q # TXD_4_.Q & reg_sm_2_.Q & reg_sm_0_.Q ; (5 pterms, 8 signals) TXD_4_.C = clk ; (1 pterm, 1 signal) TXD_4_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_4_.AR = !reset_n ; (1 pterm, 1 signal) TXD_5_.D = !( TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q # !TXD_5_.Q & !TXD_0_.Q & !reg_sm_1_.Q # !TXD_5_.Q & !TXD_1_.Q & !reg_sm_1_.Q # !TXD_5_.Q & !TXD_2_.Q & !reg_sm_1_.Q # !TXD_5_.Q & !TXD_3_.Q & !reg_sm_1_.Q # !TXD_5_.Q & !TXD_4_.Q & !reg_sm_1_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_2_.Q & reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q ) ; (9 pterms, 9 signals) TXD_5_.C = clk ; (1 pterm, 1 signal) TXD_5_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_5_.AR = !reset_n ; (1 pterm, 1 signal) TXD_6_.T = TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_6_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # TXD_6_.Q & reg_sm_1_.Q # TXD_6_.Q & reg_sm_2_.Q & reg_sm_0_.Q ; (5 pterms, 10 signals) TXD_6_.C = clk ; (1 pterm, 1 signal) TXD_6_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_6_.AR = !reset_n ; (1 pterm, 1 signal) TXD_7_.T = TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_7_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # !TXD_7_.Q & reg_sm_1_.Q & !reg_sm_0_.Q # TXD_7_.Q & reg_sm_2_.Q & reg_sm_0_.Q # TXD_7_.Q & reg_sm_1_.Q & reg_sm_0_.Q ; (6 pterms, 11 signals) TXD_7_.C = clk ; (1 pterm, 1 signal) TXD_7_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_7_.AR = !reset_n ; (1 pterm, 1 signal) TXD_8_.T = TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # TXD_8_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # TXD_8_.Q & reg_sm_1_.Q # TXD_8_.Q & reg_sm_2_.Q & reg_sm_0_.Q ; (5 pterms, 12 signals) TXD_8_.C = clk ; (1 pterm, 1 signal) TXD_8_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_8_.AR = !reset_n ; (1 pterm, 1 signal) TXD_9_.T = TXD_8_.Q & TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q # TXD_8_.Q & TXD_7_.Q & TXD_6_.Q & TXD_5_.Q & TXD_4_.Q & TXD_3_.Q & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q # !TXD_9_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # !TXD_9_.Q & reg_sm_1_.Q & !reg_sm_0_.Q # TXD_9_.Q & reg_sm_2_.Q & reg_sm_0_.Q # TXD_9_.Q & reg_sm_1_.Q & reg_sm_0_.Q ; (6 pterms, 13 signals) TXD_9_.C = clk ; (1 pterm, 1 signal) TXD_9_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) TXD_9_.AR = !reset_n ; (1 pterm, 1 signal) TX_EN.D = !( !reg_cdata_14_.Q & !reg_sm_2_.Q & reg_sm_0_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # !reg_sm_1_.Q & !reg_sm_0_.Q & reg_dis_next.Q # reg_sm_1_.Q & reg_sm_0_.Q ) ; (5 pterms, 19 signals) TX_EN.C = clk ; (1 pterm, 1 signal) TX_EN.AR = !reset_n ; (1 pterm, 1 signal) TX_ER = 0 ; (0 pterm, 0 signal) jTDO = 0 ; (0 pterm, 0 signal) jTDO.OE = 0 ; (0 pterm, 0 signal) nx1854 = !timer_14_.Q & !timer_13_.Q & !timer_12_.Q & !timer_11_.Q & !timer_10_.Q & !timer_9_.Q & timer_8_.Q & !timer_7_.Q & !timer_6_.Q & !timer_5_.Q & !timer_4_.Q & !timer_3_.Q & !timer_2_.Q & timer_1_.Q & !timer_0_.Q ; (1 pterm, 15 signals) nx1934 = reg_cdata_14_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q ; (1 pterm, 15 signals) nx1988 = !reg_cdata_14_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q ; (1 pterm, 15 signals) reg_cdata_0_.D = !( !reg_cdata_14_.Q & !reg_sm_2_.Q & reg_sm_0_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q # reg_cdata_0_.Q ) ; (5 pterms, 18 signals) reg_cdata_0_.C = clk ; (1 pterm, 1 signal) reg_cdata_0_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_0_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_10_.T = reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_10_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_10_.Q ; (6 pterms, 18 signals) reg_cdata_10_.C = clk ; (1 pterm, 1 signal) reg_cdata_10_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_10_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_11_.T = reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_11_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_11_.Q ; (6 pterms, 18 signals) reg_cdata_11_.C = clk ; (1 pterm, 1 signal) reg_cdata_11_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_11_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_12_.T = !reg_sm_1_.Q & reg_sm_2_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_12_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_12_.Q ; (5 pterms, 16 signals) reg_cdata_12_.C = clk ; (1 pterm, 1 signal) reg_cdata_12_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_12_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_13_.T = reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_13_.Q ; (6 pterms, 18 signals) reg_cdata_13_.C = clk ; (1 pterm, 1 signal) reg_cdata_13_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_13_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_14_.T = reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_13_.Q & reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & reg_cdata_9_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_cdata_14_.Q & reg_sm_0_.Q ; (6 pterms, 18 signals) reg_cdata_14_.C = clk ; (1 pterm, 1 signal) reg_cdata_14_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_14_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_1_.D = !( !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q # !reg_cdata_1_.Q & !reg_cdata_0_.Q # reg_cdata_1_.Q & reg_cdata_0_.Q ) ; (4 pterms, 5 signals) reg_cdata_1_.C = clk ; (1 pterm, 1 signal) reg_cdata_1_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_1_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_2_.D = !( !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q # !reg_cdata_2_.Q & !reg_cdata_1_.Q # !reg_cdata_2_.Q & !reg_cdata_0_.Q ) ; (5 pterms, 6 signals) reg_cdata_2_.C = clk ; (1 pterm, 1 signal) reg_cdata_2_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_2_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_3_.D = !( !reg_cdata_14_.Q & !reg_sm_2_.Q & reg_sm_0_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q # !reg_cdata_3_.Q & !reg_cdata_1_.Q # !reg_cdata_3_.Q & !reg_cdata_2_.Q # !reg_cdata_3_.Q & !reg_cdata_0_.Q ) ; (7 pterms, 18 signals) reg_cdata_3_.C = clk ; (1 pterm, 1 signal) reg_cdata_3_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_3_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_4_.T = !reg_sm_1_.Q & reg_sm_2_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_4_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_4_.Q ; (5 pterms, 8 signals) reg_cdata_4_.C = clk ; (1 pterm, 1 signal) reg_cdata_4_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_4_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_5_.D = !( !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q # !reg_cdata_5_.Q & !reg_cdata_1_.Q # !reg_cdata_5_.Q & !reg_cdata_2_.Q # !reg_cdata_5_.Q & !reg_cdata_3_.Q # !reg_cdata_5_.Q & !reg_cdata_4_.Q # !reg_cdata_5_.Q & !reg_cdata_0_.Q ) ; (9 pterms, 18 signals) reg_cdata_5_.C = clk ; (1 pterm, 1 signal) reg_cdata_5_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_5_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_6_.D = !( !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q # !reg_cdata_6_.Q & !reg_cdata_5_.Q # !reg_cdata_6_.Q & !reg_cdata_1_.Q # !reg_cdata_6_.Q & !reg_cdata_2_.Q # !reg_cdata_6_.Q & !reg_cdata_3_.Q # !reg_cdata_6_.Q & !reg_cdata_4_.Q # !reg_cdata_6_.Q & !reg_cdata_0_.Q ) ; (10 pterms, 18 signals) reg_cdata_6_.C = clk ; (1 pterm, 1 signal) reg_cdata_6_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_6_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_7_.T = !reg_sm_1_.Q & reg_sm_2_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_7_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_7_.Q ; (5 pterms, 11 signals) reg_cdata_7_.C = clk ; (1 pterm, 1 signal) reg_cdata_7_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_7_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_8_.T = reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_cdata_14_.Q & !reg_sm_0_.Q & reg_cdata_13_.Q & !reg_cdata_12_.Q & reg_cdata_11_.Q & reg_cdata_10_.Q & !reg_cdata_9_.Q & reg_cdata_8_.Q & !reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & !reg_cdata_1_.Q & !reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_8_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_8_.Q ; (6 pterms, 18 signals) reg_cdata_8_.C = clk ; (1 pterm, 1 signal) reg_cdata_8_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_8_.AR = !reset_n ; (1 pterm, 1 signal) reg_cdata_9_.T = reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_sm_0_.Q & reg_cdata_8_.Q & reg_cdata_7_.Q & reg_cdata_6_.Q & reg_cdata_5_.Q & reg_cdata_4_.Q & reg_cdata_3_.Q & reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & reg_cdata_9_.Q # reg_sm_1_.Q & reg_sm_0_.Q & reg_cdata_9_.Q ; (5 pterms, 13 signals) reg_cdata_9_.C = clk ; (1 pterm, 1 signal) reg_cdata_9_.CE = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & reg_dis_next.Q ) ; (1 pterm, 4 signals) reg_cdata_9_.AR = !reset_n ; (1 pterm, 1 signal) reg_dis_next.D = !reg_i_data_4_.Q & !reg_i_data_3_.Q & !reg_i_data_2_.Q & !reg_i_data_1_.Q & !reg_i_data_0_.Q ; (1 pterm, 5 signals) reg_dis_next.C = clk ; (1 pterm, 1 signal) reg_dis_next.AR = !reset_n ; (1 pterm, 1 signal) reg_i_data_0_.D = !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_0_.Q ; (1 pterm, 5 signals) reg_i_data_0_.C = clk ; (1 pterm, 1 signal) reg_i_data_0_.AR = !reset_n ; (1 pterm, 1 signal) reg_i_data_1_.D = !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_1_.Q & !reg_i_data_0_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & reg_i_data_1_.Q & reg_i_data_0_.Q ; (2 pterms, 6 signals) reg_i_data_1_.C = clk ; (1 pterm, 1 signal) reg_i_data_1_.AR = !reset_n ; (1 pterm, 1 signal) reg_i_data_2_.D = !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_2_.Q & !reg_i_data_1_.Q & !reg_i_data_0_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & reg_i_data_2_.Q & reg_i_data_1_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & reg_i_data_2_.Q & reg_i_data_0_.Q ; (3 pterms, 7 signals) reg_i_data_2_.C = clk ; (1 pterm, 1 signal) reg_i_data_2_.AR = !reset_n ; (1 pterm, 1 signal) reg_i_data_3_.D = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & reg_i_data_3_.Q & !reg_i_data_2_.Q & !reg_i_data_1_.Q & !reg_i_data_0_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_3_.Q & reg_i_data_1_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_3_.Q & reg_i_data_2_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_3_.Q & reg_i_data_0_.Q ) ; (4 pterms, 8 signals) reg_i_data_3_.C = clk ; (1 pterm, 1 signal) reg_i_data_3_.AR = !reset_n ; (1 pterm, 1 signal) reg_i_data_4_.D = !( !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & reg_i_data_4_.Q & !reg_i_data_3_.Q & !reg_i_data_2_.Q & !reg_i_data_1_.Q & !reg_i_data_0_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_4_.Q & reg_i_data_1_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_4_.Q & reg_i_data_2_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_4_.Q & reg_i_data_3_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & !reg_i_data_4_.Q & reg_i_data_0_.Q ) ; (5 pterms, 9 signals) reg_i_data_4_.C = clk ; (1 pterm, 1 signal) reg_i_data_4_.AR = !reset_n ; (1 pterm, 1 signal) reg_sm_0_.T = !reg_sm_1_.Q & !reg_cdata_14_.Q & reg_sm_2_.Q & reg_sm_0_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # reg_sm_1_.Q & !reg_cdata_14_.Q & !reg_sm_0_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q # !reg_sm_1_.Q & reg_sm_2_.Q & !reg_sm_0_.Q & !reg_dis_next.Q & nx1934 # !reg_sm_1_.Q & !reg_sm_2_.Q & reg_start_s.Q & !reg_sm_0_.Q # reg_sm_1_.Q & reg_sm_0_.Q & nx1854 # !reg_sm_1_.Q & !reg_sm_2_.Q & reg_sm_0_.Q & nx1988 ; (6 pterms, 23 signals) reg_sm_0_.C = clk ; (1 pterm, 1 signal) reg_sm_0_.AR = !reset_n ; (1 pterm, 1 signal) reg_sm_1_.D = !( reg_sm_1_.Q & reg_sm_0_.Q & !timer_14_.Q & !timer_13_.Q & !timer_12_.Q & !timer_11_.Q & !timer_10_.Q & !timer_9_.Q & timer_8_.Q & !timer_7_.Q & !timer_6_.Q & !timer_5_.Q & !timer_4_.Q & !timer_3_.Q & !timer_2_.Q & timer_1_.Q & !timer_0_.Q # !reg_sm_1_.Q & !reg_sm_0_.Q # !reg_sm_1_.Q & reg_sm_2_.Q # !reg_sm_1_.Q & !nx1988 ) ; (4 pterms, 19 signals) reg_sm_1_.C = clk ; (1 pterm, 1 signal) reg_sm_1_.AR = !reset_n ; (1 pterm, 1 signal) reg_sm_2_.D.X1 = !reg_sm_1_.Q & reg_sm_2_.Q # reg_sm_1_.Q & reg_start_s.Q & reg_sm_0_.Q & nx1854 ; (2 pterms, 5 signals) reg_sm_2_.D.X2 = !reg_sm_1_.Q & !reg_cdata_14_.Q & reg_sm_2_.Q & reg_sm_0_.Q & !reg_cdata_13_.Q & !reg_cdata_12_.Q & !reg_cdata_11_.Q & !reg_cdata_10_.Q & !reg_cdata_9_.Q & !reg_cdata_8_.Q & !reg_cdata_7_.Q & !reg_cdata_6_.Q & !reg_cdata_5_.Q & !reg_cdata_4_.Q & !reg_cdata_3_.Q & !reg_cdata_2_.Q & reg_cdata_1_.Q & reg_cdata_0_.Q ; (1 pterm, 18 signals) reg_sm_2_.C = clk ; (1 pterm, 1 signal) reg_sm_2_.AR = !reset_n ; (1 pterm, 1 signal) reg_start_s.D = start ; (1 pterm, 1 signal) reg_start_s.C = clk ; (1 pterm, 1 signal) reg_start_s.AR = !reset_n ; (1 pterm, 1 signal) timer_0_.D = !( !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # timer_0_.Q ) ; (2 pterms, 4 signals) timer_0_.C = clk ; (1 pterm, 1 signal) timer_0_.AR = !reset_n ; (1 pterm, 1 signal) timer_10_.T = reg_sm_0_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_10_.Q ; (4 pterms, 14 signals) timer_10_.C = clk ; (1 pterm, 1 signal) timer_10_.AR = !reset_n ; (1 pterm, 1 signal) timer_11_.T = reg_sm_0_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_11_.Q ; (4 pterms, 15 signals) timer_11_.C = clk ; (1 pterm, 1 signal) timer_11_.AR = !reset_n ; (1 pterm, 1 signal) timer_12_.T = reg_sm_0_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_12_.Q ; (4 pterms, 16 signals) timer_12_.C = clk ; (1 pterm, 1 signal) timer_12_.AR = !reset_n ; (1 pterm, 1 signal) timer_13_.T = reg_sm_0_.Q & timer_12_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_12_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_12_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_13_.Q ; (4 pterms, 17 signals) timer_13_.C = clk ; (1 pterm, 1 signal) timer_13_.AR = !reset_n ; (1 pterm, 1 signal) timer_14_.T = reg_sm_0_.Q & timer_13_.Q & timer_12_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_13_.Q & timer_12_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_13_.Q & timer_12_.Q & timer_11_.Q & timer_10_.Q & timer_9_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_14_.Q ; (4 pterms, 18 signals) timer_14_.C = clk ; (1 pterm, 1 signal) timer_14_.AR = !reset_n ; (1 pterm, 1 signal) timer_1_.D = !( !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # !timer_1_.Q & !timer_0_.Q # timer_1_.Q & timer_0_.Q ) ; (3 pterms, 5 signals) timer_1_.C = clk ; (1 pterm, 1 signal) timer_1_.AR = !reset_n ; (1 pterm, 1 signal) timer_2_.D = !( !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # timer_2_.Q & timer_1_.Q & timer_0_.Q # !timer_2_.Q & !timer_1_.Q # !timer_2_.Q & !timer_0_.Q ) ; (4 pterms, 6 signals) timer_2_.C = clk ; (1 pterm, 1 signal) timer_2_.AR = !reset_n ; (1 pterm, 1 signal) timer_3_.D = !( timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q # !timer_3_.Q & !timer_1_.Q # !timer_3_.Q & !timer_2_.Q # !timer_3_.Q & !timer_0_.Q ) ; (5 pterms, 7 signals) timer_3_.C = clk ; (1 pterm, 1 signal) timer_3_.AR = !reset_n ; (1 pterm, 1 signal) timer_4_.T = !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_4_.Q # reg_sm_0_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q ; (4 pterms, 8 signals) timer_4_.C = clk ; (1 pterm, 1 signal) timer_4_.AR = !reset_n ; (1 pterm, 1 signal) timer_5_.T = !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_5_.Q # reg_sm_0_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q ; (4 pterms, 9 signals) timer_5_.C = clk ; (1 pterm, 1 signal) timer_5_.AR = !reset_n ; (1 pterm, 1 signal) timer_6_.T = !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_6_.Q # reg_sm_0_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q ; (4 pterms, 10 signals) timer_6_.C = clk ; (1 pterm, 1 signal) timer_6_.AR = !reset_n ; (1 pterm, 1 signal) timer_7_.T = reg_sm_0_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_7_.Q ; (4 pterms, 11 signals) timer_7_.C = clk ; (1 pterm, 1 signal) timer_7_.AR = !reset_n ; (1 pterm, 1 signal) timer_8_.T = reg_sm_0_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_8_.Q ; (4 pterms, 12 signals) timer_8_.C = clk ; (1 pterm, 1 signal) timer_8_.AR = !reset_n ; (1 pterm, 1 signal) timer_9_.T = reg_sm_0_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_2_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # reg_sm_1_.Q & timer_8_.Q & timer_7_.Q & timer_6_.Q & timer_5_.Q & timer_4_.Q & timer_3_.Q & timer_2_.Q & timer_1_.Q & timer_0_.Q # !reg_sm_1_.Q & !reg_sm_2_.Q & !reg_sm_0_.Q & timer_9_.Q ; (4 pterms, 13 signals) timer_9_.C = clk ; (1 pterm, 1 signal) timer_9_.AR = !reset_n ; (1 pterm, 1 signal)