#$ TOOL  ispLEVER 5.0.01.73.31.05_Starter
#$ DATE  Wed Sep 27 18:33:05 2006
#$ MODULE  top_ni
#$ PINS 31 reset_n start clk TESTEN TXD_14_ PRBSEN TXD_13_ LCKREFN ENABLE
 LOOPEN TX_ER TXD_15_ EN SD2ANL SCL SDA jTDO TXD_12_ TXD_11_ TXD_10_ TXD_9_ TX_EN
 TXD_8_ TXD_7_ TXD_6_ TXD_5_ TXD_4_ TXD_3_ TXD_2_ TXD_1_ TXD_0_
#$ NODES 43 reg_sm_1_ reg_cdata_14_ reg_sm_2_ reg_start_s reg_sm_0_
 reg_cdata_13_ reg_cdata_12_ reg_cdata_11_ reg_cdata_10_ reg_cdata_9_
 reg_cdata_8_ reg_cdata_7_ reg_cdata_6_ reg_cdata_5_ reg_cdata_4_ reg_cdata_3_
 reg_cdata_2_ reg_cdata_1_ reg_cdata_0_ reg_dis_next reg_i_data_4_ reg_i_data_3_
 reg_i_data_2_ reg_i_data_1_ reg_i_data_0_ timer_14_ timer_13_ timer_12_
 timer_11_ timer_10_ timer_9_ timer_8_ timer_7_ timer_6_ timer_5_ timer_4_
 timer_3_ timer_2_ timer_1_ timer_0_ nx1854 nx1934 nx1988
.model top_ni 
.inputs reset_n.BLIF start.BLIF clk.BLIF TXD_11_.Q TXD_10_.Q TXD_9_.Q TXD_8_.Q \
 TXD_7_.Q TXD_6_.Q TXD_5_.Q TXD_4_.Q TXD_3_.Q TXD_2_.Q TXD_1_.Q TXD_0_.Q \
 reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_start_s.Q reg_sm_0_.Q \
 reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q \
 reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q \
 reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_dis_next.Q \
 reg_i_data_4_.Q reg_i_data_3_.Q reg_i_data_2_.Q reg_i_data_1_.Q reg_i_data_0_.Q \
 timer_14_.Q timer_13_.Q timer_12_.Q timer_11_.Q timer_10_.Q timer_9_.Q \
 timer_8_.Q timer_7_.Q timer_6_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q \
 timer_1_.Q timer_0_.Q nx1854.BLIF nx1934.BLIF nx1988.BLIF
.outputs TESTEN TXD_14_ PRBSEN TXD_13_.D TXD_13_.C TXD_13_.AR LCKREFN ENABLE \
 LOOPEN TX_ER TXD_15_.D TXD_15_.C TXD_15_.AR EN SD2ANL SCL SCL.OE SDA SDA.OE jTDO \
 jTDO.OE TXD_12_.D- TXD_12_.C TXD_12_.AR TXD_11_.T TXD_11_.C TXD_11_.CE- \
 TXD_11_.AR TXD_10_.T TXD_10_.C TXD_10_.CE- TXD_10_.AR TXD_9_.T TXD_9_.C \
 TXD_9_.CE- TXD_9_.AR TX_EN.D- TX_EN.C TX_EN.AR TXD_8_.T TXD_8_.C TXD_8_.CE- \
 TXD_8_.AR TXD_7_.T TXD_7_.C TXD_7_.CE- TXD_7_.AR TXD_6_.T TXD_6_.C TXD_6_.CE- \
 TXD_6_.AR TXD_5_.D- TXD_5_.C TXD_5_.CE- TXD_5_.AR TXD_4_.T TXD_4_.C TXD_4_.CE- \
 TXD_4_.AR TXD_3_.D- TXD_3_.C TXD_3_.CE- TXD_3_.AR TXD_2_.T TXD_2_.C TXD_2_.CE- \
 TXD_2_.AR TXD_1_.D TXD_1_.C TXD_1_.CE- TXD_1_.AR TXD_0_.D TXD_0_.C TXD_0_.CE- \
 TXD_0_.AR reg_sm_1_.D- reg_sm_1_.C reg_sm_1_.AR reg_cdata_14_.T reg_cdata_14_.C \
 reg_cdata_14_.CE- reg_cdata_14_.AR reg_sm_2_.D.X1 reg_sm_2_.D.X2 reg_sm_2_.C \
 reg_sm_2_.AR reg_start_s.D reg_start_s.C reg_start_s.AR reg_sm_0_.T reg_sm_0_.C \
 reg_sm_0_.AR reg_cdata_13_.T reg_cdata_13_.C reg_cdata_13_.CE- reg_cdata_13_.AR \
 reg_cdata_12_.T reg_cdata_12_.C reg_cdata_12_.CE- reg_cdata_12_.AR \
 reg_cdata_11_.T reg_cdata_11_.C reg_cdata_11_.CE- reg_cdata_11_.AR \
 reg_cdata_10_.T reg_cdata_10_.C reg_cdata_10_.CE- reg_cdata_10_.AR \
 reg_cdata_9_.T reg_cdata_9_.C reg_cdata_9_.CE- reg_cdata_9_.AR reg_cdata_8_.T \
 reg_cdata_8_.C reg_cdata_8_.CE- reg_cdata_8_.AR reg_cdata_7_.T reg_cdata_7_.C \
 reg_cdata_7_.CE- reg_cdata_7_.AR reg_cdata_6_.D- reg_cdata_6_.C reg_cdata_6_.CE- \
 reg_cdata_6_.AR reg_cdata_5_.D- reg_cdata_5_.C reg_cdata_5_.CE- reg_cdata_5_.AR \
 reg_cdata_4_.T reg_cdata_4_.C reg_cdata_4_.CE- reg_cdata_4_.AR reg_cdata_3_.D- \
 reg_cdata_3_.C reg_cdata_3_.CE- reg_cdata_3_.AR reg_cdata_2_.D- reg_cdata_2_.C \
 reg_cdata_2_.CE- reg_cdata_2_.AR reg_cdata_1_.D- reg_cdata_1_.C reg_cdata_1_.CE- \
 reg_cdata_1_.AR reg_cdata_0_.D- reg_cdata_0_.C reg_cdata_0_.CE- reg_cdata_0_.AR \
 reg_dis_next.D reg_dis_next.C reg_dis_next.AR reg_i_data_4_.D- reg_i_data_4_.C \
 reg_i_data_4_.AR reg_i_data_3_.D- reg_i_data_3_.C reg_i_data_3_.AR \
 reg_i_data_2_.D reg_i_data_2_.C reg_i_data_2_.AR reg_i_data_1_.D reg_i_data_1_.C \
 reg_i_data_1_.AR reg_i_data_0_.D reg_i_data_0_.C reg_i_data_0_.AR timer_14_.T \
 timer_14_.C timer_14_.AR timer_13_.T timer_13_.C timer_13_.AR timer_12_.T \
 timer_12_.C timer_12_.AR timer_11_.T timer_11_.C timer_11_.AR timer_10_.T \
 timer_10_.C timer_10_.AR timer_9_.T timer_9_.C timer_9_.AR timer_8_.T timer_8_.C \
 timer_8_.AR timer_7_.T timer_7_.C timer_7_.AR timer_6_.T timer_6_.C timer_6_.AR \
 timer_5_.T timer_5_.C timer_5_.AR timer_4_.T timer_4_.C timer_4_.AR timer_3_.D- \
 timer_3_.C timer_3_.AR timer_2_.D- timer_2_.C timer_2_.AR timer_1_.D- timer_1_.C \
 timer_1_.AR timer_0_.D- timer_0_.C timer_0_.AR nx1854 nx1934 nx1988
.names TESTEN
.names TXD_14_
.names PRBSEN
.names reg_sm_1_.Q reg_sm_0_.Q TXD_13_.D
10 1
.names clk.BLIF TXD_13_.C
1 1
.names reset_n.BLIF TXD_13_.AR
0 1
.names LCKREFN
.names ENABLE
 1
.names LOOPEN
.names TX_ER
.names reg_sm_1_.Q reg_sm_0_.Q TXD_15_.D
10 1
.names clk.BLIF TXD_15_.C
1 1
.names reset_n.BLIF TXD_15_.AR
0 1
.names EN
 1
.names SD2ANL
 1
.names SCL
.names SCL.OE
.names SDA
.names SDA.OE
.names jTDO
.names jTDO.OE
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_12_.D-
011 1
1-0 1
.names clk.BLIF TXD_12_.C
1 1
.names reset_n.BLIF TXD_12_.AR
0 1
.names TXD_11_.Q TXD_10_.Q TXD_9_.Q TXD_8_.Q TXD_7_.Q TXD_6_.Q TXD_5_.Q TXD_4_.Q TXD_3_.Q TXD_2_.Q TXD_1_.Q TXD_0_.Q reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_11_.T
-11111111111010 1
-11111111111001 1
0------------00 1
0-----------1-0 1
1------------11 1
1-----------1-1 1
.names clk.BLIF TXD_11_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q TXD_11_.CE-
0101 1
.names reset_n.BLIF TXD_11_.AR
0 1
.names TXD_10_.Q TXD_9_.Q TXD_8_.Q TXD_7_.Q TXD_6_.Q TXD_5_.Q TXD_4_.Q TXD_3_.Q TXD_2_.Q TXD_1_.Q TXD_0_.Q reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_10_.T
-1111111111010 1
-1111111111001 1
1-----------00 1
1----------1-- 1
1-----------11 1
.names clk.BLIF TXD_10_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q TXD_10_.CE-
0101 1
.names reset_n.BLIF TXD_10_.AR
0 1
.names TXD_9_.Q TXD_8_.Q TXD_7_.Q TXD_6_.Q TXD_5_.Q TXD_4_.Q TXD_3_.Q TXD_2_.Q TXD_1_.Q TXD_0_.Q reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_9_.T
-111111111010 1
-111111111001 1
0----------00 1
0---------1-0 1
1----------11 1
1---------1-1 1
.names clk.BLIF TXD_9_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q TXD_9_.CE-
0101 1
.names reset_n.BLIF TXD_9_.AR
0 1
.names reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_dis_next.Q TX_EN.D-
-00100000000001000- 1
01-010110101100000- 1
0-00--------------- 1
0--0--------------1 1
1--1--------------- 1
.names clk.BLIF TX_EN.C
1 1
.names reset_n.BLIF TX_EN.AR
0 1
.names TXD_8_.Q TXD_7_.Q TXD_6_.Q TXD_5_.Q TXD_4_.Q TXD_3_.Q TXD_2_.Q TXD_1_.Q TXD_0_.Q reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_8_.T
-11111111010 1
-11111111001 1
1---------00 1
1--------1-- 1
1---------11 1
.names clk.BLIF TXD_8_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q TXD_8_.CE-
0101 1
.names reset_n.BLIF TXD_8_.AR
0 1
.names TXD_7_.Q TXD_6_.Q TXD_5_.Q TXD_4_.Q TXD_3_.Q TXD_2_.Q TXD_1_.Q TXD_0_.Q reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_7_.T
-1111111010 1
-1111111001 1
1-------000 1
0-------1-0 1
1--------11 1
1-------1-1 1
.names clk.BLIF TXD_7_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q TXD_7_.CE-
0101 1
.names reset_n.BLIF TXD_7_.AR
0 1
.names TXD_6_.Q TXD_5_.Q TXD_4_.Q TXD_3_.Q TXD_2_.Q TXD_1_.Q TXD_0_.Q reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_6_.T
-111111010 1
-111111001 1
1-------00 1
1------1-- 1
1-------11 1
.names clk.BLIF TXD_6_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q TXD_6_.CE-
0101 1
.names reset_n.BLIF TXD_6_.AR
0 1
.names TXD_5_.Q TXD_4_.Q TXD_3_.Q TXD_2_.Q TXD_1_.Q TXD_0_.Q reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_5_.D-
1111110-- 1
0----00-- 1
0---0-0-- 1
0--0--0-- 1
0-0---0-- 1
00----0-- 1
------000 1
-------11 1
------1-1 1
.names clk.BLIF TXD_5_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q TXD_5_.CE-
0101 1
.names reset_n.BLIF TXD_5_.AR
0 1
.names TXD_4_.Q TXD_3_.Q TXD_2_.Q TXD_1_.Q TXD_0_.Q reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_4_.T
-1111010 1
-1111001 1
1-----00 1
1----1-- 1
1-----11 1
.names clk.BLIF TXD_4_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q TXD_4_.CE-
0101 1
.names reset_n.BLIF TXD_4_.AR
0 1
.names TXD_3_.Q TXD_2_.Q TXD_1_.Q TXD_0_.Q reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_3_.D-
11110-- 1
0--00-- 1
0-0-0-- 1
00--0-- 1
----000 1
-----11 1
----1-1 1
.names clk.BLIF TXD_3_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q TXD_3_.CE-
0101 1
.names reset_n.BLIF TXD_3_.AR
0 1
.names TXD_2_.Q TXD_1_.Q TXD_0_.Q reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_2_.T
-11010 1
-11001 1
1---00 1
1--1-- 1
1---11 1
.names clk.BLIF TXD_2_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q TXD_2_.CE-
0101 1
.names reset_n.BLIF TXD_2_.AR
0 1
.names TXD_1_.Q TXD_0_.Q reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_1_.D
10001 1
01001 1
10-10 1
01-10 1
--1-0 1
.names clk.BLIF TXD_1_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q TXD_1_.CE-
0101 1
.names reset_n.BLIF TXD_1_.AR
0 1
.names TXD_0_.Q reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q TXD_0_.D
0010 1
0001 1
.names clk.BLIF TXD_0_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q TXD_0_.CE-
0101 1
.names reset_n.BLIF TXD_0_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_14_.Q timer_13_.Q timer_12_.Q timer_11_.Q timer_10_.Q timer_9_.Q timer_8_.Q timer_7_.Q timer_6_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q nx1988.BLIF reg_sm_1_.D-
1-1000000100000010- 1
0-0---------------- 1
01----------------- 1
0-----------------0 1
.names clk.BLIF reg_sm_1_.C
1 1
.names reset_n.BLIF reg_sm_1_.AR
0 1
.names reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_14_.T
--1011111111111111 1
01-010110101100000 1
0--111111111111111 1
1--011111111111111 1
0100-------------- 1
11-1-------------- 1
.names clk.BLIF reg_cdata_14_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_14_.CE-
0101 1
.names reset_n.BLIF reg_cdata_14_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_start_s.Q reg_sm_0_.Q nx1854.BLIF reg_sm_2_.D.X1
01--- 1
1-111 1
.names reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_sm_2_.D.X2
001100000000000011 1
.names clk.BLIF reg_sm_2_.C
1 1
.names reset_n.BLIF reg_sm_2_.AR
0 1
.names start.BLIF reg_start_s.D
1 1
.names clk.BLIF reg_start_s.C
1 1
.names reset_n.BLIF reg_start_s.AR
0 1
.names reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_start_s.Q reg_sm_0_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_dis_next.Q nx1854.BLIF nx1934.BLIF nx1988.BLIF reg_sm_0_.T
001-100000000000011---- 1
10--000000000000011---- 1
0-1-0--------------0-1- 1
0-010------------------ 1
1---1---------------1-- 1
0-0-1-----------------1 1
.names clk.BLIF reg_sm_0_.C
1 1
.names reset_n.BLIF reg_sm_0_.AR
0 1
.names reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_13_.T
--10-1111111111111 1
01-010110101100000 1
0--1-1111111111111 1
1--0-1111111111111 1
0-001------------- 1
1--11------------- 1
.names clk.BLIF reg_cdata_13_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_13_.CE-
0101 1
.names reset_n.BLIF reg_cdata_13_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_12_.T
01--111111111111 1
1-0-111111111111 1
0-1-111111111111 1
0001------------ 1
1-11------------ 1
.names clk.BLIF reg_cdata_12_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_12_.CE-
0101 1
.names reset_n.BLIF reg_cdata_12_.AR
0 1
.names reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_11_.T
--10---11111111111 1
01-010110101100000 1
0--1---11111111111 1
1--0---11111111111 1
0-00--1----------- 1
1--1--1----------- 1
.names clk.BLIF reg_cdata_11_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_11_.CE-
0101 1
.names reset_n.BLIF reg_cdata_11_.AR
0 1
.names reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_10_.T
--10----1111111111 1
01-010110101100000 1
0--1----1111111111 1
1--0----1111111111 1
0-00---1---------- 1
1--1---1---------- 1
.names clk.BLIF reg_cdata_10_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_10_.CE-
0101 1
.names reset_n.BLIF reg_cdata_10_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_9_.T
-10-111111111 1
0-1-111111111 1
1-0-111111111 1
0001--------- 1
1-11--------- 1
.names clk.BLIF reg_cdata_9_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_9_.CE-
0101 1
.names reset_n.BLIF reg_cdata_9_.AR
0 1
.names reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_8_.T
--10------11111111 1
01-010110101100000 1
0--1------11111111 1
1--0------11111111 1
0-00-----1-------- 1
1--1-----1-------- 1
.names clk.BLIF reg_cdata_8_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_8_.CE-
0101 1
.names reset_n.BLIF reg_cdata_8_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_7_.T
01--1111111 1
1-0-1111111 1
0-1-1111111 1
0001------- 1
1-11------- 1
.names clk.BLIF reg_cdata_7_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_7_.CE-
0101 1
.names reset_n.BLIF reg_cdata_7_.AR
0 1
.names reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_6_.D-
01-01011010-100000 1
-----------1111111 1
0-00-------------- 1
1--1-------------- 1
-----------00----- 1
-----------0----0- 1
-----------0---0-- 1
-----------0--0--- 1
-----------0-0---- 1
-----------0-----0 1
.names clk.BLIF reg_cdata_6_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_6_.CE-
0101 1
.names reset_n.BLIF reg_cdata_6_.AR
0 1
.names reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_5_.D-
01-010110101-00000 1
------------111111 1
0-00-------------- 1
1--1-------------- 1
------------0---0- 1
------------0--0-- 1
------------0-0--- 1
------------00---- 1
------------0----0 1
.names clk.BLIF reg_cdata_5_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_5_.CE-
0101 1
.names reset_n.BLIF reg_cdata_5_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_4_.T
01--1111 1
1-0-1111 1
0-1-1111 1
0001---- 1
1-11---- 1
.names clk.BLIF reg_cdata_4_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_4_.CE-
0101 1
.names reset_n.BLIF reg_cdata_4_.AR
0 1
.names reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_3_.D-
-0010000000000-000 1
--------------1111 1
0-00-------------- 1
1--1-------------- 1
--------------0-0- 1
--------------00-- 1
--------------0--0 1
.names clk.BLIF reg_cdata_3_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_3_.CE-
0101 1
.names reset_n.BLIF reg_cdata_3_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_2_.D-
000--- 1
---111 1
1-1--- 1
---00- 1
---0-0 1
.names clk.BLIF reg_cdata_2_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_2_.CE-
0101 1
.names reset_n.BLIF reg_cdata_2_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_1_.D-
000-- 1
1-1-- 1
---00 1
---11 1
.names clk.BLIF reg_cdata_1_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_1_.CE-
0101 1
.names reset_n.BLIF reg_cdata_1_.AR
0 1
.names reg_sm_1_.Q reg_cdata_14_.Q reg_sm_2_.Q reg_sm_0_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q reg_cdata_0_.D-
-0010000000000100- 1
01-01011010110000- 1
0-00-------------- 1
1--1-------------- 1
-----------------1 1
.names clk.BLIF reg_cdata_0_.C
1 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_cdata_0_.CE-
0101 1
.names reset_n.BLIF reg_cdata_0_.AR
0 1
.names reg_i_data_4_.Q reg_i_data_3_.Q reg_i_data_2_.Q reg_i_data_1_.Q reg_i_data_0_.Q reg_dis_next.D
00000 1
.names clk.BLIF reg_dis_next.C
1 1
.names reset_n.BLIF reg_dis_next.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_i_data_4_.Q reg_i_data_3_.Q reg_i_data_2_.Q reg_i_data_1_.Q reg_i_data_0_.Q reg_i_data_4_.D-
010010000 1
01000--1- 1
01000-1-- 1
010001--- 1
01000---1 1
.names clk.BLIF reg_i_data_4_.C
1 1
.names reset_n.BLIF reg_i_data_4_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_i_data_3_.Q reg_i_data_2_.Q reg_i_data_1_.Q reg_i_data_0_.Q reg_i_data_3_.D-
01001000 1
01000-1- 1
010001-- 1
01000--1 1
.names clk.BLIF reg_i_data_3_.C
1 1
.names reset_n.BLIF reg_i_data_3_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_i_data_2_.Q reg_i_data_1_.Q reg_i_data_0_.Q reg_i_data_2_.D
0100000 1
010011- 1
01001-1 1
.names clk.BLIF reg_i_data_2_.C
1 1
.names reset_n.BLIF reg_i_data_2_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_i_data_1_.Q reg_i_data_0_.Q reg_i_data_1_.D
010000 1
010011 1
.names clk.BLIF reg_i_data_1_.C
1 1
.names reset_n.BLIF reg_i_data_1_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q reg_dis_next.Q reg_i_data_0_.Q reg_i_data_0_.D
01000 1
.names clk.BLIF reg_i_data_0_.C
1 1
.names reset_n.BLIF reg_i_data_0_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_14_.Q timer_13_.Q timer_12_.Q timer_11_.Q timer_10_.Q timer_9_.Q timer_8_.Q timer_7_.Q timer_6_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_14_.T
--1-11111111111111 1
-1--11111111111111 1
1---11111111111111 1
0001-------------- 1
.names clk.BLIF timer_14_.C
1 1
.names reset_n.BLIF timer_14_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_13_.Q timer_12_.Q timer_11_.Q timer_10_.Q timer_9_.Q timer_8_.Q timer_7_.Q timer_6_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_13_.T
--1-1111111111111 1
-1--1111111111111 1
1---1111111111111 1
0001------------- 1
.names clk.BLIF timer_13_.C
1 1
.names reset_n.BLIF timer_13_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_12_.Q timer_11_.Q timer_10_.Q timer_9_.Q timer_8_.Q timer_7_.Q timer_6_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_12_.T
--1-111111111111 1
-1--111111111111 1
1---111111111111 1
0001------------ 1
.names clk.BLIF timer_12_.C
1 1
.names reset_n.BLIF timer_12_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_11_.Q timer_10_.Q timer_9_.Q timer_8_.Q timer_7_.Q timer_6_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_11_.T
--1-11111111111 1
-1--11111111111 1
1---11111111111 1
0001----------- 1
.names clk.BLIF timer_11_.C
1 1
.names reset_n.BLIF timer_11_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_10_.Q timer_9_.Q timer_8_.Q timer_7_.Q timer_6_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_10_.T
--1-1111111111 1
-1--1111111111 1
1---1111111111 1
0001---------- 1
.names clk.BLIF timer_10_.C
1 1
.names reset_n.BLIF timer_10_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_9_.Q timer_8_.Q timer_7_.Q timer_6_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_9_.T
--1-111111111 1
-1--111111111 1
1---111111111 1
0001--------- 1
.names clk.BLIF timer_9_.C
1 1
.names reset_n.BLIF timer_9_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_8_.Q timer_7_.Q timer_6_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_8_.T
--1-11111111 1
-1--11111111 1
1---11111111 1
0001-------- 1
.names clk.BLIF timer_8_.C
1 1
.names reset_n.BLIF timer_8_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_7_.Q timer_6_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_7_.T
--1-1111111 1
-1--1111111 1
1---1111111 1
0001------- 1
.names clk.BLIF timer_7_.C
1 1
.names reset_n.BLIF timer_7_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_6_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_6_.T
0001------ 1
--1-111111 1
-1--111111 1
1---111111 1
.names clk.BLIF timer_6_.C
1 1
.names reset_n.BLIF timer_6_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_5_.T
0001----- 1
--1-11111 1
-1--11111 1
1---11111 1
.names clk.BLIF timer_5_.C
1 1
.names reset_n.BLIF timer_5_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_4_.T
0001---- 1
--1-1111 1
-1--1111 1
1---1111 1
.names clk.BLIF timer_4_.C
1 1
.names reset_n.BLIF timer_4_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_3_.D-
---1111 1
000---- 1
---0-0- 1
---00-- 1
---0--0 1
.names clk.BLIF timer_3_.C
1 1
.names reset_n.BLIF timer_3_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_2_.Q timer_1_.Q timer_0_.Q timer_2_.D-
000--- 1
---111 1
---00- 1
---0-0 1
.names clk.BLIF timer_2_.C
1 1
.names reset_n.BLIF timer_2_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_1_.Q timer_0_.Q timer_1_.D-
000-- 1
---00 1
---11 1
.names clk.BLIF timer_1_.C
1 1
.names reset_n.BLIF timer_1_.AR
0 1
.names reg_sm_1_.Q reg_sm_2_.Q reg_sm_0_.Q timer_0_.Q timer_0_.D-
000- 1
---1 1
.names clk.BLIF timer_0_.C
1 1
.names reset_n.BLIF timer_0_.AR
0 1
.names timer_14_.Q timer_13_.Q timer_12_.Q timer_11_.Q timer_10_.Q timer_9_.Q timer_8_.Q timer_7_.Q timer_6_.Q timer_5_.Q timer_4_.Q timer_3_.Q timer_2_.Q timer_1_.Q timer_0_.Q nx1854
000000100000010 1
.names reg_cdata_14_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q nx1934
110110101100000 1
.names reg_cdata_14_.Q reg_cdata_13_.Q reg_cdata_12_.Q reg_cdata_11_.Q reg_cdata_10_.Q reg_cdata_9_.Q reg_cdata_8_.Q reg_cdata_7_.Q reg_cdata_6_.Q reg_cdata_5_.Q reg_cdata_4_.Q reg_cdata_3_.Q reg_cdata_2_.Q reg_cdata_1_.Q reg_cdata_0_.Q nx1988
000000000001000 1
.end