TDA  - Timing Driven Analyze 
Ver. 1.0, supported by Lattice Semiconductor
ispLEVER 6.01 Copyright 1992-2006 Lattice Semiconductor. All Rights Reserved.
......

Summary for Timing Constraints:

Goal: Clock Period on clock domain "clk" of 8.00ns (125.00MHz) is met.
      Worst case path:
      From  : TX_EN.C
      to    : TXD_0_.CE
      Actual: 7.20ns (138.89MHz)
      Slack : 0.80ns

Goal: Clock Period on clock domain "NI_STR" of 8.33ns (120.05MHz) is met.
      Worst case path:
      From  : ni_nires_reg_gray_cntf_0_.C
      to    : ni_nires_reg_data0neg_0_.CE
      Actual: 5.00ns (200.00MHz)
      Slack : 3.33ns

Goal: Clock Period on clock domain "jTCK" of 1000.00ns (1.00MHz) is met.
      Worst case path:
      From  : j2c_bitcnt_1_.C
      to    : j2c_reg_clear.CE
      Actual: 7.25ns (137.93MHz)
      Slack : 992.75ns

  Total constraints: 3, passed: 3, not passed: 0