Timing Report // Project = oase // Family = lc4k // Device = LC4256V // Speed = -3 // Voltage = 3.3 // Operating Condition = COM // Data sheet version = 3.2 // Pass Bidirection = OFF // Pass S/R = OFF // Pass Latch = OFF // Pass Clock = OFF // Maximum Paths = 20 // T_SU Endpoints D/T inputs = ON // T_SU Endpoints CE inputs = OFF // T_SU Endpoints S/R inputs = OFF // T_SU Endpoints RAM gated = ON // Fmax of CE = ON // Fmax of RAM = ON // Location(From => To) // Pin number: numeric number preceded by "p", BGA number as is // Macrocell number: Segment#,GLB#,Macrocell# // Segment#: starts from 0 (if applicable) // GLB#: starts from A..Z, AA..ZZ // Macrocell#: starts from 0 to 31 Summary for Timing Constraints: -- fMAX_0 = 7.20 ns ( 8.00) : passed with slack = 0.80 (138.89 MHz) -- fMAX_1 = 5.00 ns ( 8.33) : passed with slack = 3.33 (200.00 MHz) -- fMAX_2 = 7.25 ns (1000.00) : passed with slack = 992.75 (137.93 MHz) Total constraints: 3, passed: 3, not passed: 0 fMAX_0 = 8.00 , "clk ", "clk "; Slack Req. Delay Level Location(From => To) Source Destination Destination_Clock ===== ==== ===== ===== ==================== ====== =========== ================= 0.80 8.00 7.20 2 K0 => O6 TX_EN.C TXD_0_.CE clk 0.80 8.00 7.20 2 K0 => O10 TX_EN.C TXD_1_.CE clk 0.80 8.00 7.20 2 K0 => O0 TX_EN.C TXD_2_.CE clk 0.80 8.00 7.20 2 K0 => N12 TX_EN.C TXD_3_.CE clk 0.80 8.00 7.20 2 K0 => N1 TX_EN.C TXD_4_.CE clk 0.80 8.00 7.20 2 K0 => N7 TX_EN.C TXD_5_.CE clk 0.80 8.00 7.20 2 K0 => N9 TX_EN.C TXD_6_.CE clk 0.80 8.00 7.20 2 K0 => M12 TX_EN.C TXD_7_.CE clk 0.80 8.00 7.20 2 K0 => M13 TX_EN.C TXD_8_.CE clk 0.80 8.00 7.20 2 K0 => M4 TX_EN.C TXD_9_.CE clk 0.80 8.00 7.20 2 K0 => L6 TX_EN.C TXD_10_.CE clk 0.80 8.00 7.20 2 K0 => L9 TX_EN.C TXD_11_.CE clk 0.80 8.00 7.20 2 K0 => L10 TX_EN.C TXD_12_.CE clk 0.80 8.00 7.20 2 K0 => L13 TX_EN.C TXD_13_.CE clk 0.80 8.00 7.20 2 K0 => K2 TX_EN.C TXD_14_.CE clk 0.80 8.00 7.20 2 K0 => K6 TX_EN.C TXD_15_.CE clk 0.85 8.00 7.15 2 A14 => A14 ni_nires_reg_old_cnt_0_.C ni_nires_reg_old_cnt_0_.CE clk 0.85 8.00 7.15 2 A14 => A15 ni_nires_reg_old_cnt_0_.C ni_nires_reg_old_cnt_1_.CE clk 1.10 8.00 6.90 2 M1 => M8 ID_2_4_.C ID_2_0_.CE clk 1.10 8.00 6.90 2 M1 => M3 ID_2_4_.C ID_2_1_.CE clk fMAX_1 = 8.33 , "NI_STR ", "NI_STR "; Slack Req. Delay Level Location(From => To) Source Destination Destination_Clock ===== ==== ===== ===== ==================== ====== =========== ================= 3.33 8.33 5.00 1 F9 => H12 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_0_.CE NI_STR 3.33 8.33 5.00 1 F9 => F13 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_1_.CE NI_STR 3.33 8.33 5.00 1 F9 => G3 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_2_.CE NI_STR 3.33 8.33 5.00 1 F9 => N6 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_3_.CE NI_STR 3.33 8.33 5.00 1 F9 => N10 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_4_.CE NI_STR 3.33 8.33 5.00 1 F9 => N14 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_5_.CE NI_STR 3.33 8.33 5.00 1 F9 => N2 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_6_.CE NI_STR 3.33 8.33 5.00 1 F9 => B11 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_7_.CE NI_STR 3.33 8.33 5.00 1 F9 => G6 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_8_.CE NI_STR 3.33 8.33 5.00 1 F9 => D0 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data0neg_9_.CE NI_STR 3.33 8.33 5.00 1 F9 => H11 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_0_.CE NI_STR 3.33 8.33 5.00 1 F9 => F12 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_1_.CE NI_STR 3.33 8.33 5.00 1 F9 => G2 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_2_.CE NI_STR 3.33 8.33 5.00 1 F9 => B9 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_3_.CE NI_STR 3.33 8.33 5.00 1 F9 => N8 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_4_.CE NI_STR 3.33 8.33 5.00 1 F9 => H13 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_5_.CE NI_STR 3.33 8.33 5.00 1 F9 => N0 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_6_.CE NI_STR 3.33 8.33 5.00 1 F9 => B10 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_7_.CE NI_STR 3.33 8.33 5.00 1 F9 => O3 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_8_.CE NI_STR 3.33 8.33 5.00 1 F9 => D15 ni_nires_reg_gray_cntf_0_.C ni_nires_reg_data1neg_9_.CE NI_STR fMAX_2 = 1000.00 , "jTCK ", "jTCK "; Slack Req. Delay Level Location(From => To) Source Destination Destination_Clock ===== ==== ===== ===== ==================== ====== =========== ================= 992.75 1000.00 7.25 2 E10 => E2 j2c_bitcnt_1_.C j2c_reg_clear.CE jTCK 992.75 1000.00 7.25 2 E10 => E12 j2c_bitcnt_1_.C j2c_reg_rstout_n_i.CE jTCK 996.75 1000.00 3.25 1 E13 => E13 j2c_bitcnt_0_.C j2c_bitcnt_0_.D jTCK 996.75 1000.00 3.25 1 E10 => E10 j2c_bitcnt_1_.C j2c_bitcnt_1_.D jTCK 996.75 1000.00 3.25 1 E10 => E8 j2c_bitcnt_1_.C j2c_bitcnt_2_.D jTCK 996.75 1000.00 3.25 1 E10 => E2 j2c_bitcnt_1_.C j2c_reg_clear.D jTCK 996.75 1000.00 3.25 1 E10 => E12 j2c_bitcnt_1_.C j2c_reg_rstout_n_i.D jTCK 996.80 1000.00 3.20 1 I9 => J7 j2c_reg_shreg_4_.C j2c_reg_shreg_3_.D jTCK 996.85 1000.00 3.15 1 K7 => J6 j2c_reg_shreg_2_.C j2c_reg_shreg_1_.D jTCK 996.90 1000.00 3.10 1 J6 => K15 j2c_reg_shreg_1_.C j2c_reg_shreg_0_.D jTCK 996.90 1000.00 3.10 1 J7 => K7 j2c_reg_shreg_3_.C j2c_reg_shreg_2_.D jTCK 996.90 1000.00 3.10 1 I10 => I9 j2c_reg_shreg_5_.C j2c_reg_shreg_4_.D jTCK 996.90 1000.00 3.10 1 I11 => I10 j2c_reg_shreg_6_.C j2c_reg_shreg_5_.D jTCK 996.90 1000.00 3.10 1 I12 => I11 j2c_reg_shreg_7_.C j2c_reg_shreg_6_.D jTCK