// Batch Timer Log File (Release Version: 6.1.00.38.44.06)

//  Project = oase
//  Family  = lc4k
//  Device  = LC4256V
//  Speed   = -3
//  Voltage = 3.3
//  Operating Condition = COM
//  Data sheet version  = 3.2

//  Pass Bidirection = OFF
//  Pass S/R = OFF
//  Pass Latch = OFF
//  Pass Clock = OFF
//  Maximum Paths = 20
//  T_SU Endpoints D/T inputs = ON
//  T_SU Endpoints CE inputs = OFF
//  T_SU Endpoints S/R inputs = OFF
//  T_SU Endpoints RAM gated = ON
//  Fmax of CE = ON
//  Fmax of RAM = ON

//  Location(From => To)
//    Pin number: numeric number preceded by "p", BGA number as is
//    Macrocell number: Segment#,GLB#,Macrocell#
//                      Segment#: starts from 0 (if applicable)
//                      GLB#: starts from A..Z, AA..ZZ
//                      Macrocell#: starts from 0 to 31

//  Register-to-register critical path delay: 14.35 ns
//    -    0.52  tCOi                              j2c_reg_creg1hm_0_.C     ==>  j2c_reg_creg1hm_0_.Q
//    -    1.56  tFBK+tROUTE+tMCELL                j2c_reg_creg1hm_0_.Q     ==>  ix71.X1
//    -    0.64  tPDi                              ix71.X1                  ==>  ix71
//    -    1.61  tFBK+tROUTE+tBLA+tMCELL           ix71                     ==>  ix1154
//    -    0.64  tPDi                              ix1154                   ==>  ix1154
//    -    2.01  tFBK+tROUTE+tBLA*9+tMCELL         ix1154                   ==>  nx1267
//    -    0.64  tPDi                              nx1267                   ==>  nx1267
//    -    1.76  tFBK+tROUTE+tBLA*4+tMCELL         nx1267                   ==>  nx244
//    -    0.64  tPDi                              nx244                    ==>  nx244
//    -    2.08  tFBK+tROUTE+tBLA*4+tPTCLK         nx244                    ==>  TXD_0_.CE
//    -    2.25  tCES                              TXD_0_.CE                ==>  TXD_0_.C