// Node Statistic Information File
// Tool:  ispLEVER 5.0.01.73.31.05_Starter

// Design 'top_ni' created   Tue Sep 05 11:21:05 2006


// Fmax Logic Level: 6.

// Path: j2c_reg_creg1hm_5_.Q
//    -> ix47.X1
//    -> ix1082
//    -> nx1643
//    -> nx1615
//    -> nx1581
//    -> ni_reg_prty_bit_pos_r.D

// Signal Name: TESTEN
// Type: Output
BEGIN TESTEN
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: PRBSEN
// Type: Output
BEGIN PRBSEN
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: LCKREFN
// Type: Output
BEGIN LCKREFN
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ENABLE
// Type: Output
BEGIN ENABLE
Fanin Number		5
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: LOOPEN
// Type: Output
BEGIN LOOPEN
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TX_ER
// Type: Output
BEGIN TX_ER
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: EN
// Type: Output
BEGIN EN
Fanin Number		5
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: SD2ANL
// Type: Output
BEGIN SD2ANL
Fanin Number		5
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: WP_EEP
// Type: Output
BEGIN WP_EEP
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: SCL
// Type: Tri
BEGIN SCL
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: SCL.OE
// Type: Tri
BEGIN SCL.OE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: SDA
// Type: Bidi
BEGIN SDA
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: SDA.OE
// Type: Bidi
BEGIN SDA.OE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Input     	jTMS.BLIF           	0
END

// Signal Name: jTDO
// Type: Tri
BEGIN jTDO
Fanin Number		23
Pterm Number		15
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Node      	nx1191.BLIF         	16
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ix1388.BLIF         	4
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	ix1460.BLIF         	4
Fanin Node      	ix1472.BLIF         	4
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	ix47.BLIF           	4
Fanin Node      	ix59.BLIF           	4
Fanin Node      	j2c_reg_cmdreg_2_.Q 	1
Fanin Node      	j2c_reg_cmdreg_1_.Q 	1
Fanin Node      	ix71.BLIF           	4
Fanin Node      	j2c_bitcnt_2_.Q     	3
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
Fanin Node      	ix369.BLIF          	4
Fanin Node      	ix381.BLIF          	4
Fanin Node      	ix393.BLIF          	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
Fanin Output    	SDA.PIN             	0
END

// Signal Name: jTDO.OE
// Type: Tri
BEGIN jTDO.OE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx194.BLIF          	2
END

// Signal Name: TXD_5_.D
// Type: Output_reg
BEGIN TXD_5_.D
Fanin Number		11
Pterm Number		8
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_5_.Q            	8
Fanin Output    	TXD_4_.Q            	7
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	ix1460.BLIF         	4
Fanin Node      	ix1472.BLIF         	4
Fanin Node      	nx1643.BLIF         	2
Fanin Node      	nx1673.BLIF         	3
Fanin Node      	ni_nires_reg_data_out_5_.Q	4
Fanin Node      	ni_nires_reg_data_out_6_.Q	4
END

// Signal Name: TXD_5_.C
// Type: Output_reg
BEGIN TXD_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_5_.CE
// Type: Output_reg
BEGIN TXD_5_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_4_.D
// Type: Output_reg
BEGIN TXD_4_.D
Fanin Number		10
Pterm Number		7
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_4_.Q            	7
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	ix1460.BLIF         	4
Fanin Node      	ix1472.BLIF         	4
Fanin Node      	nx1507.BLIF         	1
Fanin Node      	nx1615.BLIF         	4
Fanin Node      	nx1643.BLIF         	2
Fanin Node      	ni_nires_reg_data_out_5_.Q	4
Fanin Node      	ni_nires_reg_data_out_6_.Q	4
END

// Signal Name: TXD_4_.C
// Type: Output_reg
BEGIN TXD_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_4_.CE
// Type: Output_reg
BEGIN TXD_4_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_3_.D.X1
// Type: Output_reg
BEGIN TXD_3_.D.X1
Fanin Number		8
Pterm Number		6
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_3_.Q            	6
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	nx1615.BLIF         	4
Fanin Node      	ni_nires_reg_data_out_3_.Q	4
Fanin Node      	ni_nires_reg_data_out_4_.Q	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: TXD_3_.D.X2
// Type: Output_reg
BEGIN TXD_3_.D.X2
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_2_.Q            	13
Fanin Output    	TXD_1_.Q            	8
Fanin Output    	TXD_0_.Q            	9
END

// Signal Name: TXD_3_.C
// Type: Output_reg
BEGIN TXD_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_3_.CE
// Type: Output_reg
BEGIN TXD_3_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_2_.D
// Type: Output_reg
BEGIN TXD_2_.D
Fanin Number		13
Pterm Number		13
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_2_.Q            	13
Fanin Output    	TXD_1_.Q            	8
Fanin Output    	TXD_0_.Q            	9
Fanin Node      	ix1388.BLIF         	4
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	nx1769.BLIF         	2
Fanin Node      	ni_nires_reg_data_out_2_.Q	4
Fanin Node      	ni_nires_reg_data_out_3_.Q	4
Fanin Node      	ni_nires_reg_data_out_4_.Q	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: TXD_2_.C
// Type: Output_reg
BEGIN TXD_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_2_.CE
// Type: Output_reg
BEGIN TXD_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_1_.D
// Type: Output_reg
BEGIN TXD_1_.D
Fanin Number		10
Pterm Number		8
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_1_.Q            	8
Fanin Output    	TXD_0_.Q            	9
Fanin Node      	nx1383.BLIF         	1
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	ni_nires_reg_data_out_1_.Q	4
Fanin Node      	nx1769.BLIF         	2
Fanin Node      	ni_nires_reg_data_out_2_.Q	4
Fanin Node      	ni_nires_reg_data_out_3_.Q	4
END

// Signal Name: TXD_1_.C
// Type: Output_reg
BEGIN TXD_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_1_.CE
// Type: Output_reg
BEGIN TXD_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_0_.D
// Type: Output_reg
BEGIN TXD_0_.D
Fanin Number		9
Pterm Number		9
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_0_.Q            	9
Fanin Node      	nx1383.BLIF         	1
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	nx1507.BLIF         	1
Fanin Node      	ni_nires_reg_data_out_1_.Q	4
Fanin Node      	ni_nires_reg_data_out_0_.Q	4
Fanin Node      	ni_nires_reg_data_out_2_.Q	4
END

// Signal Name: TXD_0_.C
// Type: Output_reg
BEGIN TXD_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_0_.CE
// Type: Output_reg
BEGIN TXD_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TX_EN.D
// Type: Output_reg
BEGIN TX_EN.D
Fanin Number		7
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	nx1289.BLIF         	1
Fanin Node      	ni_pattcount_2_.Q   	3
Fanin Node      	ni_pattcount_1_.Q   	2
Fanin Node      	ni_pattcount_0_.Q   	1
Fanin Node      	ni_pattcount_4_.Q   	1
Fanin Node      	ni_pattcount_3_.Q   	4
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TX_EN.C
// Type: Output_reg
BEGIN TX_EN.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_15_.D.X1
// Type: Output_reg
BEGIN TXD_15_.D.X1
Fanin Number		9
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_14_.Q           	7
Fanin Output    	TXD_13_.Q           	6
Fanin Output    	TXD_12_.Q           	5
Fanin Node      	ix1472.BLIF         	4
Fanin Node      	ni_nires_reg_data_out_17_.Q	4
Fanin Node      	ni_nires_reg_data_out_18_.Q	4
Fanin Node      	nx2057.BLIF         	3
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: TXD_15_.D.X2
// Type: Output_reg
BEGIN TXD_15_.D.X2
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_15_.Q           	4
END

// Signal Name: TXD_15_.C
// Type: Output_reg
BEGIN TXD_15_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_15_.CE
// Type: Output_reg
BEGIN TXD_15_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_14_.D
// Type: Output_reg
BEGIN TXD_14_.D
Fanin Number		13
Pterm Number		7
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_14_.Q           	7
Fanin Output    	TXD_13_.Q           	6
Fanin Output    	TXD_12_.Q           	5
Fanin Node      	ix1388.BLIF         	4
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	ix1460.BLIF         	4
Fanin Node      	ix1472.BLIF         	4
Fanin Node      	ni_nires_reg_data_out_17_.Q	4
Fanin Node      	ni_nires_reg_data_out_18_.Q	4
Fanin Node      	nx1841.BLIF         	3
Fanin Node      	nx2166.BLIF         	3
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: TXD_14_.C
// Type: Output_reg
BEGIN TXD_14_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_14_.CE
// Type: Output_reg
BEGIN TXD_14_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_13_.D
// Type: Output_reg
BEGIN TXD_13_.D
Fanin Number		9
Pterm Number		6
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_13_.Q           	6
Fanin Output    	TXD_12_.Q           	5
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	ix1460.BLIF         	4
Fanin Node      	ix1472.BLIF         	4
Fanin Node      	nx2166.BLIF         	3
Fanin Node      	nx2188.BLIF         	2
END

// Signal Name: TXD_13_.C
// Type: Output_reg
BEGIN TXD_13_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_13_.CE
// Type: Output_reg
BEGIN TXD_13_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_12_.D
// Type: Output_reg
BEGIN TXD_12_.D
Fanin Number		8
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_12_.Q           	5
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	ix1460.BLIF         	4
Fanin Node      	ix1472.BLIF         	4
Fanin Node      	nx1507.BLIF         	1
Fanin Node      	nx2130.BLIF         	4
Fanin Node      	nx2188.BLIF         	2
END

// Signal Name: TXD_12_.C
// Type: Output_reg
BEGIN TXD_12_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_12_.CE
// Type: Output_reg
BEGIN TXD_12_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_11_.D.X1
// Type: Output_reg
BEGIN TXD_11_.D.X1
Fanin Number		8
Pterm Number		6
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx1289.BLIF         	1
Fanin Node      	ni_nires_reg_data_out_13_.Q	4
Fanin Output    	TXD_11_.Q           	6
Fanin Node      	ni_nires_reg_data_out_14_.Q	4
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	nx2130.BLIF         	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: TXD_11_.D.X2
// Type: Output_reg
BEGIN TXD_11_.D.X2
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_10_.Q           	13
Fanin Output    	TXD_9_.Q            	8
Fanin Output    	TXD_8_.Q            	9
END

// Signal Name: TXD_11_.C
// Type: Output_reg
BEGIN TXD_11_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_11_.CE
// Type: Output_reg
BEGIN TXD_11_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_10_.D
// Type: Output_reg
BEGIN TXD_10_.D
Fanin Number		13
Pterm Number		13
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	ni_nires_reg_data_out_12_.Q	4
Fanin Node      	nx1289.BLIF         	1
Fanin Node      	ni_nires_reg_data_out_13_.Q	4
Fanin Output    	TXD_10_.Q           	13
Fanin Output    	TXD_9_.Q            	8
Fanin Output    	TXD_8_.Q            	9
Fanin Node      	ni_nires_reg_data_out_14_.Q	4
Fanin Node      	ix1388.BLIF         	4
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	nx1769.BLIF         	2
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: TXD_10_.C
// Type: Output_reg
BEGIN TXD_10_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_10_.CE
// Type: Output_reg
BEGIN TXD_10_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_9_.D
// Type: Output_reg
BEGIN TXD_9_.D
Fanin Number		10
Pterm Number		8
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	ni_nires_reg_data_out_12_.Q	4
Fanin Node      	nx1289.BLIF         	1
Fanin Node      	ni_nires_reg_data_out_13_.Q	4
Fanin Output    	TXD_9_.Q            	8
Fanin Output    	TXD_8_.Q            	9
Fanin Node      	nx1383.BLIF         	1
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	nx1769.BLIF         	2
Fanin Node      	ni_nires_reg_data_out_11_.Q	4
END

// Signal Name: TXD_9_.C
// Type: Output_reg
BEGIN TXD_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_9_.CE
// Type: Output_reg
BEGIN TXD_9_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_8_.D
// Type: Output_reg
BEGIN TXD_8_.D
Fanin Number		9
Pterm Number		9
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	ni_nires_reg_data_out_10_.Q	4
Fanin Node      	ni_nires_reg_data_out_12_.Q	4
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_8_.Q            	9
Fanin Node      	nx1383.BLIF         	1
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	nx1507.BLIF         	1
Fanin Node      	ni_nires_reg_data_out_11_.Q	4
END

// Signal Name: TXD_8_.C
// Type: Output_reg
BEGIN TXD_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_8_.CE
// Type: Output_reg
BEGIN TXD_8_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_7_.D.X1
// Type: Output_reg
BEGIN TXD_7_.D.X1
Fanin Number		9
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_6_.Q            	7
Fanin Output    	TXD_5_.Q            	8
Fanin Output    	TXD_4_.Q            	7
Fanin Node      	ix1472.BLIF         	4
Fanin Node      	nx1525.BLIF         	3
Fanin Node      	ni_nires_reg_data_out_7_.Q	4
Fanin Node      	ni_nires_reg_data_out_8_.Q	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: TXD_7_.D.X2
// Type: Output_reg
BEGIN TXD_7_.D.X2
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		4
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_7_.Q            	4
END

// Signal Name: TXD_7_.C
// Type: Output_reg
BEGIN TXD_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_7_.CE
// Type: Output_reg
BEGIN TXD_7_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: TXD_6_.D
// Type: Output_reg
BEGIN TXD_6_.D
Fanin Number		13
Pterm Number		7
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TXD_6_.Q            	7
Fanin Output    	TXD_5_.Q            	8
Fanin Output    	TXD_4_.Q            	7
Fanin Node      	ix1388.BLIF         	4
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	ix1460.BLIF         	4
Fanin Node      	ix1472.BLIF         	4
Fanin Node      	nx1673.BLIF         	3
Fanin Node      	nx1841.BLIF         	3
Fanin Node      	ni_nires_reg_data_out_7_.Q	4
Fanin Node      	ni_nires_reg_data_out_8_.Q	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: TXD_6_.C
// Type: Output_reg
BEGIN TXD_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_6_.CE
// Type: Output_reg
BEGIN TXD_6_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	nx240.BLIF          	2
END

// Signal Name: ni_nires_reg_data0pos_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: nx1191
// Type: Node
BEGIN nx1191
Fanin Number		21
Pterm Number		16
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	nx2418.BLIF         	4
Fanin Node      	nx2452.BLIF         	2
Fanin Node      	j2c_reg_cmdreg_1_.Q 	1
Fanin Node      	ID_0_6_.Q           	1
Fanin Node      	nx2471.BLIF         	2
Fanin Node      	ID_0_5_.Q           	1
Fanin Node      	ID_0_4_.Q           	1
Fanin Node      	j2c_bitcnt_2_.Q     	3
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_1_6_.Q           	1
Fanin Node      	ID_1_5_.Q           	1
Fanin Node      	ID_1_4_.Q           	1
Fanin Node      	ID_1_3_.Q           	1
Fanin Node      	ID_1_2_.Q           	4
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
Fanin Node      	nx2062.BLIF         	11
END

// Signal Name: ni_nires_reg_data_out_10_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_10_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_data2pos_0_.Q	1
Fanin Node      	ni_nires_reg_data3pos_0_.Q	1
Fanin Node      	ni_nires_reg_data0pos_0_.Q	1
Fanin Node      	ni_nires_reg_data1pos_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_10_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_10_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2pos_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data_out_12_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_12_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_data2pos_2_.Q	1
Fanin Node      	ni_nires_reg_data3pos_2_.Q	1
Fanin Node      	ni_nires_reg_data0pos_2_.Q	1
Fanin Node      	ni_nires_reg_data1pos_2_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_12_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_12_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2pos_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ix1284
// Type: Node
BEGIN ix1284
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1hm_2_.Q	1
Fanin Node      	ix47.BLIF           	4
Fanin Node      	ix59.BLIF           	4
Fanin Node      	ix71.BLIF           	4
END

// Signal Name: ni_nires_reg_data0pos_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: nx1289
// Type: Node
BEGIN nx1289
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: ni_nires_reg_data_out_13_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_13_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_data2pos_3_.Q	1
Fanin Node      	ni_nires_reg_data3pos_3_.Q	1
Fanin Node      	ni_nires_reg_data0pos_3_.Q	1
Fanin Node      	ni_nires_reg_data1pos_3_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_13_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_13_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2pos_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data_out_14_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_14_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_data2pos_4_.Q	1
Fanin Node      	ni_nires_reg_data3pos_4_.Q	1
Fanin Node      	ni_nires_reg_data0pos_4_.Q	1
Fanin Node      	ni_nires_reg_data1pos_4_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_14_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_14_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2pos_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data_out_15_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_15_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_data2pos_5_.Q	1
Fanin Node      	ni_nires_reg_data3pos_5_.Q	1
Fanin Node      	ni_nires_reg_data0pos_5_.Q	1
Fanin Node      	ni_nires_reg_data1pos_5_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_15_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_15_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: nx1383
// Type: Node
BEGIN nx1383
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: ni_nires_reg_data2pos_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ix1388
// Type: Node
BEGIN ix1388
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0hm_2_.Q	1
Fanin Node      	ix369.BLIF          	4
Fanin Node      	ix381.BLIF          	4
Fanin Node      	ix393.BLIF          	4
END

// Signal Name: ni_nires_reg_data3pos_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ix1438
// Type: Node
BEGIN ix1438
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0hm_4_.Q	1
Fanin Node      	ix369.BLIF          	4
Fanin Node      	ix381.BLIF          	4
Fanin Node      	ix393.BLIF          	4
END

// Signal Name: ni_nires_reg_data_out_16_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_16_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_data2pos_6_.Q	1
Fanin Node      	ni_nires_reg_data3pos_6_.Q	1
Fanin Node      	ni_nires_reg_data0pos_6_.Q	1
Fanin Node      	ni_nires_reg_data1pos_6_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_16_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_16_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2pos_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: nx1457
// Type: Node
BEGIN nx1457
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1460.BLIF         	4
Fanin Node      	ix1472.BLIF         	4
END

// Signal Name: ni_nires_reg_data3pos_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ix1460
// Type: Node
BEGIN ix1460
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0hm_5_.Q	1
Fanin Node      	ix369.BLIF          	4
Fanin Node      	ix381.BLIF          	4
Fanin Node      	ix393.BLIF          	4
END

// Signal Name: ni_nires_reg_data0pos_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: nx194
// Type: Node
BEGIN nx194
Fanin Number		3
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Input     	jTCK.BLIF           	0
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: ix1472
// Type: Node
BEGIN ix1472
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0hm_6_.Q	1
Fanin Node      	ix369.BLIF          	4
Fanin Node      	ix381.BLIF          	4
Fanin Node      	ix393.BLIF          	4
END

// Signal Name: j2c_reg_creg1hm_2_.D
// Type: Node_reg
BEGIN j2c_reg_creg1hm_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_4_.Q  	1
END

// Signal Name: j2c_reg_creg1hm_2_.C
// Type: Node_reg
BEGIN j2c_reg_creg1hm_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg1hm_2_.CE
// Type: Node_reg
BEGIN j2c_reg_creg1hm_2_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg1hm_2_.AR
// Type: Node_reg
BEGIN j2c_reg_creg1hm_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ni_nires_reg_data_out_17_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_17_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_data2pos_7_.Q	1
Fanin Node      	ni_nires_reg_data3pos_7_.Q	1
Fanin Node      	ni_nires_reg_data0pos_7_.Q	1
Fanin Node      	ni_nires_reg_data1pos_7_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_17_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_17_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: j2c_reg_cmdreg_0_.D
// Type: Node_reg
BEGIN j2c_reg_cmdreg_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_4_.Q  	1
END

// Signal Name: j2c_reg_cmdreg_0_.C
// Type: Node_reg
BEGIN j2c_reg_cmdreg_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_cmdreg_0_.CE
// Type: Node_reg
BEGIN j2c_reg_cmdreg_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
END

// Signal Name: j2c_reg_cmdreg_0_.AP
// Type: Node_reg
BEGIN j2c_reg_cmdreg_0_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: nx0
// Type: Node
BEGIN nx0
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Input     	jTMS.BLIF           	0
END

// Signal Name: ni_nires_reg_data3pos_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: j2c_reg_shreg_4_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_5_.Q  	1
END

// Signal Name: j2c_reg_shreg_4_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: ni_nires_reg_data0pos_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: nx2401
// Type: Node
BEGIN nx2401
Fanin Number		8
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_0_7_.Q           	1
Fanin Node      	ID_0_6_.Q           	1
Fanin Node      	ID_0_5_.Q           	1
Fanin Node      	ID_0_4_.Q           	1
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: j2c_reg_shreg_5_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_6_.Q  	1
END

// Signal Name: j2c_reg_shreg_5_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: ni_nires_reg_data1pos_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: j2c_reg_shreg_6_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_7_.Q  	1
END

// Signal Name: j2c_reg_shreg_6_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_shreg_7_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
END

// Signal Name: j2c_reg_shreg_7_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_cmdreg_3_.D
// Type: Node_reg
BEGIN j2c_reg_cmdreg_3_.D
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_shreg_7_.Q  	1
END

// Signal Name: j2c_reg_cmdreg_3_.C
// Type: Node_reg
BEGIN j2c_reg_cmdreg_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_cmdreg_3_.AR
// Type: Node_reg
BEGIN j2c_reg_cmdreg_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ni_nires_reg_data_out_18_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_18_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_data2pos_8_.Q	1
Fanin Node      	ni_nires_reg_data3pos_8_.Q	1
Fanin Node      	ni_nires_reg_data0pos_8_.Q	1
Fanin Node      	ni_nires_reg_data1pos_8_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_18_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_18_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2pos_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: nx1507
// Type: Node
BEGIN nx1507
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1388.BLIF         	4
Fanin Node      	ix1438.BLIF         	4
END

// Signal Name: j2c_reg_creg1hm_6_.D
// Type: Node_reg
BEGIN j2c_reg_creg1hm_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_7_.Q  	1
END

// Signal Name: j2c_reg_creg1hm_6_.C
// Type: Node_reg
BEGIN j2c_reg_creg1hm_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg1hm_6_.CE
// Type: Node_reg
BEGIN j2c_reg_creg1hm_6_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg1hm_6_.AP
// Type: Node_reg
BEGIN j2c_reg_creg1hm_6_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: j2c_reg_creg1hm_5_.D
// Type: Node_reg
BEGIN j2c_reg_creg1hm_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_6_.Q  	1
END

// Signal Name: j2c_reg_creg1hm_5_.C
// Type: Node_reg
BEGIN j2c_reg_creg1hm_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg1hm_5_.CE
// Type: Node_reg
BEGIN j2c_reg_creg1hm_5_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg1hm_5_.AP
// Type: Node_reg
BEGIN j2c_reg_creg1hm_5_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: nx2418
// Type: Node
BEGIN nx2418
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
END

// Signal Name: j2c_reg_creg1hm_4_.D
// Type: Node_reg
BEGIN j2c_reg_creg1hm_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_5_.Q  	1
END

// Signal Name: j2c_reg_creg1hm_4_.C
// Type: Node_reg
BEGIN j2c_reg_creg1hm_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg1hm_4_.CE
// Type: Node_reg
BEGIN j2c_reg_creg1hm_4_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg1hm_4_.AR
// Type: Node_reg
BEGIN j2c_reg_creg1hm_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: j2c_reg_creg1hm_3_.D
// Type: Node_reg
BEGIN j2c_reg_creg1hm_3_.D
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_5_.Q  	1
Fanin Node      	j2c_reg_shreg_6_.Q  	1
Fanin Node      	j2c_reg_shreg_7_.Q  	1
END

// Signal Name: j2c_reg_creg1hm_3_.C
// Type: Node_reg
BEGIN j2c_reg_creg1hm_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg1hm_3_.CE
// Type: Node_reg
BEGIN j2c_reg_creg1hm_3_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg1hm_3_.AR
// Type: Node_reg
BEGIN j2c_reg_creg1hm_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: nx1525.X1
// Type: Node
BEGIN nx1525.X1
Fanin Number		6
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ni_nires_reg_data_out_8_.Q	4
Fanin Node      	ni_nires_reg_data_out_9_.Q	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: nx1525.X2
// Type: Node
BEGIN nx1525.X2
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_data_out_8_.Q	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: ni_nires_reg_data_out_19_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_19_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_data2pos_9_.Q	1
Fanin Node      	ni_nires_reg_data3pos_9_.Q	1
Fanin Node      	ni_nires_reg_data0pos_9_.Q	1
Fanin Node      	ni_nires_reg_data1pos_9_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_19_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_19_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2pos_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ix47.X1
// Type: Node
BEGIN ix47.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1hm_5_.Q	1
Fanin Node      	j2c_reg_creg1hm_4_.Q	1
Fanin Node      	j2c_reg_creg1hm_3_.Q	4
END

// Signal Name: ix47.X2
// Type: Node
BEGIN ix47.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1hm_6_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: j2c_reg_creg1hm_1_.D
// Type: Node_reg
BEGIN j2c_reg_creg1hm_1_.D
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_4_.Q  	1
Fanin Node      	j2c_reg_shreg_6_.Q  	1
Fanin Node      	j2c_reg_shreg_7_.Q  	1
END

// Signal Name: j2c_reg_creg1hm_1_.C
// Type: Node_reg
BEGIN j2c_reg_creg1hm_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg1hm_1_.CE
// Type: Node_reg
BEGIN j2c_reg_creg1hm_1_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg1hm_1_.AR
// Type: Node_reg
BEGIN j2c_reg_creg1hm_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: nx2452
// Type: Node
BEGIN nx2452
Fanin Number		6
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_1_.Q 	1
Fanin Node      	ID_2_6_.Q           	1
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
Fanin Node      	ID_3_6_.Q           	1
END

// Signal Name: ix59.X1
// Type: Node
BEGIN ix59.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1hm_6_.Q	1
Fanin Node      	j2c_reg_creg1hm_5_.Q	1
Fanin Node      	j2c_reg_creg1hm_1_.Q	4
END

// Signal Name: ix59.X2
// Type: Node
BEGIN ix59.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1hm_2_.Q	1
END

// Signal Name: j2c_reg_creg1hm_0_.D
// Type: Node_reg
BEGIN j2c_reg_creg1hm_0_.D
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_4_.Q  	1
Fanin Node      	j2c_reg_shreg_5_.Q  	1
Fanin Node      	j2c_reg_shreg_7_.Q  	1
END

// Signal Name: j2c_reg_creg1hm_0_.C
// Type: Node_reg
BEGIN j2c_reg_creg1hm_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg1hm_0_.CE
// Type: Node_reg
BEGIN j2c_reg_creg1hm_0_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg1hm_0_.AP
// Type: Node_reg
BEGIN j2c_reg_creg1hm_0_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: j2c_reg_cmdreg_2_.D
// Type: Node_reg
BEGIN j2c_reg_cmdreg_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_6_.Q  	1
END

// Signal Name: j2c_reg_cmdreg_2_.C
// Type: Node_reg
BEGIN j2c_reg_cmdreg_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_cmdreg_2_.CE
// Type: Node_reg
BEGIN j2c_reg_cmdreg_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
END

// Signal Name: j2c_reg_cmdreg_2_.AP
// Type: Node_reg
BEGIN j2c_reg_cmdreg_2_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: j2c_reg_cmdreg_1_.D
// Type: Node_reg
BEGIN j2c_reg_cmdreg_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_5_.Q  	1
END

// Signal Name: j2c_reg_cmdreg_1_.C
// Type: Node_reg
BEGIN j2c_reg_cmdreg_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_cmdreg_1_.CE
// Type: Node_reg
BEGIN j2c_reg_cmdreg_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
END

// Signal Name: j2c_reg_cmdreg_1_.AP
// Type: Node_reg
BEGIN j2c_reg_cmdreg_1_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: nx1581
// Type: Node
BEGIN nx1581
Fanin Number		11
Pterm Number		6
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1388.BLIF         	4
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	nx1507.BLIF         	1
Fanin Node      	nx1615.BLIF         	4
Fanin Node      	nx1643.BLIF         	2
Fanin Node      	nx1673.BLIF         	3
Fanin Node      	ni_nires_reg_data_out_5_.Q	4
Fanin Node      	ni_nires_reg_data_out_6_.Q	4
Fanin Node      	ni_nires_reg_data_out_7_.Q	4
Fanin Node      	ni_nires_reg_data_out_8_.Q	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: ix71.X1
// Type: Node
BEGIN ix71.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1hm_6_.Q	1
Fanin Node      	j2c_reg_creg1hm_4_.Q	1
Fanin Node      	j2c_reg_creg1hm_0_.Q	4
END

// Signal Name: ix71.X2
// Type: Node
BEGIN ix71.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1hm_2_.Q	1
END

// Signal Name: ID_0_7_.T
// Type: Node_reg
BEGIN ID_0_7_.T
Fanin Number		7
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_6_.Q           	1
Fanin Node      	ID_0_5_.Q           	1
Fanin Node      	ID_0_4_.Q           	1
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_7_.C
// Type: Node_reg
BEGIN ID_0_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_7_.CE
// Type: Node_reg
BEGIN ID_0_7_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_0_7_.AR
// Type: Node_reg
BEGIN ID_0_7_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ID_0_6_.T
// Type: Node_reg
BEGIN ID_0_6_.T
Fanin Number		6
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_5_.Q           	1
Fanin Node      	ID_0_4_.Q           	1
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_6_.C
// Type: Node_reg
BEGIN ID_0_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_6_.CE
// Type: Node_reg
BEGIN ID_0_6_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_0_6_.AR
// Type: Node_reg
BEGIN ID_0_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: nx2471
// Type: Node
BEGIN nx2471
Fanin Number		7
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	FAULT.BLIF          	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_1_.Q 	1
Fanin Node      	ID_0_7_.Q           	1
Fanin Node      	j2c_bitcnt_2_.Q     	3
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
END

// Signal Name: ID_0_5_.T
// Type: Node_reg
BEGIN ID_0_5_.T
Fanin Number		5
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_4_.Q           	1
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_5_.C
// Type: Node_reg
BEGIN ID_0_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_5_.CE
// Type: Node_reg
BEGIN ID_0_5_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_0_5_.AR
// Type: Node_reg
BEGIN ID_0_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ID_0_4_.D.X1
// Type: Node_reg
BEGIN ID_0_4_.D.X1
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_4_.Q           	1
END

// Signal Name: ID_0_4_.D.X2
// Type: Node_reg
BEGIN ID_0_4_.D.X2
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_4_.C
// Type: Node_reg
BEGIN ID_0_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_4_.CE
// Type: Node_reg
BEGIN ID_0_4_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_0_4_.AR
// Type: Node_reg
BEGIN ID_0_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ID_0_3_.D
// Type: Node_reg
BEGIN ID_0_3_.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_3_.C
// Type: Node_reg
BEGIN ID_0_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_3_.CE
// Type: Node_reg
BEGIN ID_0_3_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_0_3_.AR
// Type: Node_reg
BEGIN ID_0_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ni_pattcount_2_.D
// Type: Node_reg
BEGIN ni_pattcount_2_.D
Fanin Number		3
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_pattcount_2_.Q   	3
Fanin Node      	ni_pattcount_1_.Q   	2
Fanin Node      	ni_pattcount_0_.Q   	1
END

// Signal Name: ni_pattcount_2_.C
// Type: Node_reg
BEGIN ni_pattcount_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_2_.D
// Type: Node_reg
BEGIN ID_0_2_.D
Fanin Number		3
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_2_.C
// Type: Node_reg
BEGIN ID_0_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_2_.CE
// Type: Node_reg
BEGIN ID_0_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_0_2_.AR
// Type: Node_reg
BEGIN ID_0_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ni_pattcount_1_.D
// Type: Node_reg
BEGIN ni_pattcount_1_.D
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_pattcount_1_.Q   	2
Fanin Node      	ni_pattcount_0_.Q   	1
END

// Signal Name: ni_pattcount_1_.C
// Type: Node_reg
BEGIN ni_pattcount_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_1_.D
// Type: Node_reg
BEGIN ID_0_1_.D
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_1_.C
// Type: Node_reg
BEGIN ID_0_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_1_.CE
// Type: Node_reg
BEGIN ID_0_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_0_1_.AR
// Type: Node_reg
BEGIN ID_0_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ni_pattcount_0_.D
// Type: Node_reg
BEGIN ni_pattcount_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_pattcount_0_.Q   	1
END

// Signal Name: ni_pattcount_0_.C
// Type: Node_reg
BEGIN ni_pattcount_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_0_.D
// Type: Node_reg
BEGIN ID_0_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_0_.C
// Type: Node_reg
BEGIN ID_0_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_0_.CE
// Type: Node_reg
BEGIN ID_0_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_0_0_.AR
// Type: Node_reg
BEGIN ID_0_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: nx1615
// Type: Node
BEGIN nx1615
Fanin Number		5
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	nx1643.BLIF         	2
Fanin Node      	ni_nires_reg_data_out_4_.Q	4
Fanin Node      	ni_nires_reg_data_out_5_.Q	4
Fanin Node      	ix1082.BLIF         	4
END

// Signal Name: j2c_reg_clear.D
// Type: Node_reg
BEGIN j2c_reg_clear.D
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_bitcnt_2_.Q     	3
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
END

// Signal Name: j2c_reg_clear.C
// Type: Node_reg
BEGIN j2c_reg_clear.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_clear.CE
// Type: Node_reg
BEGIN j2c_reg_clear.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	j2c_reg_clear_0.BLIF	2
END

// Signal Name: j2c_reg_clear.AR
// Type: Node_reg
BEGIN j2c_reg_clear.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: ni_pattcount_4_.D.X1
// Type: Node_reg
BEGIN ni_pattcount_4_.D.X1
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_pattcount_2_.Q   	3
Fanin Node      	ni_pattcount_1_.Q   	2
Fanin Node      	ni_pattcount_0_.Q   	1
Fanin Node      	ni_pattcount_3_.Q   	4
END

// Signal Name: ni_pattcount_4_.D.X2
// Type: Node_reg
BEGIN ni_pattcount_4_.D.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_pattcount_4_.Q   	1
END

// Signal Name: ni_pattcount_4_.C
// Type: Node_reg
BEGIN ni_pattcount_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_pattcount_3_.D
// Type: Node_reg
BEGIN ni_pattcount_3_.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_pattcount_2_.Q   	3
Fanin Node      	ni_pattcount_1_.Q   	2
Fanin Node      	ni_pattcount_0_.Q   	1
Fanin Node      	ni_pattcount_3_.Q   	4
END

// Signal Name: ni_pattcount_3_.C
// Type: Node_reg
BEGIN ni_pattcount_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: nx1643
// Type: Node
BEGIN nx1643
Fanin Number		3
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: ni_nires_reg_valid.D
// Type: Node_reg
BEGIN ni_nires_reg_valid.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_new_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_new_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_valid.C
// Type: Node_reg
BEGIN ni_nires_reg_valid.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_new_cnt_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_new_cnt_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
END

// Signal Name: ni_nires_reg_new_cnt_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_new_cnt_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_new_cnt_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_new_cnt_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ni_nires_reg_gray_cntf_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_gray_cntf_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_gray_cntf_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_gray_cntf_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_gray_cntf_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_gray_cntf_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ni_nires_reg_gray_cntf_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_gray_cntf_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
END

// Signal Name: ni_nires_reg_gray_cntf_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_gray_cntf_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_gray_cntf_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_gray_cntf_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ni_nires_reg_clear_n_i.D
// Type: Node_reg
BEGIN ni_nires_reg_clear_n_i.D
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	reset_n.BLIF        	0
Fanin Node      	j2c_reg_rstout_n_i.Q	1
END

// Signal Name: ni_nires_reg_clear_n_i.C
// Type: Node_reg
BEGIN ni_nires_reg_clear_n_i.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_6_.T
// Type: Node_reg
BEGIN ID_2_6_.T
Fanin Number		6
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_5_.Q           	1
Fanin Node      	ID_2_4_.Q           	1
Fanin Node      	ID_2_3_.Q           	4
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
END

// Signal Name: ID_2_6_.C
// Type: Node_reg
BEGIN ID_2_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_6_.CE-
// Type: Node_reg
BEGIN ID_2_6_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_2_6__0.BLIF      	2
END

// Signal Name: ID_2_6_.AR
// Type: Node_reg
BEGIN ID_2_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: nx1673.X1
// Type: Node
BEGIN nx1673.X1
Fanin Number		6
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ni_nires_reg_data_out_6_.Q	4
Fanin Node      	ni_nires_reg_data_out_7_.Q	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: nx1673.X2
// Type: Node
BEGIN nx1673.X2
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_data_out_7_.Q	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: j2c_reg_rstout_n_i.D
// Type: Node_reg
BEGIN j2c_reg_rstout_n_i.D
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_bitcnt_2_.Q     	3
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
END

// Signal Name: j2c_reg_rstout_n_i.C
// Type: Node_reg
BEGIN j2c_reg_rstout_n_i.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_rstout_n_i.CE
// Type: Node_reg
BEGIN j2c_reg_rstout_n_i.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	j2c_reg_clear_0.BLIF	2
END

// Signal Name: j2c_reg_rstout_n_i.AP
// Type: Node_reg
BEGIN j2c_reg_rstout_n_i.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: ni_reg_ce_prty_bit_neg.D
// Type: Node_reg
BEGIN ni_reg_ce_prty_bit_neg.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Output    	TX_EN.Q             	2
Fanin Output    	TXD_8_.Q            	9
Fanin Node      	ix1695.BLIF         	4
Fanin Node      	ix1701.BLIF         	4
END

// Signal Name: ni_reg_ce_prty_bit_neg.C
// Type: Node_reg
BEGIN ni_reg_ce_prty_bit_neg.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: j2c_bitcnt_2_.D
// Type: Node_reg
BEGIN j2c_bitcnt_2_.D
Fanin Number		3
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_bitcnt_2_.Q     	3
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
END

// Signal Name: j2c_bitcnt_2_.C
// Type: Node_reg
BEGIN j2c_bitcnt_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_bitcnt_2_.AR
// Type: Node_reg
BEGIN j2c_bitcnt_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: ni_reg_prty_bit_neg_r.D
// Type: Node_reg
BEGIN ni_reg_prty_bit_neg_r.D
Fanin Number		22
Pterm Number		16
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		5
Fanin Node      	ni_nires_reg_data_out_10_.Q	4
Fanin Node      	ni_nires_reg_data_out_12_.Q	4
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ni_nires_reg_data_out_13_.Q	4
Fanin Node      	ni_nires_reg_data_out_14_.Q	4
Fanin Node      	nx1383.BLIF         	1
Fanin Node      	ix1388.BLIF         	4
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	ix1460.BLIF         	4
Fanin Node      	ix1472.BLIF         	4
Fanin Node      	ni_nires_reg_data_out_17_.Q	4
Fanin Node      	ni_nires_reg_data_out_18_.Q	4
Fanin Node      	nx1507.BLIF         	1
Fanin Node      	nx1769.BLIF         	2
Fanin Node      	nx2057.BLIF         	3
Fanin Node      	nx2130.BLIF         	4
Fanin Node      	nx2166.BLIF         	3
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	nx2188.BLIF         	2
Fanin Node      	ni_nires_reg_data_out_11_.Q	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: ni_reg_prty_bit_neg_r.C
// Type: Node_reg
BEGIN ni_reg_prty_bit_neg_r.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: j2c_bitcnt_1_.D
// Type: Node_reg
BEGIN j2c_bitcnt_1_.D
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
END

// Signal Name: j2c_bitcnt_1_.C
// Type: Node_reg
BEGIN j2c_bitcnt_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_bitcnt_1_.AR
// Type: Node_reg
BEGIN j2c_bitcnt_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_bitcnt_0_.D
// Type: Node_reg
BEGIN j2c_bitcnt_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_bitcnt_0_.Q     	1
END

// Signal Name: j2c_bitcnt_0_.C
// Type: Node_reg
BEGIN j2c_bitcnt_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_bitcnt_0_.AR
// Type: Node_reg
BEGIN j2c_bitcnt_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: ix1695.X1
// Type: Node
BEGIN ix1695.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_14_.Q           	7
Fanin Output    	TXD_13_.Q           	6
Fanin Node      	ni_reg_prty_bit_neg_r.Q	16
END

// Signal Name: ix1695.X2
// Type: Node
BEGIN ix1695.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_15_.Q           	4
END

// Signal Name: ix1701.X1
// Type: Node
BEGIN ix1701.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_11_.Q           	6
Fanin Output    	TXD_10_.Q           	13
Fanin Output    	TXD_9_.Q            	8
END

// Signal Name: ix1701.X2
// Type: Node
BEGIN ix1701.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_12_.Q           	5
END

// Signal Name: ID_2_5_.T
// Type: Node_reg
BEGIN ID_2_5_.T
Fanin Number		5
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_4_.Q           	1
Fanin Node      	ID_2_3_.Q           	4
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
END

// Signal Name: ID_2_5_.C
// Type: Node_reg
BEGIN ID_2_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_5_.CE-
// Type: Node_reg
BEGIN ID_2_5_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_2_6__0.BLIF      	2
END

// Signal Name: ID_2_5_.AR
// Type: Node_reg
BEGIN ID_2_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ni_nires_reg_old_cnt_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_old_cnt_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_old_cnt_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx977.BLIF          	4
END

// Signal Name: ni_nires_reg_old_cnt_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ID_2_4_.D.X1
// Type: Node_reg
BEGIN ID_2_4_.D.X1
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_4_.Q           	1
END

// Signal Name: ID_2_4_.D.X2
// Type: Node_reg
BEGIN ID_2_4_.D.X2
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_3_.Q           	4
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
END

// Signal Name: ID_2_4_.C
// Type: Node_reg
BEGIN ID_2_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_4_.CE-
// Type: Node_reg
BEGIN ID_2_4_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_2_6__0.BLIF      	2
END

// Signal Name: ID_2_4_.AR
// Type: Node_reg
BEGIN ID_2_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: nx977
// Type: Node
BEGIN nx977
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_new_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_new_cnt_1_.Q	1
END

// Signal Name: ID_2_3_.D
// Type: Node_reg
BEGIN ID_2_3_.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_3_.Q           	4
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
END

// Signal Name: ID_2_3_.C
// Type: Node_reg
BEGIN ID_2_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_3_.CE-
// Type: Node_reg
BEGIN ID_2_3_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_2_6__0.BLIF      	2
END

// Signal Name: ID_2_3_.AR
// Type: Node_reg
BEGIN ID_2_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ni_nires_reg_old_cnt_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_old_cnt_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_old_cnt_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx977.BLIF          	4
END

// Signal Name: ni_nires_reg_old_cnt_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ID_2_2_.D
// Type: Node_reg
BEGIN ID_2_2_.D
Fanin Number		3
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
END

// Signal Name: ID_2_2_.C
// Type: Node_reg
BEGIN ID_2_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_2_.CE-
// Type: Node_reg
BEGIN ID_2_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_2_6__0.BLIF      	2
END

// Signal Name: ID_2_2_.AR
// Type: Node_reg
BEGIN ID_2_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ID_2_1_.D
// Type: Node_reg
BEGIN ID_2_1_.D
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
END

// Signal Name: ID_2_1_.C
// Type: Node_reg
BEGIN ID_2_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_1_.CE-
// Type: Node_reg
BEGIN ID_2_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_2_6__0.BLIF      	2
END

// Signal Name: ID_2_1_.AR
// Type: Node_reg
BEGIN ID_2_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ID_2_0_.D
// Type: Node_reg
BEGIN ID_2_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_0_.Q           	1
END

// Signal Name: ID_2_0_.C
// Type: Node_reg
BEGIN ID_2_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_0_.CE-
// Type: Node_reg
BEGIN ID_2_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_2_6__0.BLIF      	2
END

// Signal Name: ID_2_0_.AR
// Type: Node_reg
BEGIN ID_2_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ni_nires_reg_new_cnt_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_new_cnt_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_new_cnt_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_new_cnt_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_new_cnt_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_new_cnt_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: nx240
// Type: Node
BEGIN nx240
Fanin Number		3
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx1289.BLIF         	1
Fanin Output    	TX_EN.Q             	2
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: ni_nires_reg_data_out_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_1_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_1_.Q	1
Fanin Node      	ni_nires_reg_data3neg_1_.Q	1
Fanin Node      	ni_nires_reg_data0neg_1_.Q	1
Fanin Node      	ni_nires_reg_data1neg_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2neg_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: nx1769
// Type: Node
BEGIN nx1769
Fanin Number		4
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: ni_nires_reg_data0neg_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ID_3_6_.T
// Type: Node_reg
BEGIN ID_3_6_.T
Fanin Number		6
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_5_.Q           	1
Fanin Node      	ID_3_4_.Q           	1
Fanin Node      	ID_3_3_.Q           	4
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
END

// Signal Name: ID_3_6_.C
// Type: Node_reg
BEGIN ID_3_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_6_.CE-
// Type: Node_reg
BEGIN ID_3_6_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_3_6__0.BLIF      	2
END

// Signal Name: ID_3_6_.AR
// Type: Node_reg
BEGIN ID_3_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ni_reg_ce_prty_bit_pos.D.X1
// Type: Node_reg
BEGIN ni_reg_ce_prty_bit_pos.D.X1
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Output    	TX_EN.Q             	2
Fanin Node      	ix1823.BLIF         	4
Fanin Node      	ix1825.BLIF         	2
Fanin Node      	ix1827.BLIF         	2
END

// Signal Name: ni_reg_ce_prty_bit_pos.D.X2
// Type: Node_reg
BEGIN ni_reg_ce_prty_bit_pos.D.X2
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
Fanin Output    	TXD_0_.Q            	9
END

// Signal Name: ni_reg_ce_prty_bit_pos.C
// Type: Node_reg
BEGIN ni_reg_ce_prty_bit_pos.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_reg_prty_bit_pos_r.D
// Type: Node_reg
BEGIN ni_reg_prty_bit_pos_r.D
Fanin Number		18
Pterm Number		12
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		6
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	nx1383.BLIF         	1
Fanin Node      	ix1388.BLIF         	4
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	ix1460.BLIF         	4
Fanin Node      	ix1472.BLIF         	4
Fanin Node      	nx1507.BLIF         	1
Fanin Node      	nx1525.BLIF         	3
Fanin Node      	nx1581.BLIF         	6
Fanin Node      	ni_nires_reg_data_out_1_.Q	4
Fanin Node      	nx1769.BLIF         	2
Fanin Node      	ni_nires_reg_data_out_0_.Q	4
Fanin Node      	ni_nires_reg_data_out_2_.Q	4
Fanin Node      	ni_nires_reg_data_out_3_.Q	4
Fanin Node      	ni_nires_reg_data_out_4_.Q	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: ni_reg_prty_bit_pos_r.C
// Type: Node_reg
BEGIN ni_reg_prty_bit_pos_r.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_0_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_0_.Q	1
Fanin Node      	ni_nires_reg_data3neg_0_.Q	1
Fanin Node      	ni_nires_reg_data0neg_0_.Q	1
Fanin Node      	ni_nires_reg_data1neg_0_.Q	1
END

// Signal Name: ni_nires_reg_data_out_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2neg_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ix1823.X1
// Type: Node
BEGIN ix1823.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_6_.Q            	7
Fanin Output    	TXD_5_.Q            	8
Fanin Node      	ni_reg_prty_bit_pos_r.Q	12
END

// Signal Name: ix1823.X2
// Type: Node
BEGIN ix1823.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_7_.Q            	4
END

// Signal Name: ni_nires_reg_data1neg_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ix1825
// Type: Node
BEGIN ix1825
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_4_.Q            	7
Fanin Output    	TXD_3_.Q            	6
END

// Signal Name: ix1827
// Type: Node
BEGIN ix1827
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_2_.Q            	13
Fanin Output    	TXD_1_.Q            	8
END

// Signal Name: j2c_reg_creg0hm_4_.D
// Type: Node_reg
BEGIN j2c_reg_creg0hm_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_1_.Q  	1
END

// Signal Name: j2c_reg_creg0hm_4_.C
// Type: Node_reg
BEGIN j2c_reg_creg0hm_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg0hm_4_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0hm_4_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg0hm_4_.AR
// Type: Node_reg
BEGIN j2c_reg_creg0hm_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: j2c_reg_shreg_1_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_2_.Q  	1
END

// Signal Name: j2c_reg_shreg_1_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_shreg_2_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_3_.Q  	1
END

// Signal Name: j2c_reg_shreg_2_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_shreg_3_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_4_.Q  	1
END

// Signal Name: j2c_reg_shreg_3_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_creg0hm_6_.D
// Type: Node_reg
BEGIN j2c_reg_creg0hm_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_3_.Q  	1
END

// Signal Name: j2c_reg_creg0hm_6_.C
// Type: Node_reg
BEGIN j2c_reg_creg0hm_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg0hm_6_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0hm_6_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg0hm_6_.AP
// Type: Node_reg
BEGIN j2c_reg_creg0hm_6_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ID_3_5_.T
// Type: Node_reg
BEGIN ID_3_5_.T
Fanin Number		5
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_4_.Q           	1
Fanin Node      	ID_3_3_.Q           	4
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
END

// Signal Name: ID_3_5_.C
// Type: Node_reg
BEGIN ID_3_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_5_.CE-
// Type: Node_reg
BEGIN ID_3_5_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_3_6__0.BLIF      	2
END

// Signal Name: ID_3_5_.AR
// Type: Node_reg
BEGIN ID_3_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: j2c_reg_creg0hm_5_.D
// Type: Node_reg
BEGIN j2c_reg_creg0hm_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_2_.Q  	1
END

// Signal Name: j2c_reg_creg0hm_5_.C
// Type: Node_reg
BEGIN j2c_reg_creg0hm_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg0hm_5_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0hm_5_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg0hm_5_.AR
// Type: Node_reg
BEGIN j2c_reg_creg0hm_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: j2c_reg_creg0hm_2_.D
// Type: Node_reg
BEGIN j2c_reg_creg0hm_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_0_.Q  	1
END

// Signal Name: j2c_reg_creg0hm_2_.C
// Type: Node_reg
BEGIN j2c_reg_creg0hm_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg0hm_2_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0hm_2_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg0hm_2_.AP
// Type: Node_reg
BEGIN j2c_reg_creg0hm_2_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ID_3_4_.D.X1
// Type: Node_reg
BEGIN ID_3_4_.D.X1
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_4_.Q           	1
END

// Signal Name: ID_3_4_.D.X2
// Type: Node_reg
BEGIN ID_3_4_.D.X2
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_3_.Q           	4
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
END

// Signal Name: ID_3_4_.C
// Type: Node_reg
BEGIN ID_3_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_4_.CE-
// Type: Node_reg
BEGIN ID_3_4_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_3_6__0.BLIF      	2
END

// Signal Name: ID_3_4_.AR
// Type: Node_reg
BEGIN ID_3_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: j2c_reg_shreg_0_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_1_.Q  	1
END

// Signal Name: j2c_reg_shreg_0_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: ID_3_3_.D
// Type: Node_reg
BEGIN ID_3_3_.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_3_.Q           	4
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
END

// Signal Name: ID_3_3_.C
// Type: Node_reg
BEGIN ID_3_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_3_.CE-
// Type: Node_reg
BEGIN ID_3_3_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_3_6__0.BLIF      	2
END

// Signal Name: ID_3_3_.AR
// Type: Node_reg
BEGIN ID_3_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: j2c_reg_creg0hm_1_.D
// Type: Node_reg
BEGIN j2c_reg_creg0hm_1_.D
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_2_.Q  	1
Fanin Node      	j2c_reg_shreg_3_.Q  	1
Fanin Node      	j2c_reg_shreg_0_.Q  	1
END

// Signal Name: j2c_reg_creg0hm_1_.C
// Type: Node_reg
BEGIN j2c_reg_creg0hm_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg0hm_1_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0hm_1_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg0hm_1_.AR
// Type: Node_reg
BEGIN j2c_reg_creg0hm_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ID_3_2_.D
// Type: Node_reg
BEGIN ID_3_2_.D
Fanin Number		3
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
END

// Signal Name: ID_3_2_.C
// Type: Node_reg
BEGIN ID_3_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_2_.CE-
// Type: Node_reg
BEGIN ID_3_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_3_6__0.BLIF      	2
END

// Signal Name: ID_3_2_.AR
// Type: Node_reg
BEGIN ID_3_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ID_3_1_.D
// Type: Node_reg
BEGIN ID_3_1_.D
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
END

// Signal Name: ID_3_1_.C
// Type: Node_reg
BEGIN ID_3_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_1_.CE-
// Type: Node_reg
BEGIN ID_3_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_3_6__0.BLIF      	2
END

// Signal Name: ID_3_1_.AR
// Type: Node_reg
BEGIN ID_3_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ID_3_0_.D
// Type: Node_reg
BEGIN ID_3_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_0_.Q           	1
END

// Signal Name: ID_3_0_.C
// Type: Node_reg
BEGIN ID_3_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_0_.CE-
// Type: Node_reg
BEGIN ID_3_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_3_6__0.BLIF      	2
END

// Signal Name: ID_3_0_.AR
// Type: Node_reg
BEGIN ID_3_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: nx1841
// Type: Node
BEGIN nx1841
Fanin Number		5
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx1289.BLIF         	1
Fanin Node      	ix1388.BLIF         	4
Fanin Node      	ix1438.BLIF         	4
Fanin Node      	nx1457.BLIF         	1
Fanin Node      	ix1472.BLIF         	4
END

// Signal Name: ix369.X1
// Type: Node
BEGIN ix369.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0hm_5_.Q	1
Fanin Node      	j2c_reg_creg0hm_2_.Q	1
Fanin Node      	j2c_reg_creg0hm_1_.Q	4
END

// Signal Name: ix369.X2
// Type: Node
BEGIN ix369.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0hm_6_.Q	1
END

// Signal Name: j2c_reg_creg0hm_3_.D
// Type: Node_reg
BEGIN j2c_reg_creg0hm_3_.D
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_1_.Q  	1
Fanin Node      	j2c_reg_shreg_2_.Q  	1
Fanin Node      	j2c_reg_shreg_3_.Q  	1
END

// Signal Name: j2c_reg_creg0hm_3_.C
// Type: Node_reg
BEGIN j2c_reg_creg0hm_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg0hm_3_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0hm_3_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg0hm_3_.AP
// Type: Node_reg
BEGIN j2c_reg_creg0hm_3_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ix381.X1
// Type: Node
BEGIN ix381.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0hm_6_.Q	1
Fanin Node      	j2c_reg_creg0hm_5_.Q	1
Fanin Node      	j2c_reg_creg0hm_3_.Q	4
END

// Signal Name: ix381.X2
// Type: Node
BEGIN ix381.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0hm_4_.Q	1
END

// Signal Name: j2c_reg_creg0hm_0_.D
// Type: Node_reg
BEGIN j2c_reg_creg0hm_0_.D
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_1_.Q  	1
Fanin Node      	j2c_reg_shreg_3_.Q  	1
Fanin Node      	j2c_reg_shreg_0_.Q  	1
END

// Signal Name: j2c_reg_creg0hm_0_.C
// Type: Node_reg
BEGIN j2c_reg_creg0hm_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx0.BLIF            	1
END

// Signal Name: j2c_reg_creg0hm_0_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0hm_0_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
END

// Signal Name: j2c_reg_creg0hm_0_.AR
// Type: Node_reg
BEGIN j2c_reg_creg0hm_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ix393.X1
// Type: Node
BEGIN ix393.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0hm_6_.Q	1
Fanin Node      	j2c_reg_creg0hm_2_.Q	1
Fanin Node      	j2c_reg_creg0hm_0_.Q	4
END

// Signal Name: ix393.X2
// Type: Node
BEGIN ix393.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0hm_4_.Q	1
END

// Signal Name: ID_1_6_.T
// Type: Node_reg
BEGIN ID_1_6_.T
Fanin Number		7
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx2401.BLIF         	1
Fanin Node      	ID_1_5_.Q           	1
Fanin Node      	ID_1_4_.Q           	1
Fanin Node      	ID_1_3_.Q           	1
Fanin Node      	ID_1_2_.Q           	4
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
END

// Signal Name: ID_1_6_.C
// Type: Node_reg
BEGIN ID_1_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_6_.CE
// Type: Node_reg
BEGIN ID_1_6_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_1_6_.AR
// Type: Node_reg
BEGIN ID_1_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ID_1_5_.T
// Type: Node_reg
BEGIN ID_1_5_.T
Fanin Number		6
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx2401.BLIF         	1
Fanin Node      	ID_1_4_.Q           	1
Fanin Node      	ID_1_3_.Q           	1
Fanin Node      	ID_1_2_.Q           	4
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
END

// Signal Name: ID_1_5_.C
// Type: Node_reg
BEGIN ID_1_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_5_.CE
// Type: Node_reg
BEGIN ID_1_5_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_1_5_.AR
// Type: Node_reg
BEGIN ID_1_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ID_1_4_.T
// Type: Node_reg
BEGIN ID_1_4_.T
Fanin Number		5
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx2401.BLIF         	1
Fanin Node      	ID_1_3_.Q           	1
Fanin Node      	ID_1_2_.Q           	4
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
END

// Signal Name: ID_1_4_.C
// Type: Node_reg
BEGIN ID_1_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_4_.CE
// Type: Node_reg
BEGIN ID_1_4_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_1_4_.AR
// Type: Node_reg
BEGIN ID_1_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ID_1_3_.D.X1
// Type: Node_reg
BEGIN ID_1_3_.D.X1
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_1_3_.Q           	1
END

// Signal Name: ID_1_3_.D.X2
// Type: Node_reg
BEGIN ID_1_3_.D.X2
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx2401.BLIF         	1
Fanin Node      	ID_1_2_.Q           	4
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
END

// Signal Name: ID_1_3_.C
// Type: Node_reg
BEGIN ID_1_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_3_.CE
// Type: Node_reg
BEGIN ID_1_3_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_1_3_.AR
// Type: Node_reg
BEGIN ID_1_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ID_1_2_.D
// Type: Node_reg
BEGIN ID_1_2_.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx2401.BLIF         	1
Fanin Node      	ID_1_2_.Q           	4
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
END

// Signal Name: ID_1_2_.C
// Type: Node_reg
BEGIN ID_1_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_2_.CE
// Type: Node_reg
BEGIN ID_1_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_1_2_.AR
// Type: Node_reg
BEGIN ID_1_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ID_1_1_.D
// Type: Node_reg
BEGIN ID_1_1_.D
Fanin Number		3
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx2401.BLIF         	1
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
END

// Signal Name: ID_1_1_.C
// Type: Node_reg
BEGIN ID_1_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_1_.CE
// Type: Node_reg
BEGIN ID_1_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_1_1_.AR
// Type: Node_reg
BEGIN ID_1_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ni_nires_reg_data_out_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_2_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_2_.Q	1
Fanin Node      	ni_nires_reg_data3neg_2_.Q	1
Fanin Node      	ni_nires_reg_data0neg_2_.Q	1
Fanin Node      	ni_nires_reg_data1neg_2_.Q	1
END

// Signal Name: ni_nires_reg_data_out_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_0_.D
// Type: Node_reg
BEGIN ID_1_0_.D
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx2401.BLIF         	1
Fanin Node      	ID_1_0_.Q           	2
END

// Signal Name: ID_1_0_.C
// Type: Node_reg
BEGIN ID_1_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_0_.CE
// Type: Node_reg
BEGIN ID_1_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	2
END

// Signal Name: ID_1_0_.AR
// Type: Node_reg
BEGIN ID_1_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_clear.Q     	1
END

// Signal Name: ni_nires_reg_data2neg_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_3_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_3_.Q	1
Fanin Node      	ni_nires_reg_data3neg_3_.Q	1
Fanin Node      	ni_nires_reg_data0neg_3_.Q	1
Fanin Node      	ni_nires_reg_data1neg_3_.Q	1
END

// Signal Name: ni_nires_reg_data_out_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2neg_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_4_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_4_.Q	1
Fanin Node      	ni_nires_reg_data3neg_4_.Q	1
Fanin Node      	ni_nires_reg_data0neg_4_.Q	1
Fanin Node      	ni_nires_reg_data1neg_4_.Q	1
END

// Signal Name: ni_nires_reg_data_out_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2neg_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: nx2062
// Type: Node
BEGIN nx2062
Fanin Number		15
Pterm Number		11
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	FAULT.BLIF          	0
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	j2c_bitcnt_2_.Q     	3
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
Fanin Node      	ID_2_5_.Q           	1
Fanin Node      	ID_2_4_.Q           	1
Fanin Node      	ID_2_3_.Q           	4
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
Fanin Node      	ID_3_5_.Q           	1
Fanin Node      	ID_3_4_.Q           	1
Fanin Node      	ID_3_3_.Q           	4
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
END

// Signal Name: ni_nires_reg_data0neg_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: nx2057.X1
// Type: Node
BEGIN nx2057.X1
Fanin Number		6
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ni_nires_reg_data_out_18_.Q	4
Fanin Node      	ni_nires_reg_data_out_19_.Q	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: nx2057.X2
// Type: Node
BEGIN nx2057.X2
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_data_out_18_.Q	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: ni_nires_reg_data_out_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_5_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_5_.Q	1
Fanin Node      	ni_nires_reg_data3neg_5_.Q	1
Fanin Node      	ni_nires_reg_data0neg_5_.Q	1
Fanin Node      	ni_nires_reg_data1neg_5_.Q	1
END

// Signal Name: ni_nires_reg_data_out_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2neg_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_6_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_6_.Q	1
Fanin Node      	ni_nires_reg_data3neg_6_.Q	1
Fanin Node      	ni_nires_reg_data0neg_6_.Q	1
Fanin Node      	ni_nires_reg_data1neg_6_.Q	1
END

// Signal Name: ni_nires_reg_data_out_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2neg_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_7_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_7_.Q	1
Fanin Node      	ni_nires_reg_data3neg_7_.Q	1
Fanin Node      	ni_nires_reg_data0neg_7_.Q	1
Fanin Node      	ni_nires_reg_data1neg_7_.Q	1
END

// Signal Name: ni_nires_reg_data_out_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2neg_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: nx2130
// Type: Node
BEGIN nx2130
Fanin Number		5
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ni_nires_reg_data_out_14_.Q	4
Fanin Node      	ni_nires_reg_data_out_15_.Q	4
Fanin Node      	nx1643.BLIF         	2
Fanin Node      	ix1082.BLIF         	4
END

// Signal Name: ni_nires_reg_data_out_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_8_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_8_.Q	1
Fanin Node      	ni_nires_reg_data3neg_8_.Q	1
Fanin Node      	ni_nires_reg_data0neg_8_.Q	1
Fanin Node      	ni_nires_reg_data1neg_8_.Q	1
END

// Signal Name: ni_nires_reg_data_out_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2neg_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: nx2166.X1
// Type: Node
BEGIN nx2166.X1
Fanin Number		6
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ix1284.BLIF         	4
Fanin Node      	ni_nires_reg_data_out_16_.Q	4
Fanin Node      	ni_nires_reg_data_out_17_.Q	4
Fanin Node      	ix1082.BLIF         	4
Fanin Node      	ix1160.BLIF         	4
Fanin Node      	ix1164.BLIF         	4
END

// Signal Name: nx2166.X2
// Type: Node
BEGIN nx2166.X2
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_data_out_17_.Q	4
Fanin Node      	ix1160.BLIF         	4
END

// Signal Name: ni_nires_reg_data_out_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_9_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_9_.Q	1
Fanin Node      	ni_nires_reg_data3neg_9_.Q	1
Fanin Node      	ni_nires_reg_data0neg_9_.Q	1
Fanin Node      	ni_nires_reg_data1neg_9_.Q	1
END

// Signal Name: ni_nires_reg_data_out_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2neg_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ix1082
// Type: Node
BEGIN ix1082
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1hm_5_.Q	1
Fanin Node      	ix47.BLIF           	4
Fanin Node      	ix59.BLIF           	4
Fanin Node      	ix71.BLIF           	4
END

// Signal Name: nx2188
// Type: Node
BEGIN nx2188
Fanin Number		3
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_data_out_15_.Q	4
Fanin Node      	ni_nires_reg_data_out_16_.Q	4
Fanin Node      	nx1643.BLIF         	2
END

// Signal Name: ni_nires_reg_data_out_11_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_11_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_data0pos_1_.Q	1
Fanin Node      	ni_nires_reg_data1pos_1_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2pos_1_.Q	1
Fanin Node      	ni_nires_reg_data3pos_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_11_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_11_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data2pos_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_gray_cnt_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_gray_cnt_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_gray_cnt_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_gray_cnt_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_gray_cnt_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_gray_cnt_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ni_nires_reg_gray_cnt_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_gray_cnt_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_gray_cnt_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_gray_cnt_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_gray_cnt_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_gray_cnt_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ix1160
// Type: Node
BEGIN ix1160
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1hm_6_.Q	1
Fanin Node      	ix47.BLIF           	4
Fanin Node      	ix59.BLIF           	4
Fanin Node      	ix71.BLIF           	4
END

// Signal Name: ix1164
// Type: Node
BEGIN ix1164
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1hm_4_.Q	1
Fanin Node      	ix47.BLIF           	4
Fanin Node      	ix59.BLIF           	4
Fanin Node      	ix71.BLIF           	4
END

// Signal Name: ni_nires_reg_data3pos_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: j2c_reg_clear_0
// Type: Node
BEGIN j2c_reg_clear_0
Fanin Number		4
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_bitcnt_2_.Q     	3
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
END

// Signal Name: ID_2_6__0
// Type: Node
BEGIN ID_2_6__0
Fanin Number		8
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_6_.Q           	1
Fanin Node      	ni_reg_ce_prty_bit_neg.Q	4
Fanin Node      	ID_2_5_.Q           	1
Fanin Node      	ID_2_4_.Q           	1
Fanin Node      	ID_2_3_.Q           	4
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
END

// Signal Name: ID_3_6__0
// Type: Node
BEGIN ID_3_6__0
Fanin Number		8
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_3_6_.Q           	1
Fanin Node      	ni_reg_ce_prty_bit_pos.Q	4
Fanin Node      	ID_3_5_.Q           	1
Fanin Node      	ID_3_4_.Q           	1
Fanin Node      	ID_3_3_.Q           	4
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
END

// Design 'top_ni' used clock signal list:
CLOCK	clk
CLOCK	NI_STR
CLOCK	jTCK