ispLEVER 5.0.01.73.31.05_Starter Fitter Report File
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Project Name : oase Project Path : U:\REFERENCE\SIM\PROJECTS\ORI\lattice_final_pinout Project Fitted on : Thu May 18 11:26:00 2006 Device : M4256_64 Package : 100 GLB Input Mux Size : 33 Available Blocks : 16 Speed : -3 Part Number : LC4256V-3T100C Source Format : EDIF Project 'oase' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.14 secs Partition Time 4.95 secs Place Time 0.70 secs Route Time 0.41 secs Total Fit Time 00:00:06 Design_Summary
Total Input Pins 19 Total Logic Functions 256 Total Output Pins 25 Total Bidir I/O Pins 3 Total Buried Nodes 228 Total Flip-Flops 196 Total D Flip-Flops 186 Total T Flip-Flops 10 Total Latches 0 Total Product Terms 1060 Total Reserved Pins 1 Total Locked Pins 47 Total Locked Nodes 0 Total Unique Output Enables 3 Total Unique Clocks 6 Total Unique Clock Enables 16 Total Unique Resets 4 Total Unique Presets 2 Fmax Logic Levels 6 Device_Resource_Summary
Device Total Used Not Used Utilization ----------------------------------------------------------------------- Dedicated Pins Clock/Input Pins 4 2 2 --> 50 Input-Only Pins 6 0 6 --> 0 I/O / Enable Pins 2 1 1 --> 50 I/O Pins 62 44 18 --> 70 Logic Functions 256 256 0 --> 100 Input Registers 64 0 64 --> 0 GLB Inputs 576 516 60 --> 89 Logical Product Terms 1280 865 415 --> 67 Occupied GLBs 16 16 0 --> 100 Macrocells 256 256 0 --> 100 Product Terms 1316 865 451 --> 65 Control Product Terms: GLB Clock/Clock Enables 16 16 0 --> 100 GLB Reset/Presets 16 0 16 --> 0 Macrocell Clocks 256 39 217 --> 15 Macrocell Clock Enables 256 146 110 --> 57 Macrocell Enables 256 0 256 --> 0 Macrocell Resets 256 8 248 --> 3 Macrocell Presets 256 0 256 --> 0 Global Routing Pool 324 264 60 --> 81 GRP from IFB .. 19 .. --> .. (from input signals) .. 18 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 1 .. --> .. GRP from MFB .. 245 .. --> .. ---------------------------------------------------------------------- <Note> 1 : The available PT is the product term that has not been used. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT --- Fanin --- I/O Input Macrocells Macrocells Logic clusters Unique Shared Total Pins Regs Used Inaccessible available PTs used ------------------------------------------------------------------------------------------- Maximum GLB 36 *(1) 8 -- -- 16 80 16 ------------------------------------------------------------------------------------------- GLB A 24 9 33 0/4 0 16 0 0 50 16 GLB B 21 8 29 4/4 0 16 0 0 37 15 GLB C 17 17 34 3/4 0 16 0 0 53 15 GLB D 21 13 34 4/4 0 16 0 0 59 15 ------------------------------------------------------------------------------------------- GLB E 14 19 33 4/4 0 16 0 0 63 16 GLB F 16 17 33 3/4 0 16 0 0 53 15 GLB G 18 16 34 0/4 0 16 0 0 55 15 GLB H 17 12 29 0/4 0 16 0 0 57 16 ------------------------------------------------------------------------------------------- GLB I 5 19 24 1/4 0 16 0 0 47 16 GLB J 19 14 33 4/4 0 16 0 0 45 15 GLB K 15 19 34 4/4 0 16 0 0 47 15 GLB L 7 27 34 4/4 0 16 0 0 70 16 ------------------------------------------------------------------------------------------- GLB M 14 19 33 4/4 0 16 0 0 58 16 GLB N 10 26 36 4/4 0 16 0 0 67 16 GLB O 15 19 34 4/4 0 16 0 0 61 16 GLB P 18 11 29 1/4 0 16 0 0 43 16 ------------------------------------------------------------------------------------------- TOTALS: 251 265 516 44/64 0 256 0 0 865 249 <Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Rst/Pr | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 16 16 16 16 16 ============================================================================== GLB A 1 0 6 10 0 0 0 GLB B 1 0 5 10 0 2 0 GLB C 1 0 0 0 0 0 0 GLB D 1 0 1 2 0 0 0 ------------------------------------------------------------------------------ GLB E 1 0 0 13 0 0 0 GLB F 1 0 0 7 0 0 0 GLB G 1 0 0 7 0 5 0 GLB H 1 0 4 10 0 0 0 ------------------------------------------------------------------------------ GLB I 1 0 0 11 0 0 0 GLB J 1 0 1 4 0 0 0 GLB K 1 0 1 2 0 1 0 GLB L 1 0 4 14 0 0 0 ------------------------------------------------------------------------------ GLB M 1 0 3 14 0 0 0 GLB N 1 0 8 14 0 0 0 GLB O 1 0 5 14 0 0 0 GLB P 1 0 1 14 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : Yes @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : Yes Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : No Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : FMAX Fmax_Logic_Level : 1 D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 80 Max Symbols : 24 @Utilization_options Max. % of Macrocells used : 100 @Usercode (HEX) @IO_Types Default = LVCMOS18 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_UP (2) @Fast_Bypass Default = None (2) @ORP_Bypass Default = None @Input_Registers Default = None (2) @Register_Powerup Default = None Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal| Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name ---------------------------------------------------------------------------------------- 1 | GND | - | | | | | 2 | TDI | - | | | | | 3 | I_O | 0 |C12 | * |LVCMOS33 | Output|SD2ANL 4 | I_O | 0 |C10 | | | | 5 | I_O | 0 |C6 | * |LVCMOS18 | Input |Reserved_Pin_283 6 | I_O | 0 |C2 | * |LVCMOS33 | Input |NI_STR 7 |GNDIO0 | - | | | | | 8 | I_O | 0 |D12 | * |LVCMOS33 | Input |NI_D_9_ 9 | I_O | 0 |D10 | * |LVCMOS33 | Input |NI_D_8_ 10 | I_O | 0 |D6 | * |LVCMOS33 | Input |NI_D_7_ 11 | I_O | 0 |D4 | * |LVCMOS33 | Input |NI_D_6_ 12 | IN0 | 0 | | | | | 13 |VCCIO0 | - | | | | | 14 | I_O | 0 |E4 | * |LVCMOS33 | Input |NI_D_5_ 15 | I_O | 0 |E6 | * |LVCMOS33 | Input |NI_D_4_ 16 | I_O | 0 |E10 | * |LVCMOS33 | Input |NI_D_3_ 17 | I_O | 0 |E12 | * |LVCMOS33 | Input |NI_D_2_ 18 |GNDIO0 | - | | | | | 19 | I_O | 0 |F2 | * |LVCMOS33 | Input |NI_D_1_ 20 | I_O | 0 |F6 | * |LVCMOS33 | Input |NI_D_0_ 21 | I_O | 0 |F10 | * |LVCMOS33 |Tri-Out|jTDO 22 | I_O | 0 |F12 | | | | 23 | IN1 | 0 | | | | | 24 | TCK | - | | | | | 25 | VCC | - | | | | | 26 | GND | - | | | | | 27 | IN2 | 0 | | | | | 28 | I_O | 0 |G12 | | | | 29 | I_O | 0 |G10 | | | | 30 | I_O | 0 |G6 | | | | 31 | I_O | 0 |G2 | | | | 32 |GNDIO0 | - | | | | | 33 |VCCIO0 | - | | | | | 34 | I_O | 0 |H12 | | | | 35 | I_O | 0 |H10 | | | | 36 | I_O | 0 |H6 | | | | 37 | I_O | 0 |H2 | | | | 38 |INCLK1 | 0 | | * |LVCMOS33 | Input |jTCK 39 |INCLK2 | 1 | | | | | 40 | VCC | - | | | | | 41 | I_O | 1 |I2 | | | | 42 | I_O | 1 |I6 | | | | 43 | I_O | 1 |I10 | | | | 44 | I_O | 1 |I12 | * |LVCMOS33 | Output|TESTEN 45 |VCCIO1 | - | | | | | 46 |GNDIO1 | - | | | | | 47 | I_O | 1 |J2 | * |LVCMOS33 | Output|PRBSEN 48 | I_O | 1 |J6 | * |LVCMOS33 | Output|LCKREFN 49 | I_O | 1 |J10 | * |LVCMOS33 | Output|ENABLE 50 | I_O | 1 |J12 | * |LVCMOS33 | Output|TX_ER 51 | GND | - | | | | | 52 | TMS | - | | | | | 53 | I_O | 1 |K12 | * |LVCMOS33 | Output|LOOPEN 54 | I_O | 1 |K10 | * |LVCMOS33 | Output|TX_EN 55 | I_O | 1 |K6 | * |LVCMOS33 | Output|TXD_15_ 56 | I_O | 1 |K2 | * |LVCMOS33 | Output|TXD_14_ 57 |GNDIO1 | - | | | | | 58 | I_O | 1 |L12 | * |LVCMOS33 | Output|TXD_13_ 59 | I_O | 1 |L10 | * |LVCMOS33 | Output|TXD_12_ 60 | I_O | 1 |L6 | * |LVCMOS33 | Output|TXD_11_ 61 | I_O | 1 |L4 | * |LVCMOS33 | Output|TXD_10_ 62 | IN3 | 1 | | | | | 63 |VCCIO1 | - | | | | | 64 | I_O | 1 |M4 | * |LVCMOS33 | Output|TXD_9_ 65 | I_O | 1 |M6 | * |LVCMOS33 | Output|TXD_8_ 66 | I_O | 1 |M10 | * |LVCMOS33 | Input |clk 67 | I_O | 1 |M12 | * |LVCMOS33 | Output|TXD_7_ 68 |GNDIO1 | - | | | | | 69 | I_O | 1 |N2 | * |LVCMOS33 | Output|TXD_6_ 70 | I_O | 1 |N6 | * |LVCMOS33 | Output|TXD_5_ 71 | I_O | 1 |N10 | * |LVCMOS33 | Output|TXD_4_ 72 | I_O | 1 |N12 | * |LVCMOS33 | Output|TXD_3_ 73 | IN4 | 1 | | | | | 74 | TDO | - | | | | | 75 | VCC | - | | | | | 76 | GND | - | | | | | 77 | IN5 | 1 | | | | | 78 | I_O | 1 |O12 | * |LVCMOS33 | Output|TXD_2_ 79 | I_O | 1 |O10 | * |LVCMOS33 | Output|TXD_1_ 80 | I_O | 1 |O6 | * |LVCMOS33 | Output|TXD_0_ 81 | I_O | 1 |O2 | * |LVCMOS33 | Input |FAULT 82 |GNDIO1 | - | | | | | 83 |VCCIO1 | - | | | | | 84 | I_O | 1 |P12 | * |LVCMOS33 | Output|EN 85 | I_O | 1 |P10 | | | | 86 | I_O | 1 |P6 | | | | 87 | I_O/OE| 1 |P2 | * |LVCMOS33 | Input |jTMS 88 |INCLK3 | 1 | | * |LVCMOS33 | Input |jTDI 89 |INCLK0 | 0 | | | | | 90 | VCC | - | | | | | 91 | I_O/OE| 0 |A2 | | | | 92 | I_O | 0 |A6 | | | | 93 | I_O | 0 |A10 | | | | 94 | I_O | 0 |A12 | | | | 95 |VCCIO0 | - | | | | | 96 |GNDIO0 | - | | | | | 97 | I_O | 0 |B2 | * |LVCMOS33 | Bidir |SDA 98 | I_O | 0 |B6 | * |LVCMOS33 |Tri-Out|SCL 99 | I_O | 0 |B10 | * |LVCMOS33 | Input |DIS_JTG 100 | I_O | 0 |B12 | * |LVCMOS33 | Input |reset_n ---------------------------------------------------------------------------------------- <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal ---------------------------------------------------------- 99 B I/O 2 -B---F---------- Up DIS_JTG 81 O I/O 2 ----E-G--------- Up FAULT 20 F I/O 2 A--------------P Up NI_D_0_ 19 F I/O 1 -------------N-- Up NI_D_1_ 17 E I/O 2 --------------OP Up NI_D_2_ 16 E I/O 3 -B----------M-O- Up NI_D_3_ 15 E I/O 2 ------------M-O- Up NI_D_4_ 14 E I/O 2 A--------J------ Up NI_D_5_ 11 D I/O 4 A----------LM--P Up NI_D_6_ 10 D I/O 3 -----------L-N-P Up NI_D_7_ 9 D I/O 2 -B-------------P Up NI_D_8_ 8 D I/O 2 -----------LM--- Up NI_D_9_ 6 C I/O 10 AB-D-----JKLMNOP Up NI_STR 5 C I/O ---------------- Up Reserved_Pin_283 66 M I/O 14 A-CDE-GHIJKLMNOP Up clk 38 -- INCLK 1 -----F---------- Up jTCK 88 -- INCLK 2 -----F-H-------- Up jTDI 87 P I/O 2 -B---F---------- Up jTMS 100 B I/O 5 --C--F-H-J-----P Up reset_n ---------------------------------------------------------- Output_Signal_List
I C P R P O Output N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal -------------------------------------------------------------------------------- 84 P 5 1 2 1 COM ---------------- Slow Up EN 49 J 5 1 2 1 COM ---------------- Slow Up ENABLE 48 J 0 - 0 1 COM ---------------- Slow Up LCKREFN 53 K 0 - 0 1 COM ---------------- Slow Up LOOPEN 47 J 4 - 1 1 COM ---------------- Slow Up PRBSEN 98 B 0 - 0 1 COM * ---------------- Slow Up SCL 3 C 5 1 2 1 COM ---------------- Slow Up SD2ANL 44 I 0 - 0 1 COM ---------------- Slow Up TESTEN 80 O 8 5 6 2 DFF R * 3 -------H-----NO- Fast Up TXD_0_ 61 L 15 4 15 4 DFF R * 1 -----------L---- Fast Up TXD_10_ 60 L 13 5 9 3 DFF R * 1 -----------L---- Fast Up TXD_11_ 59 L 12 5 7 2 DFF R * 2 ----------KL---- Fast Up TXD_12_ 58 L 14 4 12 3 DFF R * 2 ----------KL---- Fast Up TXD_13_ 56 K 16 5 10 3 DFF R * 1 ----------K----- Fast Up TXD_14_ 55 K 12 4 6 2 DFF R * 1 ----------K----- Fast Up TXD_15_ 79 O 11 5 8 2 DFF R * 2 -------------NO- Fast Up TXD_1_ 78 O 15 4 15 4 DFF R * 2 -------------NO- Fast Up TXD_2_ 72 N 13 5 9 3 DFF R * 1 -------------N-- Fast Up TXD_3_ 71 N 12 5 7 2 DFF R * 2 ------------MN-- Fast Up TXD_4_ 70 N 14 4 12 3 DFF R * 2 ------------MN-- Fast Up TXD_5_ 69 N 16 5 11 3 DFF R * 2 ------------MN-- Fast Up TXD_6_ 67 M 12 4 7 2 DFF R * 1 ------------M--- Fast Up TXD_7_ 65 M 11 4 11 3 DFF R * 3 ----------KLM--- Fast Up TXD_8_ 64 M 12 4 10 3 DFF R * 2 -----------LM--- Fast Up TXD_9_ 54 K 8 4 2 1 DFF R 4 ----E-GH--K----- Fast Up TX_EN 50 J 0 - 0 1 COM ---------------- Slow Up TX_ER 21 F 23 3 15 3 COM * ---------------- Slow Up jTDO -------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Bidir_Signal_List
I C P R P O Bidir N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------------------- 97 B 0 - 0 1 COM * 1 -----F---------- Slow Up SDA ------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Buried_Signal_List
I C P R P Node N L Mc R E U C I F Fanout Mc GLB P LL PTs S Type E S P E R P Signal ---------------------------------------------------------------------------------- 3 G 4 1 3 1 DFF * R * 3 -B--E-G--------- ID_0_0_ 0 G 5 1 4 1 DFF * R * 3 -B--E-G--------- ID_0_1_ 2 E 6 1 4 1 DFF * R * 2 -B--E----------- ID_0_2_ 0 E 7 1 5 1 DFF * R * 2 -B--E----------- ID_0_3_ 6 E 8 1 3 1 DFF * R * 2 -B--E----------- ID_0_4_ 12 E 8 1 2 2 TFF * R * 2 -B--E----------- ID_0_5_ 11 E 9 1 2 2 TFF * R * 2 -B--E----------- ID_0_6_ 9 E 10 1 2 1 TFF * R * 2 -B----G--------- ID_0_7_ 8 E 5 2 3 1 DFF * R * 1 ----E----------- ID_1_0_ 3 E 6 2 4 1 DFF * R * 1 ----E----------- ID_1_1_ 1 E 7 2 5 1 DFF * R * 1 ----E----------- ID_1_2_ 7 E 8 2 3 1 DFF * R * 1 ----E----------- ID_1_3_ 15 E 8 2 2 1 TFF * R * 1 ----E----------- ID_1_4_ 14 E 9 2 2 1 TFF * R * 1 ----E----------- ID_1_5_ 13 E 10 2 2 1 TFF * R * 1 ----E----------- ID_1_6_ 4 G 4 1 3 1 DFF * R * 2 ------G-I------- ID_2_0_ 1 G 5 1 4 1 DFF * R * 2 ------G-I------- ID_2_1_ 11 G 6 1 5 1 DFF * R * 3 ----E-G-I------- ID_2_2_ 4 I 7 1 5 1 DFF * R * 1 --------I------- ID_2_3_ 8 I 8 1 3 1 DFF * R * 1 --------I------- ID_2_4_ 12 I 8 1 2 1 TFF * R * 1 --------I------- ID_2_5_ 11 I 9 1 2 1 TFF * R * 2 ----E---I------- ID_2_6_ 0 I 8 - 2 1 COM 2 ------G-I------- ID_2_6__0 15 I 4 1 2 1 DFF * R * 1 --------I------- ID_3_0_ 10 I 5 1 3 1 DFF * R * 1 --------I------- ID_3_1_ 6 I 6 1 4 1 DFF * R * 2 ----E---I------- ID_3_2_ 5 I 7 1 5 1 DFF * R * 1 --------I------- ID_3_3_ 9 I 8 1 3 1 DFF * R * 1 --------I------- ID_3_4_ 14 I 8 1 2 1 TFF * R * 1 --------I------- ID_3_5_ 13 I 9 1 2 1 TFF * R * 2 ----E---I------- ID_3_6_ 1 I 8 - 2 1 COM 1 --------I------- ID_3_6__0 0 D 4 - 4 1 COM 4 --C--F---J-----P ix1231 1 D 4 - 4 1 COM 5 --C--F---J--M--P ix1254 2 D 4 - 4 1 COM 10 -BC--F---JKLMNOP ix1340 3 D 4 - 4 1 COM 7 --C--F---J-L-NOP ix1344 9 C 4 - 4 1 COM 9 -B---F---JKLMNOP ix1374 10 C 4 - 4 1 COM 9 -B---F---JKLMNOP ix1422 13 C 4 - 4 1 COM 6 -----F---JKL-N-P ix1442 14 C 4 - 4 1 COM 7 -----F---JKLMN-P ix1454 14 K 4 - 5 1 COM 1 ----------K----- ix1681 2 L 4 - 5 2 COM 1 ----------K----- ix1687 5 M 4 - 5 1 COM 1 -------H-------- ix1809 12 N 2 - 2 1 COM 1 -------H-------- ix1811 7 N 2 - 2 1 COM 1 -------H-------- ix1813 5 C 4 - 5 1 COM 2 --C--F---------- ix369 6 C 4 - 5 1 COM 2 --C--F---------- ix381 7 C 4 - 5 1 COM 2 --C--F---------- ix393 12 D 4 - 5 1 COM 2 ---D-F---------- ix47 13 D 4 - 5 1 COM 2 ---D-F---------- ix59 14 D 4 - 5 1 COM 2 ---D-F---------- ix71 10 G 2 1 1 1 DFF * R 4 ----EFG-I------- j2c_bitcnt_0_ 9 G 3 1 2 1 DFF * R 4 ----EFG-I------- j2c_bitcnt_1_ 5 G 4 1 3 1 DFF * R 3 ----EFG--------- j2c_bitcnt_2_ 6 G 5 1 2 1 DFF * R * 3 ----E-G-I------- j2c_reg_clear 12 F 4 - 2 1 COM 1 ------G--------- j2c_reg_clear_0 5 H 4 1 2 1 DFF * S * 5 ----EFGHI------- j2c_reg_cmdreg_0_ 11 H 4 1 2 2 DFF * S * 3 ----EFG--------- j2c_reg_cmdreg_1_ 10 H 4 1 2 2 DFF * S * 1 -----F---------- j2c_reg_cmdreg_2_ 15 H 4 1 1 1 DFF * R 2 -----F-H-------- j2c_reg_cmdreg_3_ 5 F 8 1 5 1 DFF * R * 1 --C------------- j2c_reg_creg0hm_0_ 14 F 8 1 5 1 DFF * R * 1 --C------------- j2c_reg_creg0hm_1_ 10 F 6 1 2 1 DFF * S * 1 --C------------- j2c_reg_creg0hm_2_ 15 F 8 1 5 1 DFF * S * 1 --C------------- j2c_reg_creg0hm_3_ 4 F 6 1 2 1 DFF * R * 1 --C------------- j2c_reg_creg0hm_4_ 9 F 6 1 2 1 DFF * R * 1 --C------------- j2c_reg_creg0hm_5_ 8 F 6 1 2 1 DFF * S * 1 --C------------- j2c_reg_creg0hm_6_ 3 H 8 1 5 2 DFF * S * 1 ---D------------ j2c_reg_creg1hm_0_ 2 H 8 1 5 2 DFF * R * 1 ---D------------ j2c_reg_creg1hm_1_ 4 H 6 1 2 2 DFF * R * 1 ---D------------ j2c_reg_creg1hm_2_ 12 H 8 1 5 1 DFF * R * 1 ---D------------ j2c_reg_creg1hm_3_ 9 H 6 1 2 2 DFF * R * 1 ---D------------ j2c_reg_creg1hm_4_ 8 H 6 1 2 1 DFF * S * 1 ---D------------ j2c_reg_creg1hm_5_ 7 H 6 1 2 2 DFF * S * 1 ---D------------ j2c_reg_creg1hm_6_ 7 G 5 1 2 1 DFF * S * 1 --C------------- j2c_reg_rstout_n_i 11 F 1 1 2 2 DFF R 1 -----F---------- j2c_reg_shreg_0_ 6 F 1 1 2 1 DFF R 1 -----F---------- j2c_reg_shreg_1_ 7 F 1 1 2 1 DFF R 1 -----F---------- j2c_reg_shreg_2_ 10 K 1 1 1 1 DFF R 1 -----F---------- j2c_reg_shreg_3_ 6 H 1 1 2 1 DFF R 2 -------H--K----- j2c_reg_shreg_4_ 3 C 1 1 1 1 DFF R 1 -------H-------- j2c_reg_shreg_5_ 8 K 1 1 1 1 DFF R 2 --C----H-------- j2c_reg_shreg_6_ 3 F 1 - 2 1 DFF R 2 -------H--K----- j2c_reg_shreg_7_ 4 C 3 1 1 1 DFF R 3 -B-D------K----- ni_nires_reg_clear_n_i 1 P 4 - 2 2 DFF R * 1 -------H-------- ni_nires_reg_data0neg_0_ 15 N 4 - 2 1 DFF R * 1 ------G--------- ni_nires_reg_data0neg_1_ 5 P 4 - 2 1 DFF R * 1 -------H-------- ni_nires_reg_data0neg_2_ 14 B 4 - 3 1 DFF R * 1 A--------------- ni_nires_reg_data0neg_3_ 13 M 4 - 2 2 DFF R * 1 ------G--------- ni_nires_reg_data0neg_4_ 12 J 4 - 2 1 DFF R * 1 A--------------- ni_nires_reg_data0neg_5_ 0 M 4 - 2 1 DFF R * 1 ---D------------ ni_nires_reg_data0neg_6_ 9 P 4 - 2 1 DFF R * 1 --------------O- ni_nires_reg_data0neg_7_ 11 P 4 - 2 2 DFF R * 1 A--------------- ni_nires_reg_data0neg_8_ 3 M 4 - 2 2 DFF R * 1 -------H-------- ni_nires_reg_data0neg_9_ 8 A 4 - 2 1 DFF R * 1 ------G--------- ni_nires_reg_data0pos_0_ 3 N 4 - 3 2 DFF R * 1 A--------------- ni_nires_reg_data0pos_1_ 9 O 4 - 2 2 DFF R * 1 ---D------------ ni_nires_reg_data0pos_2_ 14 O 4 - 2 1 DFF R * 1 A--------------- ni_nires_reg_data0pos_3_ 2 O 4 - 2 2 DFF R * 1 ---D------------ ni_nires_reg_data0pos_4_ 12 A 4 - 2 1 DFF R * 1 --------------O- ni_nires_reg_data0pos_5_ 3 L 4 - 2 2 DFF R * 1 --C------------- ni_nires_reg_data0pos_6_ 7 L 4 - 2 2 DFF R * 1 A--------------- ni_nires_reg_data0pos_7_ 6 B 4 - 2 1 DFF R * 1 ---D------------ ni_nires_reg_data0pos_8_ 14 L 4 - 2 1 DFF R * 1 --C------------- ni_nires_reg_data0pos_9_ 2 P 4 - 2 2 DFF R * 1 -------H-------- ni_nires_reg_data1neg_0_ 4 N 4 - 2 1 DFF R * 1 ------G--------- ni_nires_reg_data1neg_1_ 6 P 4 - 2 1 DFF R * 1 -------H-------- ni_nires_reg_data1neg_2_ 15 B 4 - 3 1 DFF R * 1 A--------------- ni_nires_reg_data1neg_3_ 14 M 4 - 2 1 DFF R * 1 ------G--------- ni_nires_reg_data1neg_4_ 13 J 4 - 2 1 DFF R * 1 A--------------- ni_nires_reg_data1neg_5_ 8 P 4 - 2 1 DFF R * 1 ---D------------ ni_nires_reg_data1neg_6_ 10 P 4 - 2 2 DFF R * 1 --------------O- ni_nires_reg_data1neg_7_ 12 P 4 - 2 2 DFF R * 1 A--------------- ni_nires_reg_data1neg_8_ 4 M 4 - 2 2 DFF R * 1 -------H-------- ni_nires_reg_data1neg_9_ 9 A 4 - 2 1 DFF R * 1 ------G--------- ni_nires_reg_data1pos_0_ 8 N 4 - 3 2 DFF R * 1 A--------------- ni_nires_reg_data1pos_1_ 11 O 4 - 2 1 DFF R * 1 ---D------------ ni_nires_reg_data1pos_2_ 15 O 4 - 2 1 DFF R * 1 A--------------- ni_nires_reg_data1pos_3_ 3 O 4 - 2 2 DFF R * 1 ---D------------ ni_nires_reg_data1pos_4_ 13 A 4 - 2 1 DFF R * 1 --------------O- ni_nires_reg_data1pos_5_ 15 A 4 - 2 2 DFF R * 1 --C------------- ni_nires_reg_data1pos_6_ 8 L 4 - 2 1 DFF R * 1 A--------------- ni_nires_reg_data1pos_7_ 7 B 4 - 2 1 DFF R * 1 ---D------------ ni_nires_reg_data1pos_8_ 15 L 4 - 2 1 DFF R * 1 --C------------- ni_nires_reg_data1pos_9_ 14 P 4 - 2 1 DFF R * 1 -------H-------- ni_nires_reg_data2neg_0_ 10 N 4 - 2 2 DFF R * 1 ------G--------- ni_nires_reg_data2neg_1_ 3 P 4 - 2 1 DFF R * 1 -------H-------- ni_nires_reg_data2neg_2_ 7 M 4 - 2 1 DFF R * 1 A--------------- ni_nires_reg_data2neg_3_ 10 M 4 - 2 2 DFF R * 1 ------G--------- ni_nires_reg_data2neg_4_ 5 J 4 - 2 1 DFF R * 1 A--------------- ni_nires_reg_data2neg_5_ 15 M 4 - 2 1 DFF R * 1 ---D------------ ni_nires_reg_data2neg_6_ 5 N 4 - 2 1 DFF R * 1 --------------O- ni_nires_reg_data2neg_7_ 0 B 4 - 3 1 DFF R * 1 A--------------- ni_nires_reg_data2neg_8_ 1 M 4 - 2 1 DFF R * 1 -------H-------- ni_nires_reg_data2neg_9_ 6 A 4 - 2 1 DFF R * 1 ------G--------- ni_nires_reg_data2pos_0_ 0 N 4 - 3 1 DFF R * 1 A--------------- ni_nires_reg_data2pos_1_ 7 O 4 - 2 1 DFF R * 1 ---D------------ ni_nires_reg_data2pos_2_ 3 B 4 - 2 1 DFF R * 1 A--------------- ni_nires_reg_data2pos_3_ 0 O 4 - 2 1 DFF R * 1 ---D------------ ni_nires_reg_data2pos_4_ 10 A 4 - 2 1 DFF R * 1 --------------O- ni_nires_reg_data2pos_5_ 14 A 4 - 2 1 DFF R * 1 --C------------- ni_nires_reg_data2pos_6_ 4 L 4 - 2 1 DFF R * 1 A--------------- ni_nires_reg_data2pos_7_ 4 B 4 - 2 1 DFF R * 1 ---D------------ ni_nires_reg_data2pos_8_ 11 L 4 - 2 1 DFF R * 1 --C------------- ni_nires_reg_data2pos_9_ 15 P 4 - 2 1 DFF R * 1 -------H-------- ni_nires_reg_data3neg_0_ 14 N 4 - 2 1 DFF R * 1 ------G--------- ni_nires_reg_data3neg_1_ 4 P 4 - 2 1 DFF R * 1 -------H-------- ni_nires_reg_data3neg_2_ 13 B 4 - 3 1 DFF R * 1 A--------------- ni_nires_reg_data3neg_3_ 11 M 4 - 2 1 DFF R * 1 ------G--------- ni_nires_reg_data3neg_4_ 11 J 4 - 2 1 DFF R * 1 A--------------- ni_nires_reg_data3neg_5_ 7 P 4 - 2 1 DFF R * 1 ---D------------ ni_nires_reg_data3neg_6_ 6 N 4 - 2 2 DFF R * 1 --------------O- ni_nires_reg_data3neg_7_ 1 B 4 - 3 1 DFF R * 1 A--------------- ni_nires_reg_data3neg_8_ 2 M 4 - 2 2 DFF R * 1 -------H-------- ni_nires_reg_data3neg_9_ 7 A 4 - 2 1 DFF R * 1 ------G--------- ni_nires_reg_data3pos_0_ 1 N 4 - 3 2 DFF R * 1 A--------------- ni_nires_reg_data3pos_1_ 8 O 4 - 2 1 DFF R * 1 ---D------------ ni_nires_reg_data3pos_2_ 13 O 4 - 2 2 DFF R * 1 A--------------- ni_nires_reg_data3pos_3_ 1 O 4 - 2 2 DFF R * 1 ---D------------ ni_nires_reg_data3pos_4_ 11 A 4 - 2 1 DFF R * 1 --------------O- ni_nires_reg_data3pos_5_ 0 L 4 - 2 1 DFF R * 1 --C------------- ni_nires_reg_data3pos_6_ 5 L 4 - 2 1 DFF R * 1 A--------------- ni_nires_reg_data3pos_7_ 5 B 4 - 2 1 DFF R * 1 ---D------------ ni_nires_reg_data3pos_8_ 13 L 4 - 2 1 DFF R * 1 --C------------- ni_nires_reg_data3pos_9_ 14 H 7 1 6 2 DFF R 1 --C------------- ni_nires_reg_data_out_0_ 12 G 7 1 5 1 DFF R 2 ------------M--P ni_nires_reg_data_out_10_ 5 A 7 1 5 1 DFF R 2 ------------M--P ni_nires_reg_data_out_11_ 9 D 7 1 5 1 DFF R 3 -----------LM--P ni_nires_reg_data_out_12_ 0 A 7 1 5 1 DFF R 3 -----------LM--P ni_nires_reg_data_out_13_ 10 D 7 1 5 1 DFF R 3 ---------J-L---P ni_nires_reg_data_out_14_ 4 O 7 1 5 1 DFF R 3 -B-------J-L---- ni_nires_reg_data_out_15_ 11 C 7 1 4 1 DFF R 3 -B--------KL---- ni_nires_reg_data_out_16_ 1 A 7 1 5 1 DFF R 3 -B--------KL---- ni_nires_reg_data_out_17_ 11 D 7 1 5 1 DFF R 3 -BC-------K----- ni_nires_reg_data_out_18_ 15 C 7 1 4 1 DFF R 1 --C------------- ni_nires_reg_data_out_19_ 14 G 7 1 5 1 DFF R 1 --C------------- ni_nires_reg_data_out_1_ 0 H 7 1 6 2 DFF R 3 --C------J----O- ni_nires_reg_data_out_2_ 2 A 7 1 5 1 DFF R 3 ---------J---NO- ni_nires_reg_data_out_3_ 15 G 7 1 5 1 DFF R 3 ---------J---NO- ni_nires_reg_data_out_4_ 3 A 7 1 5 1 DFF R 2 ---------J---N-- ni_nires_reg_data_out_5_ 15 D 7 1 5 1 DFF R 2 ---------J---N-- ni_nires_reg_data_out_6_ 5 O 7 1 5 1 DFF R 3 ---------J--MN-- ni_nires_reg_data_out_7_ 4 A 7 1 5 1 DFF R 3 ---------J--MN-- ni_nires_reg_data_out_8_ 1 H 7 1 6 2 DFF R 1 ---------J------ ni_nires_reg_data_out_9_ 9 B 3 1 2 2 DFF * R 5 AB---------L-NO- ni_nires_reg_gray_cnt_0_ 8 B 3 1 2 2 DFF * R 5 AB---------L-NO- ni_nires_reg_gray_cnt_1_ 1 K 3 1 3 1 DFF * R 6 -B-D-----J--MN-P ni_nires_reg_gray_cntf_0_ 4 D 3 1 2 1 DFF * R 7 -B-D-----JK-MN-P ni_nires_reg_gray_cntf_1_ 7 D 3 1 1 1 DFF * R 1 ------G--------- ni_nires_reg_new_cnt_0_ 8 D 3 1 1 1 DFF * R 1 ------G--------- ni_nires_reg_new_cnt_1_ 5 D 4 1 2 1 DFF * R * 6 A-CD--GH------O- ni_nires_reg_old_cnt_0_ 6 D 4 1 2 2 DFF * R * 6 A-CD--GH------O- ni_nires_reg_old_cnt_1_ 13 G 5 1 5 1 DFF R 1 ----------K----- ni_nires_reg_valid 9 K 2 1 1 1 DFF R 1 ----------K----- ni_pattcount_0_ 6 K 3 1 2 1 DFF R 1 ----------K----- ni_pattcount_1_ 4 K 4 1 3 1 DFF R 1 ----------K----- ni_pattcount_2_ 15 K 5 1 4 1 DFF R 1 ----------K----- ni_pattcount_3_ 5 K 6 1 2 1 DFF R 1 ----------K----- ni_pattcount_4_ 0 K 5 2 4 1 DFF R 1 --------I------- ni_reg_ce_prty_bit_neg 13 H 6 2 7 2 DFF R 1 --------I------- ni_reg_ce_prty_bit_pos 0 P 19 6 13 3 DFF R 1 ----------K----- ni_reg_prty_bit_neg_r 4 J 23 5 16 4 DFF R 1 ------------M--- ni_reg_prty_bit_pos_r 13 F 2 - 1 1 COM 3 -----FGH-------- nx0 10 E 21 - 16 4 COM 1 -----F---------- nx1093 3 I 9 - 6 2 COM 1 ----E----------- nx1117 2 C 4 - 1 1 COM 5 ----------KLMNO- nx1267 1 C 3 - 2 1 COM 2 ---------J----O- nx1303 0 J 3 - 1 1 COM 3 --C---------M--P nx1369 3 K 2 - 1 1 COM 6 ---------J-LMNOP nx1439 0 C 4 - 3 1 COM 2 ---------J----O- nx1459 1 J 2 - 1 1 COM 7 -B-------J-LMNOP nx1491 7 J 6 - 4 1 COM 2 ---------J--M--- nx1507 8 J 5 - 4 1 COM 2 ---------J---N-- nx1597 14 J 3 - 2 1 COM 4 -B-------J-L-N-- nx1625 15 J 4 - 2 1 COM 5 -B-------JKL-N-- nx1689 2 F 4 - 2 1 COM 5 ---------J-LM-OP nx1755 12 L 4 - 2 1 COM 2 -----------L-N-- nx1795 9 M 5 - 3 1 COM 2 ----------K--N-- nx1827 1 F 3 - 2 1 COM 1 --------I------- nx191 7 I 7 - 4 1 COM 1 ----E----------- nx2010 8 C 6 - 4 1 COM 2 ----------K----P nx2043 12 B 11 - 7 2 COM 1 ---------------P nx2090 9 J 5 - 4 1 COM 2 -B---------L---- nx2116 4 E 6 - 4 1 COM 1 ----E----------- nx2344 10 B 8 - 1 1 COM 1 ----E----------- nx2387 7 K 3 - 2 1 COM 5 ----------KLMNO- nx240 5 E 6 - 4 1 COM 1 ----E----------- nx2404 8 G 7 - 2 1 COM 1 ----E----------- nx2457 2 G 4 - 4 1 COM 1 ---D------------ nx973 -- F 2 1 0 PTOE ---------------- SCL.OE -- B 2 1 0 PTOE ---------------- SDA.OE -- I 1 1 0 PTOE ---------------- jTDO.OE ---------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used OBP = ORP bypass used PostFit_Equations
EN = !( !ix1231 & ix1254 & !ix1340 & !ix1344 # !reset_n ) ; (2 pterms, 5 signals) ENABLE = !( !ix1231 & ix1254 & !ix1340 & !ix1344 # !reset_n ) ; (2 pterms, 5 signals) ID_0_0_.D = !ID_0_0_.Q ; (1 pterm, 1 signal) ID_0_0_.C = clk ; (1 pterm, 1 signal) ID_0_0_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_0_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_0_1_.D = ID_0_1_.Q & !ID_0_0_.Q # !ID_0_1_.Q & ID_0_0_.Q ; (2 pterms, 2 signals) ID_0_1_.C = clk ; (1 pterm, 1 signal) ID_0_1_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_1_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_0_2_.D = !ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q # ID_0_2_.Q & !ID_0_1_.Q # ID_0_2_.Q & !ID_0_0_.Q ; (3 pterms, 3 signals) ID_0_2_.C = clk ; (1 pterm, 1 signal) ID_0_2_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_2_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_0_3_.D = !ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q # ID_0_3_.Q & !ID_0_1_.Q # ID_0_3_.Q & !ID_0_2_.Q # ID_0_3_.Q & !ID_0_0_.Q ; (4 pterms, 4 signals) ID_0_3_.C = clk ; (1 pterm, 1 signal) ID_0_3_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_3_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_0_4_.D.X1 = ID_0_4_.Q ; (1 pterm, 1 signal) ID_0_4_.D.X2 = ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q ; (1 pterm, 4 signals) ID_0_4_.C = clk ; (1 pterm, 1 signal) ID_0_4_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_4_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_0_5_.T = ID_0_4_.Q & ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q ; (1 pterm, 5 signals) ID_0_5_.C = clk ; (1 pterm, 1 signal) ID_0_5_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_5_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_0_6_.T = ID_0_5_.Q & ID_0_4_.Q & ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q ; (1 pterm, 6 signals) ID_0_6_.C = clk ; (1 pterm, 1 signal) ID_0_6_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_6_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_0_7_.T = ID_0_6_.Q & ID_0_5_.Q & ID_0_4_.Q & ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q ; (1 pterm, 7 signals) ID_0_7_.C = clk ; (1 pterm, 1 signal) ID_0_7_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_7_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_1_0_.D = !nx2387 & !ID_1_0_.Q # nx2387 & ID_1_0_.Q ; (2 pterms, 2 signals) ID_1_0_.C = clk ; (1 pterm, 1 signal) ID_1_0_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_0_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_1_1_.D = !nx2387 & !ID_1_1_.Q & ID_1_0_.Q # nx2387 & ID_1_1_.Q # ID_1_1_.Q & !ID_1_0_.Q ; (3 pterms, 3 signals) ID_1_1_.C = clk ; (1 pterm, 1 signal) ID_1_1_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_1_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_1_2_.D = !nx2387 & !ID_1_2_.Q & ID_1_1_.Q & ID_1_0_.Q # ID_1_2_.Q & !ID_1_1_.Q # nx2387 & ID_1_2_.Q # ID_1_2_.Q & !ID_1_0_.Q ; (4 pterms, 4 signals) ID_1_2_.C = clk ; (1 pterm, 1 signal) ID_1_2_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_2_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_1_3_.D.X1 = ID_1_3_.Q ; (1 pterm, 1 signal) ID_1_3_.D.X2 = !nx2387 & ID_1_2_.Q & ID_1_1_.Q & ID_1_0_.Q ; (1 pterm, 4 signals) ID_1_3_.C = clk ; (1 pterm, 1 signal) ID_1_3_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_3_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_1_4_.T = !nx2387 & ID_1_3_.Q & ID_1_2_.Q & ID_1_1_.Q & ID_1_0_.Q ; (1 pterm, 5 signals) ID_1_4_.C = clk ; (1 pterm, 1 signal) ID_1_4_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_4_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_1_5_.T = !nx2387 & ID_1_4_.Q & ID_1_3_.Q & ID_1_2_.Q & ID_1_1_.Q & ID_1_0_.Q ; (1 pterm, 6 signals) ID_1_5_.C = clk ; (1 pterm, 1 signal) ID_1_5_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_5_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_1_6_.T = !nx2387 & ID_1_5_.Q & ID_1_4_.Q & ID_1_3_.Q & ID_1_2_.Q & ID_1_1_.Q & ID_1_0_.Q ; (1 pterm, 7 signals) ID_1_6_.C = clk ; (1 pterm, 1 signal) ID_1_6_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_6_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_2_0_.D = !ID_2_0_.Q ; (1 pterm, 1 signal) ID_2_0_.C = clk ; (1 pterm, 1 signal) ID_2_0_.CE = !( ID_2_6__0 ) ; (1 pterm, 1 signal) ID_2_0_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_2_1_.D = ID_2_1_.Q & !ID_2_0_.Q # !ID_2_1_.Q & ID_2_0_.Q ; (2 pterms, 2 signals) ID_2_1_.C = clk ; (1 pterm, 1 signal) ID_2_1_.CE = !( ID_2_6__0 ) ; (1 pterm, 1 signal) ID_2_1_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_2_2_.D = !ID_2_2_.Q & ID_2_1_.Q & ID_2_0_.Q # ID_2_2_.Q & !ID_2_1_.Q # ID_2_2_.Q & !ID_2_0_.Q ; (3 pterms, 3 signals) ID_2_2_.C = clk ; (1 pterm, 1 signal) ID_2_2_.CE = !( ID_2_6__0 ) ; (1 pterm, 1 signal) ID_2_2_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_2_3_.D = !ID_2_3_.Q & ID_2_2_.Q & ID_2_1_.Q & ID_2_0_.Q # ID_2_3_.Q & !ID_2_1_.Q # ID_2_3_.Q & !ID_2_2_.Q # ID_2_3_.Q & !ID_2_0_.Q ; (4 pterms, 4 signals) ID_2_3_.C = clk ; (1 pterm, 1 signal) ID_2_3_.CE = !( ID_2_6__0 ) ; (1 pterm, 1 signal) ID_2_3_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_2_4_.D.X1 = ID_2_4_.Q ; (1 pterm, 1 signal) ID_2_4_.D.X2 = ID_2_3_.Q & ID_2_2_.Q & ID_2_1_.Q & ID_2_0_.Q ; (1 pterm, 4 signals) ID_2_4_.C = clk ; (1 pterm, 1 signal) ID_2_4_.CE = !( ID_2_6__0 ) ; (1 pterm, 1 signal) ID_2_4_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_2_5_.T = ID_2_4_.Q & ID_2_3_.Q & ID_2_2_.Q & ID_2_1_.Q & ID_2_0_.Q ; (1 pterm, 5 signals) ID_2_5_.C = clk ; (1 pterm, 1 signal) ID_2_5_.CE = !( ID_2_6__0 ) ; (1 pterm, 1 signal) ID_2_5_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_2_6_.T = ID_2_5_.Q & ID_2_4_.Q & ID_2_3_.Q & ID_2_2_.Q & ID_2_1_.Q & ID_2_0_.Q ; (1 pterm, 6 signals) ID_2_6_.C = clk ; (1 pterm, 1 signal) ID_2_6_.CE = !( ID_2_6__0 ) ; (1 pterm, 1 signal) ID_2_6_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_2_6__0 = !ni_reg_ce_prty_bit_neg.Q # ID_2_6_.Q & ID_2_5_.Q & ID_2_4_.Q & ID_2_3_.Q & ID_2_2_.Q & ID_2_1_.Q & ID_2_0_.Q ; (2 pterms, 8 signals) ID_3_0_.D = !ID_3_0_.Q ; (1 pterm, 1 signal) ID_3_0_.C = clk ; (1 pterm, 1 signal) ID_3_0_.CE = !( ID_3_6__0 ) ; (1 pterm, 1 signal) ID_3_0_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_3_1_.D = ID_3_1_.Q & !ID_3_0_.Q # !ID_3_1_.Q & ID_3_0_.Q ; (2 pterms, 2 signals) ID_3_1_.C = clk ; (1 pterm, 1 signal) ID_3_1_.CE = !( ID_3_6__0 ) ; (1 pterm, 1 signal) ID_3_1_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_3_2_.D = !ID_3_2_.Q & ID_3_1_.Q & ID_3_0_.Q # ID_3_2_.Q & !ID_3_1_.Q # ID_3_2_.Q & !ID_3_0_.Q ; (3 pterms, 3 signals) ID_3_2_.C = clk ; (1 pterm, 1 signal) ID_3_2_.CE = !( ID_3_6__0 ) ; (1 pterm, 1 signal) ID_3_2_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_3_3_.D = !ID_3_3_.Q & ID_3_2_.Q & ID_3_1_.Q & ID_3_0_.Q # ID_3_3_.Q & !ID_3_1_.Q # ID_3_3_.Q & !ID_3_2_.Q # ID_3_3_.Q & !ID_3_0_.Q ; (4 pterms, 4 signals) ID_3_3_.C = clk ; (1 pterm, 1 signal) ID_3_3_.CE = !( ID_3_6__0 ) ; (1 pterm, 1 signal) ID_3_3_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_3_4_.D.X1 = ID_3_4_.Q ; (1 pterm, 1 signal) ID_3_4_.D.X2 = ID_3_3_.Q & ID_3_2_.Q & ID_3_1_.Q & ID_3_0_.Q ; (1 pterm, 4 signals) ID_3_4_.C = clk ; (1 pterm, 1 signal) ID_3_4_.CE = !( ID_3_6__0 ) ; (1 pterm, 1 signal) ID_3_4_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_3_5_.T = ID_3_4_.Q & ID_3_3_.Q & ID_3_2_.Q & ID_3_1_.Q & ID_3_0_.Q ; (1 pterm, 5 signals) ID_3_5_.C = clk ; (1 pterm, 1 signal) ID_3_5_.CE = !( ID_3_6__0 ) ; (1 pterm, 1 signal) ID_3_5_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_3_6_.T = ID_3_5_.Q & ID_3_4_.Q & ID_3_3_.Q & ID_3_2_.Q & ID_3_1_.Q & ID_3_0_.Q ; (1 pterm, 6 signals) ID_3_6_.C = clk ; (1 pterm, 1 signal) ID_3_6_.CE = !( ID_3_6__0 ) ; (1 pterm, 1 signal) ID_3_6_.AR = j2c_reg_clear.Q ; (1 pterm, 1 signal) ID_3_6__0 = !ni_reg_ce_prty_bit_pos.Q # ID_3_6_.Q & ID_3_5_.Q & ID_3_4_.Q & ID_3_3_.Q & ID_3_2_.Q & ID_3_1_.Q & ID_3_0_.Q ; (2 pterms, 8 signals) LCKREFN = 0 ; (0 pterm, 0 signal) LOOPEN = 0 ; (0 pterm, 0 signal) PRBSEN = !ix1231 & ix1254 & !ix1340 & ix1344 ; (1 pterm, 4 signals) SCL = 0 ; (0 pterm, 0 signal) SCL.OE = DIS_JTG & !jTCK ; (1 pterm, 2 signals) SD2ANL = !( !ix1231 & ix1254 & !ix1340 & !ix1344 # !reset_n ) ; (2 pterms, 5 signals) SDA = 0 ; (0 pterm, 0 signal) SDA.OE = DIS_JTG & !jTMS ; (1 pterm, 2 signals) TESTEN = 0 ; (0 pterm, 0 signal) TXD_0_.D = !nx1267 & !nx1303 & nx1439 & nx1491 # !nx1267 & !nx1439 & !nx1459 # !TXD_0_.Q & nx1267 # !nx1267 & !nx1459 & !nx1491 ; (4 pterms, 6 signals) TXD_0_.C = clk ; (1 pterm, 1 signal) TXD_0_.CE = nx240 ; (1 pterm, 1 signal) TXD_10_.D = !nx1267 & ix1340 & ni_nires_reg_data_out_14_.Q & ix1344 & ix1422 & nx1439 # !nx1267 & ix1340 & ni_nires_reg_data_out_14_.Q & ix1344 & ix1374 & nx1439 # ni_nires_reg_data_out_12_.Q & !nx1267 & !ix1374 & !ix1422 & !nx1755 # !TXD_10_.Q & !TXD_9_.Q & !TXD_8_.Q & nx1267 # ni_nires_reg_data_out_12_.Q & !nx1267 & !nx1439 & !nx1755 # !nx1267 & ni_nires_reg_data_out_13_.Q & !ix1344 & ix1422 & nx1439 # !nx1267 & ni_nires_reg_data_out_13_.Q & !ix1340 & ix1422 & nx1439 # !nx1267 & ni_nires_reg_data_out_13_.Q & !ix1344 & ix1374 & nx1439 # !nx1267 & ni_nires_reg_data_out_13_.Q & !ix1340 & ix1374 & nx1439 # TXD_10_.Q & TXD_8_.Q & nx1267 # TXD_10_.Q & TXD_9_.Q & nx1267 # !nx1267 & ni_nires_reg_data_out_13_.Q & !ix1374 & !ix1422 & nx1755 # !nx1267 & ni_nires_reg_data_out_13_.Q & !nx1439 & nx1755 ; (13 pterms, 13 signals) TXD_10_.C = clk ; (1 pterm, 1 signal) TXD_10_.CE = nx240 ; (1 pterm, 1 signal) TXD_11_.D.X1 = TXD_11_.Q & nx1267 # !nx1267 & nx1439 & !nx2116 # !nx1267 & ni_nires_reg_data_out_13_.Q & !ix1344 & !nx1439 # !nx1267 & ni_nires_reg_data_out_13_.Q & ni_nires_reg_data_out_14_.Q & !nx1439 # !nx1267 & ni_nires_reg_data_out_13_.Q & !ix1340 & !nx1439 # !nx1267 & !ni_nires_reg_data_out_13_.Q & ix1340 & ni_nires_reg_data_out_14_.Q & ix1344 & !nx1439 ; (6 pterms, 8 signals) TXD_11_.D.X2 = !TXD_10_.Q & !TXD_9_.Q & !TXD_8_.Q & nx1267 ; (1 pterm, 4 signals) TXD_11_.C = clk ; (1 pterm, 1 signal) TXD_11_.CE = nx240 ; (1 pterm, 1 signal) TXD_12_.D = !nx1267 & !ix1442 & !nx1491 & !nx2116 # ni_nires_reg_data_out_15_.Q & !nx1625 & !nx1795 # ni_nires_reg_data_out_16_.Q & nx1625 & !nx1795 # !TXD_12_.Q & nx1267 # !nx1267 & !ix1454 & !nx2116 ; (5 pterms, 10 signals) TXD_12_.C = clk ; (1 pterm, 1 signal) TXD_12_.CE = nx240 ; (1 pterm, 1 signal) TXD_13_.D = !nx1267 & ni_nires_reg_data_out_15_.Q & !ix1422 & !ix1442 & !nx1625 # !nx1267 & !ix1422 & ni_nires_reg_data_out_16_.Q & !ix1442 & nx1625 # !nx1267 & ix1422 & ix1454 & ni_nires_reg_data_out_17_.Q & nx1689 # !nx1267 & ix1422 & ni_nires_reg_data_out_16_.Q & ix1454 & !nx1689 # !nx1267 & ni_nires_reg_data_out_15_.Q & !ix1454 & !nx1625 # TXD_13_.Q & !TXD_12_.Q & nx1267 # !TXD_13_.Q & TXD_12_.Q & nx1267 # !nx1267 & ni_nires_reg_data_out_16_.Q & !ix1454 & nx1625 # !nx1267 & nx1439 & ni_nires_reg_data_out_17_.Q & nx1689 # !nx1267 & ni_nires_reg_data_out_16_.Q & nx1439 & !nx1689 ; (10 pterms, 12 signals) TXD_13_.C = clk ; (1 pterm, 1 signal) TXD_13_.CE = nx240 ; (1 pterm, 1 signal) TXD_14_.D = !nx1267 & !ix1374 & !ix1422 & ni_nires_reg_data_out_16_.Q & !ix1442 & !nx1689 # !nx1267 & !ix1374 & !ix1422 & !ix1442 & ni_nires_reg_data_out_17_.Q & nx1689 # !TXD_14_.Q & TXD_13_.Q & TXD_12_.Q & nx1267 # !nx1267 & ni_nires_reg_data_out_16_.Q & !ix1454 & !nx1689 # !nx1267 & !ix1454 & ni_nires_reg_data_out_17_.Q & nx1689 # TXD_14_.Q & !TXD_12_.Q & nx1267 # TXD_14_.Q & !TXD_13_.Q & nx1267 # ix1340 & ni_nires_reg_data_out_18_.Q & !nx1827 # !ix1340 & ni_nires_reg_data_out_17_.Q & !nx1827 ; (9 pterms, 14 signals) TXD_14_.C = clk ; (1 pterm, 1 signal) TXD_14_.CE = nx240 ; (1 pterm, 1 signal) TXD_15_.D.X1 = !nx1267 & !ix1340 & !ix1454 & ni_nires_reg_data_out_17_.Q # !nx1267 & ix1340 & !ix1454 & ni_nires_reg_data_out_18_.Q # !nx1267 & ix1454 & !nx2043 # TXD_14_.Q & TXD_13_.Q & TXD_12_.Q & nx1267 ; (4 pterms, 9 signals) TXD_15_.D.X2 = TXD_15_.Q & nx1267 ; (1 pterm, 2 signals) TXD_15_.C = clk ; (1 pterm, 1 signal) TXD_15_.CE = nx240 ; (1 pterm, 1 signal) TXD_1_.D = !nx1267 & ix1422 & nx1439 & !nx1755 & ni_nires_reg_data_out_2_.Q # !nx1267 & ix1422 & nx1439 & nx1755 & ni_nires_reg_data_out_3_.Q # TXD_1_.Q & !TXD_0_.Q & nx1267 # !TXD_1_.Q & TXD_0_.Q & nx1267 # !nx1267 & !nx1303 & !nx1439 # !nx1267 & !nx1303 & !ix1422 ; (6 pterms, 9 signals) TXD_1_.C = clk ; (1 pterm, 1 signal) TXD_1_.CE = nx240 ; (1 pterm, 1 signal) TXD_2_.D = !nx1267 & ix1340 & ix1344 & ix1422 & nx1439 & ni_nires_reg_data_out_4_.Q # !nx1267 & ix1340 & ix1344 & ix1374 & nx1439 & ni_nires_reg_data_out_4_.Q # !nx1267 & !ix1374 & !ix1422 & !nx1755 & ni_nires_reg_data_out_2_.Q # !TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & nx1267 # !nx1267 & !nx1439 & !nx1755 & ni_nires_reg_data_out_2_.Q # !nx1267 & !ix1344 & ix1422 & nx1439 & ni_nires_reg_data_out_3_.Q # !nx1267 & !ix1340 & ix1422 & nx1439 & ni_nires_reg_data_out_3_.Q # !nx1267 & !ix1344 & ix1374 & nx1439 & ni_nires_reg_data_out_3_.Q # !nx1267 & !ix1340 & ix1374 & nx1439 & ni_nires_reg_data_out_3_.Q # !nx1267 & !ix1374 & !ix1422 & nx1755 & ni_nires_reg_data_out_3_.Q # TXD_2_.Q & !TXD_0_.Q & nx1267 # TXD_2_.Q & !TXD_1_.Q & nx1267 # !nx1267 & !nx1439 & nx1755 & ni_nires_reg_data_out_3_.Q ; (13 pterms, 13 signals) TXD_2_.C = clk ; (1 pterm, 1 signal) TXD_2_.CE = nx240 ; (1 pterm, 1 signal) TXD_3_.D.X1 = TXD_3_.Q & nx1267 # !nx1267 & nx1439 & !nx1597 # !nx1267 & !nx1439 & ni_nires_reg_data_out_3_.Q & ni_nires_reg_data_out_4_.Q # !nx1267 & !ix1344 & !nx1439 & ni_nires_reg_data_out_3_.Q # !nx1267 & !ix1340 & !nx1439 & ni_nires_reg_data_out_3_.Q # !nx1267 & ix1340 & ix1344 & !nx1439 & !ni_nires_reg_data_out_3_.Q & ni_nires_reg_data_out_4_.Q ; (6 pterms, 8 signals) TXD_3_.D.X2 = TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & nx1267 ; (1 pterm, 4 signals) TXD_3_.C = clk ; (1 pterm, 1 signal) TXD_3_.CE = nx240 ; (1 pterm, 1 signal) TXD_4_.D = !nx1267 & !ix1442 & !nx1491 & !nx1597 # !nx1625 & !nx1795 & ni_nires_reg_data_out_5_.Q # !nx1267 & !ix1454 & !nx1597 # !TXD_4_.Q & nx1267 # nx1625 & !nx1795 & ni_nires_reg_data_out_6_.Q ; (5 pterms, 10 signals) TXD_4_.C = clk ; (1 pterm, 1 signal) TXD_4_.CE = nx240 ; (1 pterm, 1 signal) TXD_5_.D = !nx1267 & !ix1422 & !ix1442 & !nx1625 & ni_nires_reg_data_out_5_.Q # !nx1267 & ix1422 & ix1454 & !nx1689 & ni_nires_reg_data_out_6_.Q # !nx1267 & !ix1422 & !ix1442 & nx1625 & ni_nires_reg_data_out_6_.Q # !nx1267 & ix1422 & ix1454 & nx1689 & ni_nires_reg_data_out_7_.Q # !nx1267 & !ix1454 & !nx1625 & ni_nires_reg_data_out_5_.Q # !TXD_5_.Q & !TXD_4_.Q & nx1267 # TXD_5_.Q & TXD_4_.Q & nx1267 # !nx1267 & nx1439 & !nx1689 & ni_nires_reg_data_out_6_.Q # !nx1267 & !ix1454 & nx1625 & ni_nires_reg_data_out_6_.Q # !nx1267 & nx1439 & nx1689 & ni_nires_reg_data_out_7_.Q ; (10 pterms, 12 signals) TXD_5_.C = clk ; (1 pterm, 1 signal) TXD_5_.CE = nx240 ; (1 pterm, 1 signal) TXD_6_.D = !nx1267 & !ix1374 & !ix1422 & !ix1442 & !nx1689 & ni_nires_reg_data_out_6_.Q # !nx1267 & !ix1374 & !ix1422 & !ix1442 & nx1689 & ni_nires_reg_data_out_7_.Q # !TXD_6_.Q & !TXD_5_.Q & !TXD_4_.Q & nx1267 # !nx1267 & !ix1454 & !nx1689 & ni_nires_reg_data_out_6_.Q # !nx1267 & !ix1454 & nx1689 & ni_nires_reg_data_out_7_.Q # !ix1340 & !nx1827 & ni_nires_reg_data_out_7_.Q # TXD_6_.Q & TXD_4_.Q & nx1267 # TXD_6_.Q & TXD_5_.Q & nx1267 # ix1340 & !nx1827 & ni_nires_reg_data_out_8_.Q ; (9 pterms, 14 signals) TXD_6_.C = clk ; (1 pterm, 1 signal) TXD_6_.CE = nx240 ; (1 pterm, 1 signal) TXD_7_.D.X1 = !nx1267 & !ix1340 & !ix1454 & ni_nires_reg_data_out_7_.Q # !nx1267 & ix1340 & !ix1454 & ni_nires_reg_data_out_8_.Q # !nx1267 & ix1454 & !nx1507 # !TXD_6_.Q & !TXD_5_.Q & !TXD_4_.Q & nx1267 ; (4 pterms, 9 signals) TXD_7_.D.X2 = TXD_7_.Q & nx1267 ; (1 pterm, 2 signals) TXD_7_.C = clk ; (1 pterm, 1 signal) TXD_7_.CE = nx240 ; (1 pterm, 1 signal) TXD_8_.D = ni_nires_reg_data_out_12_.Q & !nx1267 & nx1369 & nx1439 & nx1491 # ix1254 & !nx1267 & nx1369 & !nx1491 & ni_nires_reg_data_out_11_.Q # !nx1267 & !nx1369 & nx1439 & nx1491 & ni_nires_reg_data_out_11_.Q # ix1254 & !nx1267 & nx1369 & !nx1439 & ni_nires_reg_data_out_11_.Q # ni_nires_reg_data_out_10_.Q & !ix1254 & !nx1267 & !nx1491 # ni_nires_reg_data_out_10_.Q & !ix1254 & !nx1267 & !nx1439 # ni_nires_reg_data_out_10_.Q & !nx1267 & !nx1369 & !nx1491 # ni_nires_reg_data_out_10_.Q & !nx1267 & !nx1369 & !nx1439 # !TXD_8_.Q & nx1267 ; (9 pterms, 9 signals) TXD_8_.C = clk ; (1 pterm, 1 signal) TXD_8_.CE = nx240 ; (1 pterm, 1 signal) TXD_9_.D = !nx1267 & ni_nires_reg_data_out_13_.Q & ix1422 & nx1439 & nx1755 # ni_nires_reg_data_out_12_.Q & !nx1267 & ix1422 & nx1439 & !nx1755 # !TXD_9_.Q & !TXD_8_.Q & nx1267 # TXD_9_.Q & TXD_8_.Q & nx1267 # ni_nires_reg_data_out_12_.Q & !nx1267 & nx1369 & !nx1439 # ni_nires_reg_data_out_12_.Q & !nx1267 & nx1369 & !ix1422 # !nx1267 & !nx1369 & !nx1439 & ni_nires_reg_data_out_11_.Q # !nx1267 & !nx1369 & !ix1422 & ni_nires_reg_data_out_11_.Q ; (8 pterms, 10 signals) TXD_9_.C = clk ; (1 pterm, 1 signal) TXD_9_.CE = nx240 ; (1 pterm, 1 signal) TX_EN.D = !( nx1267 & !ni_pattcount_2_.Q & !ni_pattcount_1_.Q & !ni_pattcount_0_.Q & !ni_pattcount_4_.Q & !ni_pattcount_3_.Q # !nx1267 & !ni_nires_reg_valid.Q ) ; (2 pterms, 7 signals) TX_EN.C = clk ; (1 pterm, 1 signal) TX_ER = 0 ; (0 pterm, 0 signal) ix1231 = j2c_reg_creg1hm_4_.Q & ix47 & !ix59 & ix71 # !j2c_reg_creg1hm_4_.Q & ix59 # !j2c_reg_creg1hm_4_.Q & !ix47 # !j2c_reg_creg1hm_4_.Q & !ix71 ; (4 pterms, 4 signals) ix1254 = j2c_reg_creg1hm_2_.Q & !ix47 & ix59 & ix71 # !j2c_reg_creg1hm_2_.Q & !ix59 # !j2c_reg_creg1hm_2_.Q & ix47 # !j2c_reg_creg1hm_2_.Q & !ix71 ; (4 pterms, 4 signals) ix1340 = j2c_reg_creg1hm_6_.Q & ix47 & ix59 & ix71 # !j2c_reg_creg1hm_6_.Q & !ix59 # !j2c_reg_creg1hm_6_.Q & !ix47 # !j2c_reg_creg1hm_6_.Q & !ix71 ; (4 pterms, 4 signals) ix1344 = j2c_reg_creg1hm_5_.Q & ix47 & ix59 & !ix71 # !j2c_reg_creg1hm_5_.Q & !ix59 # !j2c_reg_creg1hm_5_.Q & !ix47 # !j2c_reg_creg1hm_5_.Q & ix71 ; (4 pterms, 4 signals) ix1374 = j2c_reg_creg0hm_2_.Q & ix369 & !ix381 & ix393 # !j2c_reg_creg0hm_2_.Q & ix381 # !j2c_reg_creg0hm_2_.Q & !ix369 # !j2c_reg_creg0hm_2_.Q & !ix393 ; (4 pterms, 4 signals) ix1422 = j2c_reg_creg0hm_4_.Q & !ix369 & ix381 & ix393 # !j2c_reg_creg0hm_4_.Q & !ix381 # !j2c_reg_creg0hm_4_.Q & ix369 # !j2c_reg_creg0hm_4_.Q & !ix393 ; (4 pterms, 4 signals) ix1442 = j2c_reg_creg0hm_5_.Q & ix369 & ix381 & !ix393 # !j2c_reg_creg0hm_5_.Q & !ix381 # !j2c_reg_creg0hm_5_.Q & !ix369 # !j2c_reg_creg0hm_5_.Q & ix393 ; (4 pterms, 4 signals) ix1454 = j2c_reg_creg0hm_6_.Q & ix369 & ix381 & ix393 # !j2c_reg_creg0hm_6_.Q & !ix381 # !j2c_reg_creg0hm_6_.Q & !ix369 # !j2c_reg_creg0hm_6_.Q & !ix393 ; (4 pterms, 4 signals) ix1681.X1 = !TXD_14_.Q & !TXD_13_.Q & !ni_reg_prty_bit_neg_r.Q # !TXD_14_.Q & TXD_13_.Q & ni_reg_prty_bit_neg_r.Q # TXD_14_.Q & !TXD_13_.Q & ni_reg_prty_bit_neg_r.Q # TXD_14_.Q & TXD_13_.Q & !ni_reg_prty_bit_neg_r.Q ; (4 pterms, 3 signals) ix1681.X2 = !TXD_15_.Q ; (1 pterm, 1 signal) ix1687.X1 = !TXD_11_.Q & !TXD_10_.Q & !TXD_9_.Q # !TXD_11_.Q & TXD_10_.Q & TXD_9_.Q # TXD_11_.Q & !TXD_10_.Q & TXD_9_.Q # TXD_11_.Q & TXD_10_.Q & !TXD_9_.Q ; (4 pterms, 3 signals) ix1687.X2 = !TXD_12_.Q ; (1 pterm, 1 signal) ix1809.X1 = !TXD_6_.Q & !TXD_5_.Q & !ni_reg_prty_bit_pos_r.Q # !TXD_6_.Q & TXD_5_.Q & ni_reg_prty_bit_pos_r.Q # TXD_6_.Q & !TXD_5_.Q & ni_reg_prty_bit_pos_r.Q # TXD_6_.Q & TXD_5_.Q & !ni_reg_prty_bit_pos_r.Q ; (4 pterms, 3 signals) ix1809.X2 = !TXD_7_.Q ; (1 pterm, 1 signal) ix1811 = TXD_4_.Q & !TXD_3_.Q # !TXD_4_.Q & TXD_3_.Q ; (2 pterms, 2 signals) ix1813 = TXD_2_.Q & !TXD_1_.Q # !TXD_2_.Q & TXD_1_.Q ; (2 pterms, 2 signals) ix369.X1 = !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_1_.Q # !j2c_reg_creg0hm_5_.Q & j2c_reg_creg0hm_2_.Q & j2c_reg_creg0hm_1_.Q # j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_2_.Q & j2c_reg_creg0hm_1_.Q # j2c_reg_creg0hm_5_.Q & j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_1_.Q ; (4 pterms, 3 signals) ix369.X2 = !j2c_reg_creg0hm_6_.Q ; (1 pterm, 1 signal) ix381.X1 = !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_3_.Q # !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_5_.Q & j2c_reg_creg0hm_3_.Q # j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_5_.Q & j2c_reg_creg0hm_3_.Q # j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_3_.Q ; (4 pterms, 3 signals) ix381.X2 = !j2c_reg_creg0hm_4_.Q ; (1 pterm, 1 signal) ix393.X1 = !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_0_.Q # !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_2_.Q & j2c_reg_creg0hm_0_.Q # j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_2_.Q & j2c_reg_creg0hm_0_.Q # j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_0_.Q ; (4 pterms, 3 signals) ix393.X2 = !j2c_reg_creg0hm_4_.Q ; (1 pterm, 1 signal) ix47.X1 = !j2c_reg_creg1hm_5_.Q & !j2c_reg_creg1hm_4_.Q & !j2c_reg_creg1hm_3_.Q # !j2c_reg_creg1hm_5_.Q & j2c_reg_creg1hm_4_.Q & j2c_reg_creg1hm_3_.Q # j2c_reg_creg1hm_5_.Q & !j2c_reg_creg1hm_4_.Q & j2c_reg_creg1hm_3_.Q # j2c_reg_creg1hm_5_.Q & j2c_reg_creg1hm_4_.Q & !j2c_reg_creg1hm_3_.Q ; (4 pterms, 3 signals) ix47.X2 = !j2c_reg_creg1hm_6_.Q ; (1 pterm, 1 signal) ix59.X1 = !j2c_reg_creg1hm_6_.Q & !j2c_reg_creg1hm_5_.Q & !j2c_reg_creg1hm_1_.Q # !j2c_reg_creg1hm_6_.Q & j2c_reg_creg1hm_5_.Q & j2c_reg_creg1hm_1_.Q # j2c_reg_creg1hm_6_.Q & !j2c_reg_creg1hm_5_.Q & j2c_reg_creg1hm_1_.Q # j2c_reg_creg1hm_6_.Q & j2c_reg_creg1hm_5_.Q & !j2c_reg_creg1hm_1_.Q ; (4 pterms, 3 signals) ix59.X2 = !j2c_reg_creg1hm_2_.Q ; (1 pterm, 1 signal) ix71.X1 = !j2c_reg_creg1hm_6_.Q & !j2c_reg_creg1hm_4_.Q & !j2c_reg_creg1hm_0_.Q # !j2c_reg_creg1hm_6_.Q & j2c_reg_creg1hm_4_.Q & j2c_reg_creg1hm_0_.Q # j2c_reg_creg1hm_6_.Q & !j2c_reg_creg1hm_4_.Q & j2c_reg_creg1hm_0_.Q # j2c_reg_creg1hm_6_.Q & j2c_reg_creg1hm_4_.Q & !j2c_reg_creg1hm_0_.Q ; (4 pterms, 3 signals) ix71.X2 = !j2c_reg_creg1hm_2_.Q ; (1 pterm, 1 signal) j2c_bitcnt_0_.D = !j2c_bitcnt_0_.Q ; (1 pterm, 1 signal) j2c_bitcnt_0_.C = !jTCK ; (1 pterm, 1 signal) j2c_bitcnt_0_.AR = !nx0 ; (1 pterm, 1 signal) j2c_bitcnt_1_.D = j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q ; (2 pterms, 2 signals) j2c_bitcnt_1_.C = !jTCK ; (1 pterm, 1 signal) j2c_bitcnt_1_.AR = !nx0 ; (1 pterm, 1 signal) j2c_bitcnt_2_.D = !j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # j2c_bitcnt_2_.Q & !j2c_bitcnt_1_.Q # j2c_bitcnt_2_.Q & !j2c_bitcnt_0_.Q ; (3 pterms, 3 signals) j2c_bitcnt_2_.C = !jTCK ; (1 pterm, 1 signal) j2c_bitcnt_2_.AR = !nx0 ; (1 pterm, 1 signal) j2c_reg_clear.D = !( j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q ) ; (1 pterm, 3 signals) j2c_reg_clear.C = !jTCK ; (1 pterm, 1 signal) j2c_reg_clear.CE = j2c_reg_clear_0 ; (1 pterm, 1 signal) j2c_reg_clear.AR = !nx0 ; (1 pterm, 1 signal) j2c_reg_clear_0 = j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # j2c_reg_cmdreg_3_.Q & !j2c_bitcnt_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q ; (2 pterms, 4 signals) j2c_reg_cmdreg_0_.D = j2c_reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c_reg_cmdreg_0_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_cmdreg_0_.CE = jTDI ; (1 pterm, 1 signal) j2c_reg_cmdreg_0_.AP = !reset_n ; (1 pterm, 1 signal) j2c_reg_cmdreg_1_.D = j2c_reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c_reg_cmdreg_1_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_cmdreg_1_.CE = jTDI ; (1 pterm, 1 signal) j2c_reg_cmdreg_1_.AP = !reset_n ; (1 pterm, 1 signal) j2c_reg_cmdreg_2_.D = j2c_reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c_reg_cmdreg_2_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_cmdreg_2_.CE = jTDI ; (1 pterm, 1 signal) j2c_reg_cmdreg_2_.AP = !reset_n ; (1 pterm, 1 signal) j2c_reg_cmdreg_3_.D = jTDI & j2c_reg_shreg_7_.Q ; (1 pterm, 2 signals) j2c_reg_cmdreg_3_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_cmdreg_3_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_0_.D = j2c_reg_shreg_1_.Q & !j2c_reg_shreg_3_.Q & !j2c_reg_shreg_0_.Q # !j2c_reg_shreg_1_.Q & j2c_reg_shreg_3_.Q & !j2c_reg_shreg_0_.Q # !j2c_reg_shreg_1_.Q & !j2c_reg_shreg_3_.Q & j2c_reg_shreg_0_.Q # j2c_reg_shreg_1_.Q & j2c_reg_shreg_3_.Q & j2c_reg_shreg_0_.Q ; (4 pterms, 3 signals) j2c_reg_creg0hm_0_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_0_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_0_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_1_.D = j2c_reg_shreg_2_.Q & !j2c_reg_shreg_3_.Q & !j2c_reg_shreg_0_.Q # !j2c_reg_shreg_2_.Q & j2c_reg_shreg_3_.Q & !j2c_reg_shreg_0_.Q # !j2c_reg_shreg_2_.Q & !j2c_reg_shreg_3_.Q & j2c_reg_shreg_0_.Q # j2c_reg_shreg_2_.Q & j2c_reg_shreg_3_.Q & j2c_reg_shreg_0_.Q ; (4 pterms, 3 signals) j2c_reg_creg0hm_1_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_1_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_1_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_2_.D = j2c_reg_shreg_0_.Q ; (1 pterm, 1 signal) j2c_reg_creg0hm_2_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_2_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_2_.AP = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_3_.D = j2c_reg_shreg_1_.Q & !j2c_reg_shreg_2_.Q & !j2c_reg_shreg_3_.Q # !j2c_reg_shreg_1_.Q & j2c_reg_shreg_2_.Q & !j2c_reg_shreg_3_.Q # !j2c_reg_shreg_1_.Q & !j2c_reg_shreg_2_.Q & j2c_reg_shreg_3_.Q # j2c_reg_shreg_1_.Q & j2c_reg_shreg_2_.Q & j2c_reg_shreg_3_.Q ; (4 pterms, 3 signals) j2c_reg_creg0hm_3_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_3_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_3_.AP = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_4_.D = j2c_reg_shreg_1_.Q ; (1 pterm, 1 signal) j2c_reg_creg0hm_4_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_4_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_4_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_5_.D = j2c_reg_shreg_2_.Q ; (1 pterm, 1 signal) j2c_reg_creg0hm_5_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_5_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_5_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_6_.D = j2c_reg_shreg_3_.Q ; (1 pterm, 1 signal) j2c_reg_creg0hm_6_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_6_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_6_.AP = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_0_.D = j2c_reg_shreg_4_.Q & !j2c_reg_shreg_5_.Q & !j2c_reg_shreg_7_.Q # !j2c_reg_shreg_4_.Q & j2c_reg_shreg_5_.Q & !j2c_reg_shreg_7_.Q # !j2c_reg_shreg_4_.Q & !j2c_reg_shreg_5_.Q & j2c_reg_shreg_7_.Q # j2c_reg_shreg_4_.Q & j2c_reg_shreg_5_.Q & j2c_reg_shreg_7_.Q ; (4 pterms, 3 signals) j2c_reg_creg1hm_0_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_0_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_0_.AP = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_1_.D = j2c_reg_shreg_4_.Q & !j2c_reg_shreg_6_.Q & !j2c_reg_shreg_7_.Q # !j2c_reg_shreg_4_.Q & j2c_reg_shreg_6_.Q & !j2c_reg_shreg_7_.Q # !j2c_reg_shreg_4_.Q & !j2c_reg_shreg_6_.Q & j2c_reg_shreg_7_.Q # j2c_reg_shreg_4_.Q & j2c_reg_shreg_6_.Q & j2c_reg_shreg_7_.Q ; (4 pterms, 3 signals) j2c_reg_creg1hm_1_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_1_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_1_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_2_.D = j2c_reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c_reg_creg1hm_2_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_2_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_2_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_3_.D = j2c_reg_shreg_5_.Q & !j2c_reg_shreg_6_.Q & !j2c_reg_shreg_7_.Q # !j2c_reg_shreg_5_.Q & j2c_reg_shreg_6_.Q & !j2c_reg_shreg_7_.Q # !j2c_reg_shreg_5_.Q & !j2c_reg_shreg_6_.Q & j2c_reg_shreg_7_.Q # j2c_reg_shreg_5_.Q & j2c_reg_shreg_6_.Q & j2c_reg_shreg_7_.Q ; (4 pterms, 3 signals) j2c_reg_creg1hm_3_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_3_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_3_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_4_.D = j2c_reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c_reg_creg1hm_4_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_4_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_4_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_5_.D = j2c_reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c_reg_creg1hm_5_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_5_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_5_.AP = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_6_.D = j2c_reg_shreg_7_.Q ; (1 pterm, 1 signal) j2c_reg_creg1hm_6_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_6_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_6_.AP = !reset_n ; (1 pterm, 1 signal) j2c_reg_rstout_n_i.D = j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q ; (1 pterm, 3 signals) j2c_reg_rstout_n_i.C = !jTCK ; (1 pterm, 1 signal) j2c_reg_rstout_n_i.CE = j2c_reg_clear_0 ; (1 pterm, 1 signal) j2c_reg_rstout_n_i.AP = !nx0 ; (1 pterm, 1 signal) j2c_reg_shreg_0_.D = j2c_reg_shreg_1_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_0_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_1_.D = j2c_reg_shreg_2_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_1_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_2_.D = j2c_reg_shreg_3_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_2_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_3_.D = j2c_reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_3_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_4_.D = j2c_reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_4_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_5_.D = j2c_reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_5_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_6_.D = j2c_reg_shreg_7_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_6_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_7_.D = jTDI ; (1 pterm, 1 signal) j2c_reg_shreg_7_.C = jTCK ; (1 pterm, 1 signal) jTDO = !( !DIS_JTG & j2c_reg_cmdreg_2_.Q & j2c_reg_cmdreg_1_.Q & j2c_bitcnt_2_.Q & !j2c_bitcnt_0_.Q & !ix369 & !ix381 & !ix393 # !DIS_JTG & !ix47 & !ix59 & j2c_reg_cmdreg_2_.Q & j2c_reg_cmdreg_1_.Q & !ix71 & j2c_bitcnt_0_.Q # !DIS_JTG & ix1442 & j2c_reg_cmdreg_2_.Q & !j2c_reg_cmdreg_1_.Q & !j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !DIS_JTG & ix1344 & j2c_reg_cmdreg_2_.Q & !j2c_reg_cmdreg_1_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !DIS_JTG & ix1340 & j2c_reg_cmdreg_2_.Q & !j2c_reg_cmdreg_1_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & ix1374 & j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !DIS_JTG & ix1254 & j2c_reg_cmdreg_2_.Q & j2c_bitcnt_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !DIS_JTG & ix1454 & j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & ix1422 & j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & ix1231 & j2c_reg_cmdreg_2_.Q & j2c_bitcnt_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & j2c_reg_cmdreg_1_.Q & !j2c_bitcnt_2_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & !j2c_reg_cmdreg_2_.Q & nx1093 # !DIS_JTG & j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_2_.Q & !j2c_reg_cmdreg_1_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & j2c_reg_cmdreg_1_.Q & !j2c_bitcnt_1_.Q # DIS_JTG & !SDA.PIN ) ; (15 pterms, 23 signals) jTDO.OE = nx191 ; (1 pterm, 1 signal) ni_nires_reg_clear_n_i.D = reset_n & j2c_reg_rstout_n_i.Q ; (1 pterm, 2 signals) ni_nires_reg_clear_n_i.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data0neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_0_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_1_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_2_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_3_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_4_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_5_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_6_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_7_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_8_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_9_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_0_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_1_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_2_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_3_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_4_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_5_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_6_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_7_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_8_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_9_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_0_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_1_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_2_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_3_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_4_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_5_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_6_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_7_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_8_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_9_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_0_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_1_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_2_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_3_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_4_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_5_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_6_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_7_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_8_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_9_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_0_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_1_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_2_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_3_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_4_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_5_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_6_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_7_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_8_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_9_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_0_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_1_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_2_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_3_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_4_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_5_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_6_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_7_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_8_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_9_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_0_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_1_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_2_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_3_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_4_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_5_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_6_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_7_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_8_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_9_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_0_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_1_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_2_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_3_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_4_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_5_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_6_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_7_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_8_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_9_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data_out_0_.D = !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_0_.Q # ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_0_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_0_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_0_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_0_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_10_.D = ni_nires_reg_data0pos_0_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_0_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_0_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_0_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_10_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_11_.D = !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3pos_1_.Q # ni_nires_reg_data1pos_1_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2pos_1_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0pos_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_11_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_12_.D = ni_nires_reg_data0pos_2_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_2_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_2_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_2_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_12_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_13_.D = ni_nires_reg_data0pos_3_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_3_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_3_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_3_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_13_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_14_.D = ni_nires_reg_data0pos_4_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_4_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_4_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_4_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_14_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_15_.D = ni_nires_reg_data0pos_5_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_5_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_5_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_5_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_15_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_16_.D = ni_nires_reg_data0pos_6_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_6_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_6_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_6_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_16_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_17_.D = ni_nires_reg_data0pos_7_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_7_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_7_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_7_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_17_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_18_.D = ni_nires_reg_data0pos_8_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_8_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_8_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_8_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_18_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_19_.D = ni_nires_reg_data0pos_9_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_9_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_9_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_9_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_19_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_1_.D = !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_1_.Q # ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_1_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_1_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_1_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_2_.D = !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_2_.Q # ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_2_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_2_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_2_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_2_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_3_.D = !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_3_.Q # ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_3_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_3_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_3_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_3_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_4_.D = !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_4_.Q # ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_4_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_4_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_4_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_4_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_5_.D = !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_5_.Q # ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_5_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_5_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_5_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_5_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_6_.D = !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_6_.Q # ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_6_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_6_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_6_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_6_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_7_.D = !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_7_.Q # ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_7_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_7_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_7_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_7_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_8_.D = !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_8_.Q # ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_8_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_8_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_8_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_8_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_9_.D = !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_9_.Q # ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_9_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_9_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_9_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_9_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_gray_cnt_0_.D = !ni_nires_reg_gray_cnt_1_.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cnt_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_gray_cnt_0_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cnt_1_.D = ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cnt_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_gray_cnt_1_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cntf_0_.D = !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cntf_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_gray_cntf_0_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cntf_1_.D = ni_nires_reg_gray_cntf_0_.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cntf_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_gray_cntf_1_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_new_cnt_0_.D = ni_nires_reg_gray_cntf_0_.Q ; (1 pterm, 1 signal) ni_nires_reg_new_cnt_0_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_new_cnt_0_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_new_cnt_1_.D = ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 1 signal) ni_nires_reg_new_cnt_1_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_new_cnt_1_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_0_.D = !ni_nires_reg_old_cnt_1_.Q ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_0_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_0_.CE = nx973 ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_0_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_1_.D = ni_nires_reg_old_cnt_0_.Q ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_1_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_1_.CE = nx973 ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_1_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_valid.D = ni_nires_reg_new_cnt_0_.Q & !ni_nires_reg_old_cnt_0_.Q # !ni_nires_reg_new_cnt_0_.Q & ni_nires_reg_old_cnt_0_.Q # ni_nires_reg_old_cnt_1_.Q & !ni_nires_reg_new_cnt_1_.Q # !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_new_cnt_1_.Q ; (4 pterms, 4 signals) ni_nires_reg_valid.C = clk ; (1 pterm, 1 signal) ni_pattcount_0_.D = !ni_pattcount_0_.Q ; (1 pterm, 1 signal) ni_pattcount_0_.C = clk ; (1 pterm, 1 signal) ni_pattcount_1_.D = ni_pattcount_1_.Q & !ni_pattcount_0_.Q # !ni_pattcount_1_.Q & ni_pattcount_0_.Q ; (2 pterms, 2 signals) ni_pattcount_1_.C = clk ; (1 pterm, 1 signal) ni_pattcount_2_.D = !ni_pattcount_2_.Q & ni_pattcount_1_.Q & ni_pattcount_0_.Q # ni_pattcount_2_.Q & !ni_pattcount_1_.Q # ni_pattcount_2_.Q & !ni_pattcount_0_.Q ; (3 pterms, 3 signals) ni_pattcount_2_.C = clk ; (1 pterm, 1 signal) ni_pattcount_3_.D = ni_pattcount_2_.Q & ni_pattcount_1_.Q & ni_pattcount_0_.Q & !ni_pattcount_3_.Q # !ni_pattcount_0_.Q & ni_pattcount_3_.Q # !ni_pattcount_1_.Q & ni_pattcount_3_.Q # !ni_pattcount_2_.Q & ni_pattcount_3_.Q ; (4 pterms, 4 signals) ni_pattcount_3_.C = clk ; (1 pterm, 1 signal) ni_pattcount_4_.D.X1 = ni_pattcount_2_.Q & ni_pattcount_1_.Q & ni_pattcount_0_.Q & ni_pattcount_3_.Q ; (1 pterm, 4 signals) ni_pattcount_4_.D.X2 = ni_pattcount_4_.Q ; (1 pterm, 1 signal) ni_pattcount_4_.C = clk ; (1 pterm, 1 signal) ni_reg_ce_prty_bit_neg.D = TX_EN.Q & TXD_8_.Q & !ix1681 & !ix1687 # TX_EN.Q & !TXD_8_.Q & ix1681 & !ix1687 # TX_EN.Q & !TXD_8_.Q & !ix1681 & ix1687 # TX_EN.Q & TXD_8_.Q & ix1681 & ix1687 ; (4 pterms, 4 signals) ni_reg_ce_prty_bit_neg.C = clk ; (1 pterm, 1 signal) ni_reg_ce_prty_bit_pos.D.X1 = TX_EN.Q & !ix1809 & !ix1811 & !ix1813 # TX_EN.Q & !ix1809 & ix1811 & ix1813 # TX_EN.Q & ix1809 & !ix1811 & ix1813 # TX_EN.Q & ix1809 & ix1811 & !ix1813 ; (4 pterms, 4 signals) ni_reg_ce_prty_bit_pos.D.X2 = !TXD_0_.Q & TX_EN.Q ; (1 pterm, 2 signals) ni_reg_ce_prty_bit_pos.C = clk ; (1 pterm, 1 signal) ni_reg_prty_bit_neg_r.D = ix1340 & ni_nires_reg_data_out_14_.Q & ix1344 & !ix1374 & !ix1422 & nx1439 # ni_nires_reg_data_out_12_.Q & nx1369 & !ix1374 & ix1422 & nx1439 # ni_nires_reg_data_out_12_.Q & ix1374 & !ix1422 & nx1439 & !nx1755 # ni_nires_reg_data_out_13_.Q & ix1374 & !ix1422 & nx1439 & nx1755 # ni_nires_reg_data_out_13_.Q & !ix1344 & !ix1374 & !ix1422 & nx1439 # ni_nires_reg_data_out_13_.Q & !ix1340 & !ix1374 & !ix1422 & nx1439 # !ix1442 & ix1454 & !nx2090 # ni_nires_reg_data_out_10_.Q & !ix1254 & nx1439 & nx1491 # ix1254 & nx1369 & nx1439 & nx1491 & ni_nires_reg_data_out_11_.Q # ni_nires_reg_data_out_10_.Q & !nx1369 & nx1439 & nx1491 # !nx1369 & !ix1374 & ix1422 & nx1439 & ni_nires_reg_data_out_11_.Q # !ix1454 & !nx2043 ; (12 pterms, 18 signals) ni_reg_prty_bit_neg_r.C = clk ; (1 pterm, 1 signal) ni_reg_prty_bit_pos_r.D = !ix1374 & ix1422 & !ix1442 & ix1454 & !nx1625 & ni_nires_reg_data_out_5_.Q # !ix1374 & ix1422 & !ix1442 & ix1454 & nx1625 & ni_nires_reg_data_out_6_.Q # ix1340 & ix1344 & !ix1374 & !ix1422 & nx1439 & ni_nires_reg_data_out_4_.Q # ix1374 & !ix1422 & !ix1442 & ix1454 & nx1689 & ni_nires_reg_data_out_7_.Q # ix1374 & !ix1422 & !ix1442 & ix1454 & !nx1689 & ni_nires_reg_data_out_6_.Q # !ix1340 & !ix1374 & !ix1422 & !ix1442 & ix1454 & ni_nires_reg_data_out_7_.Q # ix1374 & !ix1422 & nx1439 & !nx1755 & ni_nires_reg_data_out_2_.Q # ix1374 & !ix1422 & nx1439 & nx1755 & ni_nires_reg_data_out_3_.Q # !ix1344 & !ix1374 & !ix1422 & nx1439 & ni_nires_reg_data_out_3_.Q # !ix1340 & !ix1374 & !ix1422 & nx1439 & ni_nires_reg_data_out_3_.Q # !ix1442 & ix1454 & nx1491 & !nx1597 # ix1340 & !ix1374 & !ix1422 & !ix1442 & ix1454 & ni_nires_reg_data_out_8_.Q # !nx1303 & !ix1374 & ix1422 & nx1439 # nx1439 & !nx1459 & nx1491 # !ix1454 & !nx1507 ; (15 pterms, 22 signals) ni_reg_prty_bit_pos_r.C = clk ; (1 pterm, 1 signal) nx0 = !( !DIS_JTG & !jTMS ) ; (1 pterm, 2 signals) nx1093 = !( j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_1_.Q & !j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_3_2_.Q # !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_1_.Q & !j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_2_2_.Q # j2c_reg_cmdreg_0_.Q & !j2c_reg_cmdreg_1_.Q & j2c_bitcnt_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_1_5_.Q # !j2c_reg_cmdreg_0_.Q & !j2c_reg_cmdreg_1_.Q & ID_0_5_.Q & j2c_bitcnt_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_1_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_3_6_.Q # !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_1_.Q & ID_2_6_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # j2c_reg_cmdreg_0_.Q & !j2c_reg_cmdreg_1_.Q & j2c_bitcnt_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_1_4_.Q # !j2c_reg_cmdreg_0_.Q & !j2c_reg_cmdreg_1_.Q & ID_0_4_.Q & j2c_bitcnt_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # j2c_reg_cmdreg_0_.Q & !j2c_reg_cmdreg_1_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_1_6_.Q # !j2c_reg_cmdreg_0_.Q & !j2c_reg_cmdreg_1_.Q & ID_0_6_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # FAULT & j2c_reg_cmdreg_1_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !j2c_reg_cmdreg_0_.Q & !nx2404 & !j2c_reg_cmdreg_1_.Q & !j2c_bitcnt_2_.Q # !nx2344 & j2c_reg_cmdreg_0_.Q & !j2c_reg_cmdreg_1_.Q & !j2c_bitcnt_2_.Q # j2c_reg_cmdreg_1_.Q & j2c_bitcnt_2_.Q & nx2010 # j2c_reg_cmdreg_1_.Q & !j2c_bitcnt_2_.Q & !nx1117 # !nx2457 ) ; (16 pterms, 21 signals) nx1117 = !( !j2c_reg_cmdreg_0_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_2_0_.Q # j2c_reg_cmdreg_0_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_3_3_.Q # !j2c_reg_cmdreg_0_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_2_3_.Q # j2c_reg_cmdreg_0_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_3_1_.Q # !j2c_reg_cmdreg_0_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_2_1_.Q # j2c_reg_cmdreg_0_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_3_0_.Q ) ; (6 pterms, 9 signals) nx1267 = ix1231 & ix1254 & !ix1340 & !ix1344 ; (1 pterm, 4 signals) nx1303 = !nx1369 & !ni_nires_reg_data_out_1_.Q # nx1369 & !ni_nires_reg_data_out_2_.Q ; (2 pterms, 3 signals) nx1369 = ix1231 & ix1340 & ix1344 ; (1 pterm, 3 signals) nx1439 = ix1442 & ix1454 ; (1 pterm, 2 signals) nx1459 = ix1254 & nx1369 & !ni_nires_reg_data_out_1_.Q # !nx1369 & !ni_nires_reg_data_out_0_.Q # !ix1254 & !ni_nires_reg_data_out_0_.Q ; (3 pterms, 4 signals) nx1491 = ix1374 & ix1422 ; (1 pterm, 2 signals) nx1507.X1 = ix1340 & !ni_nires_reg_data_out_9_.Q # ix1231 & ix1254 & !ix1340 & ix1344 & !ni_nires_reg_data_out_8_.Q & ni_nires_reg_data_out_9_.Q # ix1231 & ix1254 & !ix1340 & ix1344 & ni_nires_reg_data_out_8_.Q & !ni_nires_reg_data_out_9_.Q ; (3 pterms, 6 signals) nx1507.X2 = !ix1340 & !ni_nires_reg_data_out_8_.Q ; (1 pterm, 2 signals) nx1597 = !ix1254 & !ix1344 & !ni_nires_reg_data_out_4_.Q # ix1344 & nx1625 & !ni_nires_reg_data_out_5_.Q # ix1254 & nx1625 & !ni_nires_reg_data_out_5_.Q # !nx1625 & !ni_nires_reg_data_out_4_.Q ; (4 pterms, 5 signals) nx1625 = ix1231 & ix1340 # ix1340 & ix1344 ; (2 pterms, 3 signals) nx1689 = !( !ix1231 & !ix1254 & !ix1344 # !ix1340 ) ; (2 pterms, 4 signals) nx1755 = ix1254 & ix1340 & ix1344 # ix1231 & ix1340 & ix1344 ; (2 pterms, 4 signals) nx1795 = !( !nx1267 & nx1439 # !nx1267 & ix1454 & nx1491 ) ; (2 pterms, 4 signals) nx1827 = !ix1374 & !ix1422 & !nx1439 # !nx1439 & !ix1454 # nx1267 ; (3 pterms, 5 signals) nx191 = DIS_JTG # jTCK & nx0 ; (2 pterms, 3 signals) nx2010 = j2c_reg_cmdreg_0_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_3_5_.Q # !j2c_reg_cmdreg_0_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_2_4_.Q # !j2c_reg_cmdreg_0_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_2_5_.Q # j2c_reg_cmdreg_0_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_3_4_.Q ; (4 pterms, 7 signals) nx2043.X1 = ix1340 & !ni_nires_reg_data_out_19_.Q # ix1231 & ix1254 & !ix1340 & ix1344 & !ni_nires_reg_data_out_18_.Q & ni_nires_reg_data_out_19_.Q # ix1231 & ix1254 & !ix1340 & ix1344 & ni_nires_reg_data_out_18_.Q & !ni_nires_reg_data_out_19_.Q ; (3 pterms, 6 signals) nx2043.X2 = !ix1340 & !ni_nires_reg_data_out_18_.Q ; (1 pterm, 2 signals) nx2090 = !( ni_nires_reg_data_out_15_.Q & !ix1374 & ix1422 & !nx1625 # ix1374 & !ix1422 & ni_nires_reg_data_out_16_.Q & !nx1689 # ix1374 & !ix1422 & ni_nires_reg_data_out_17_.Q & nx1689 # !ix1374 & ix1422 & ni_nires_reg_data_out_16_.Q & nx1625 # ix1340 & !ix1374 & !ix1422 & ni_nires_reg_data_out_18_.Q # !ix1340 & !ix1374 & !ix1422 & ni_nires_reg_data_out_17_.Q # nx1491 & !nx2116 ) ; (7 pterms, 11 signals) nx2116 = !ix1254 & !ni_nires_reg_data_out_14_.Q & !ix1344 # ix1344 & !ni_nires_reg_data_out_15_.Q & nx1625 # ix1254 & !ni_nires_reg_data_out_15_.Q & nx1625 # !ni_nires_reg_data_out_14_.Q & !nx1625 ; (4 pterms, 5 signals) nx2344 = !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & !ID_1_1_.Q # j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & !ID_1_2_.Q # j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & !ID_1_3_.Q # !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & !ID_1_0_.Q ; (4 pterms, 6 signals) nx2387 = !( ID_0_7_.Q & ID_0_6_.Q & ID_0_5_.Q & ID_0_4_.Q & ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q ) ; (1 pterm, 8 signals) nx240 = TX_EN.Q & nx1267 # !nx1267 & ni_nires_reg_valid.Q ; (2 pterms, 3 signals) nx2404 = !ID_0_0_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !ID_0_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !ID_0_1_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !ID_0_3_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q ; (4 pterms, 6 signals) nx2457 = !( !j2c_reg_cmdreg_0_.Q & !j2c_reg_cmdreg_1_.Q & ID_0_7_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # FAULT & j2c_reg_cmdreg_0_.Q & !j2c_reg_cmdreg_1_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q ) ; (2 pterms, 7 signals) nx973 = ni_nires_reg_new_cnt_0_.Q & !ni_nires_reg_old_cnt_0_.Q # !ni_nires_reg_new_cnt_0_.Q & ni_nires_reg_old_cnt_0_.Q # ni_nires_reg_old_cnt_1_.Q & !ni_nires_reg_new_cnt_1_.Q # !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_new_cnt_1_.Q ; (4 pterms, 4 signals)