Timing Report // Project = oase // Family = lc4k // Device = LC4256V // Speed = -3 // Voltage = 3.3 // Operating Condition = COM // Data sheet version = 3.2 // Pass Bidirection = OFF // Pass S/R = OFF // Pass Latch = OFF // Pass Clock = OFF // Maximum Paths = 20 // T_SU Endpoints D/T inputs = ON // T_SU Endpoints CE inputs = OFF // T_SU Endpoints S/R inputs = OFF // T_SU Endpoints RAM gated = ON // Fmax of CE = ON // Fmax of RAM = ON // Location(From => To) // Pin number: numeric number preceded by "p", BGA number as is // Macrocell number: Segment#,GLB#,Macrocell# // Segment#: starts from 0 (if applicable) // GLB#: starts from A..Z, AA..ZZ // Macrocell#: starts from 0 to 31 Summary for Timing Constraints: -- fMAX_0 = 7.95 ns ( 8.00) : passed with slack = 0.05 (125.79 MHz) -- fMAX_1 = 4.95 ns ( 8.33) : passed with slack = 3.38 (202.02 MHz) -- fMAX_2 = 7.00 ns (1000.00) : passed with slack = 993.00 (142.86 MHz) Total constraints: 3, passed: 3, not passed: 0 fMAX_0 = 8.00 , "clk ", "clk "; Slack Req. Delay Level Location(From => To) Source Destination Destination_Clock ===== ==== ===== ===== ==================== ====== =========== ================= 0.05 8.00 7.95 3 D10 => P0 ni_nires_reg_data_out_14_.C ni_reg_prty_bit_neg_r.D clk 0.80 8.00 7.20 2 K11 => O6 TX_EN.C TXD_0_.CE clk 0.80 8.00 7.20 2 K11 => O10 TX_EN.C TXD_1_.CE clk 0.80 8.00 7.20 2 K11 => O12 TX_EN.C TXD_2_.CE clk 0.80 8.00 7.20 2 K11 => N13 TX_EN.C TXD_3_.CE clk 0.80 8.00 7.20 2 K11 => N11 TX_EN.C TXD_4_.CE clk 0.80 8.00 7.20 2 K11 => N9 TX_EN.C TXD_5_.CE clk 0.80 8.00 7.20 2 K11 => N2 TX_EN.C TXD_6_.CE clk 0.80 8.00 7.20 2 K11 => M12 TX_EN.C TXD_7_.CE clk 0.80 8.00 7.20 2 K11 => M6 TX_EN.C TXD_8_.CE clk 0.80 8.00 7.20 2 K11 => M8 TX_EN.C TXD_9_.CE clk 0.80 8.00 7.20 2 K11 => L6 TX_EN.C TXD_10_.CE clk 0.80 8.00 7.20 2 K11 => L9 TX_EN.C TXD_11_.CE clk 0.80 8.00 7.20 2 K11 => L10 TX_EN.C TXD_12_.CE clk 0.80 8.00 7.20 2 K11 => L1 TX_EN.C TXD_13_.CE clk 0.80 8.00 7.20 2 K11 => K2 TX_EN.C TXD_14_.CE clk 0.80 8.00 7.20 2 K11 => K12 TX_EN.C TXD_15_.CE clk 0.90 8.00 7.10 2 D5 => D5 ni_nires_reg_old_cnt_0_.C ni_nires_reg_old_cnt_0_.CE clk 0.90 8.00 7.10 2 D5 => D6 ni_nires_reg_old_cnt_0_.C ni_nires_reg_old_cnt_1_.CE clk 1.00 8.00 7.00 2 G11 => G4 ID_2_2_.C ID_2_0_.CE clk fMAX_1 = 8.33 , "NI_STR ", "NI_STR "; Slack Req. Delay Level Location(From => To) Source Destination Destination_Clock ===== ==== ===== ===== ==================== ====== =========== ================= 3.38 8.33 4.95 1 D4 => P1 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data0neg_0_.CE NI_STR 3.38 8.33 4.95 1 D4 => N15 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data0neg_1_.CE NI_STR 3.38 8.33 4.95 1 D4 => P5 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data0neg_2_.CE NI_STR 3.38 8.33 4.95 1 D4 => B14 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data0neg_3_.CE NI_STR 3.38 8.33 4.95 1 D4 => M13 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data0neg_4_.CE NI_STR 3.38 8.33 4.95 1 D4 => J12 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data0neg_5_.CE NI_STR 3.38 8.33 4.95 1 D4 => M0 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data0neg_6_.CE NI_STR 3.38 8.33 4.95 1 D4 => P9 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data0neg_7_.CE NI_STR 3.38 8.33 4.95 1 D4 => P11 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data0neg_8_.CE NI_STR 3.38 8.33 4.95 1 D4 => M3 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data0neg_9_.CE NI_STR 3.38 8.33 4.95 1 D4 => P2 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data1neg_0_.CE NI_STR 3.38 8.33 4.95 1 D4 => N4 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data1neg_1_.CE NI_STR 3.38 8.33 4.95 1 D4 => P6 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data1neg_2_.CE NI_STR 3.38 8.33 4.95 1 D4 => B15 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data1neg_3_.CE NI_STR 3.38 8.33 4.95 1 D4 => M14 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data1neg_4_.CE NI_STR 3.38 8.33 4.95 1 D4 => J13 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data1neg_5_.CE NI_STR 3.38 8.33 4.95 1 D4 => P8 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data1neg_6_.CE NI_STR 3.38 8.33 4.95 1 D4 => P10 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data1neg_7_.CE NI_STR 3.38 8.33 4.95 1 D4 => P12 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data1neg_8_.CE NI_STR 3.38 8.33 4.95 1 D4 => M4 ni_nires_reg_gray_cntf_1_.C ni_nires_reg_data1neg_9_.CE NI_STR fMAX_2 = 1000.00 , "jTCK ", "jTCK "; Slack Req. Delay Level Location(From => To) Source Destination Destination_Clock ===== ==== ===== ===== ==================== ====== =========== ================= 993.00 1000.00 7.00 2 G9 => G6 j2c_bitcnt_1_.C j2c_reg_clear.CE jTCK 993.00 1000.00 7.00 2 G9 => G7 j2c_bitcnt_1_.C j2c_reg_rstout_n_i.CE jTCK 996.75 1000.00 3.25 1 G10 => G10 j2c_bitcnt_0_.C j2c_bitcnt_0_.D jTCK 996.75 1000.00 3.25 1 G9 => G9 j2c_bitcnt_1_.C j2c_bitcnt_1_.D jTCK 996.75 1000.00 3.25 1 G9 => G5 j2c_bitcnt_1_.C j2c_bitcnt_2_.D jTCK 996.75 1000.00 3.25 1 G9 => G6 j2c_bitcnt_1_.C j2c_reg_clear.D jTCK 996.75 1000.00 3.25 1 G9 => G7 j2c_bitcnt_1_.C j2c_reg_rstout_n_i.D jTCK 996.85 1000.00 3.15 1 H6 => K10 j2c_reg_shreg_4_.C j2c_reg_shreg_3_.D jTCK 996.85 1000.00 3.15 1 K8 => C3 j2c_reg_shreg_6_.C j2c_reg_shreg_5_.D jTCK 996.85 1000.00 3.15 1 F3 => K8 j2c_reg_shreg_7_.C j2c_reg_shreg_6_.D jTCK 996.90 1000.00 3.10 1 F6 => F11 j2c_reg_shreg_1_.C j2c_reg_shreg_0_.D jTCK 996.90 1000.00 3.10 1 F7 => F6 j2c_reg_shreg_2_.C j2c_reg_shreg_1_.D jTCK 996.90 1000.00 3.10 1 K10 => F7 j2c_reg_shreg_3_.C j2c_reg_shreg_2_.D jTCK 996.90 1000.00 3.10 1 C3 => H6 j2c_reg_shreg_5_.C j2c_reg_shreg_4_.D jTCK