TDA  - Timing Driven Analyze 
Ver. 1.0, supported by Lattice Semiconductor
ispLEVER 6.01 Copyright 1992-2006 Lattice Semiconductor. All Rights Reserved.
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Summary for Timing Constraints:

Goal: Clock Period on clock domain "clk" of 8.00ns (125.00MHz) is met.
      Worst case path:
      From  : ni_nires__reg_data_out_2_.C
      to    : TXD_0_.D
      Actual: 7.95ns (125.79MHz)
      Slack : 0.05ns

Goal: Clock Period on clock domain "NI_STR" of 8.33ns (120.05MHz) is met.
      Worst case path:
      From  : ni_nires__reg_gray_cntf_1_.C
      to    : ni_nires__reg_data0neg_0_.CE
      Actual: 4.90ns (204.08MHz)
      Slack : 3.43ns

Goal: Clock Period on clock domain "jTCK" of 1000.00ns (1.00MHz) is met.
      Worst case path:
      From  : j2c__bitcnt_0_.C
      to    : j2c__reg_rstout_n_i.CE
      Actual: 6.95ns (143.88MHz)
      Slack : 993.05ns

  Total constraints: 3, passed: 3, not passed: 0