ispLEVER 6.1.00.38.44.06 Fitter Report File
Copyright(C), 1992-2005, Lattice Semiconductor Corporation
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Project Name : oase Project Path : M:\REFERENCE\SIM\PROJECTS\ORI\lattice_ena_shdn Project Fitted on : Mon Sep 10 14:07:52 2007 Device : M4256_64 Package : 100 GLB Input Mux Size : 33 Available Blocks : 16 Speed : -3 Part Number : LC4256V-3T100C Source Format : EDIF Project 'oase' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.16 secs Partition Time 7.57 secs Place Time 14.14 secs Route Time 0.39 secs Total Fit Time 00:00:22 Design_Summary
Total Input Pins 19 Total Logic Functions 247 Total Output Pins 26 Total Bidir I/O Pins 3 Total Buried Nodes 218 Total Flip-Flops 192 Total D Flip-Flops 182 Total T Flip-Flops 10 Total Latches 0 Total Product Terms 1027 Total Reserved Pins 1 Total Locked Pins 48 Total Locked Nodes 0 Total Unique Output Enables 3 Total Unique Clocks 6 Total Unique Clock Enables 16 Total Unique Resets 4 Total Unique Presets 2 Fmax Logic Levels 5 Device_Resource_Summary
Device Total Used Not Used Utilization ----------------------------------------------------------------------- Dedicated Pins Clock/Input Pins 4 2 2 --> 50 Input-Only Pins 6 0 6 --> 0 I/O / Enable Pins 2 1 1 --> 50 I/O Pins 62 45 17 --> 72 Logic Functions 256 247 9 --> 96 Input Registers 64 0 64 --> 0 GLB Inputs 576 492 84 --> 85 Logical Product Terms 1280 837 443 --> 65 Occupied GLBs 16 16 0 --> 100 Macrocells 256 247 9 --> 96 Control Product Terms: GLB Clock/Clock Enables 16 16 0 --> 100 GLB Reset/Presets 16 0 16 --> 0 Macrocell Clocks 256 42 214 --> 16 Macrocell Clock Enables 256 142 114 --> 55 Macrocell Enables 256 0 256 --> 0 Macrocell Resets 256 15 241 --> 5 Macrocell Presets 256 4 252 --> 1 Global Routing Pool 324 255 69 --> 78 GRP from IFB .. 19 .. --> .. (from input signals) .. 18 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 1 .. --> .. GRP from MFB .. 236 .. --> .. ---------------------------------------------------------------------- <Note> 1 : The available PT is the product term that has not been used. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT --- Fanin --- I/O Input Macrocells Macrocells Logic clusters Unique Shared Total Pins Regs Used Inaccessible available PTs used ------------------------------------------------------------------------------------------- Maximum GLB 36 *(1) 8 -- -- 16 80 16 ------------------------------------------------------------------------------------------- GLB A 26 6 32 0/4 0 15 0 1 43 15 GLB B 24 8 32 4/4 0 16 0 0 46 16 GLB C 24 8 32 3/4 0 15 0 1 46 15 GLB D 9 16 25 4/4 0 15 1 0 57 16 ------------------------------------------------------------------------------------------- GLB E 22 11 33 4/4 0 16 0 0 54 16 GLB F 19 14 33 3/4 0 16 0 0 49 16 GLB G 24 9 33 0/4 0 16 0 0 52 16 GLB H 16 9 25 0/4 0 16 0 0 44 16 ------------------------------------------------------------------------------------------- GLB I 10 12 22 1/4 0 16 0 0 35 15 GLB J 9 16 25 4/4 0 16 0 0 45 15 GLB K 7 25 32 4/4 0 15 0 1 62 15 GLB L 7 25 32 4/4 0 16 0 0 70 16 ------------------------------------------------------------------------------------------- GLB M 16 20 36 4/4 0 15 0 1 45 14 GLB N 8 28 36 4/4 0 13 2 1 73 16 GLB O 7 27 34 4/4 0 15 1 0 65 16 GLB P 5 25 30 2/4 0 16 0 0 51 15 ------------------------------------------------------------------------------------------- TOTALS: 233 259 492 45/64 0 247 4 5 837 248 <Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Rst/Pr | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 16 16 16 16 16 ============================================================================== GLB A 1 0 1 13 0 0 0 GLB B 1 0 6 8 0 0 0 GLB C 1 0 5 11 0 2 0 GLB D 1 0 0 13 0 0 0 ------------------------------------------------------------------------------ GLB E 1 0 7 8 0 0 0 GLB F 1 0 0 4 0 2 2 GLB G 1 0 6 6 0 6 0 GLB H 1 0 4 12 0 0 0 ------------------------------------------------------------------------------ GLB I 1 0 1 13 0 1 0 GLB J 1 0 0 4 0 0 0 GLB K 1 0 0 7 0 2 0 GLB L 1 0 4 12 0 2 2 ------------------------------------------------------------------------------ GLB M 1 0 0 3 0 0 0 GLB N 1 0 4 8 0 0 0 GLB O 1 0 4 10 0 0 0 GLB P 1 0 0 10 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : Yes @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : Yes Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : No Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : FMAX Fmax_Logic_Level : 1 D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 80 Max Symbols : 24 @Utilization_options Max. % of Macrocells used : 100 @Usercode (HEX) @IO_Types Default = LVCMOS18 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_UP (2) @Fast_Bypass Default = None (2) @ORP_Bypass Default = None @Input_Registers Default = None (2) @Register_Powerup Default = None Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal| Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name ----------------------------------------------------------------------------------------- 1 | GND | - | | | | | 2 | TDI | - | | | | | 3 | I_O | 0 |C12 | * |LVCMOS33 | Output|SD2ANL 4 | I_O | 0 |C10 | | | | 5 | I_O | 0 |C6 | * |LVCMOS18 | Input |Reserved_Pin_274 6 | I_O | 0 |C2 | * |LVCMOS33 | Input |NI_STR 7 |GNDIO0 | - | | | | | 8 | I_O | 0 |D12 | * |LVCMOS33 | Input |NI_D_9_ 9 | I_O | 0 |D10 | * |LVCMOS33 | Input |NI_D_8_ 10 | I_O | 0 |D6 | * |LVCMOS33 | Input |NI_D_7_ 11 | I_O | 0 |D4 | * |LVCMOS33 | Input |NI_D_6_ 12 | IN0 | 0 | | | | | 13 |VCCIO0 | - | | | | | 14 | I_O | 0 |E4 | * |LVCMOS33 | Input |NI_D_5_ 15 | I_O | 0 |E6 | * |LVCMOS33 | Input |NI_D_4_ 16 | I_O | 0 |E10 | * |LVCMOS33 | Input |NI_D_3_ 17 | I_O | 0 |E12 | * |LVCMOS33 | Input |NI_D_2_ 18 |GNDIO0 | - | | | | | 19 | I_O | 0 |F2 | * |LVCMOS33 | Input |NI_D_1_ 20 | I_O | 0 |F6 | * |LVCMOS33 | Input |NI_D_0_ 21 | I_O | 0 |F10 | * |LVCMOS33 |Tri-Out|jTDO 22 | I_O | 0 |F12 | | | | 23 | IN1 | 0 | | | | | 24 | TCK | - | | | | | 25 | VCC | - | | | | | 26 | GND | - | | | | | 27 | IN2 | 0 | | | | | 28 | I_O | 0 |G12 | | | | 29 | I_O | 0 |G10 | | | | 30 | I_O | 0 |G6 | | | | 31 | I_O | 0 |G2 | | | | 32 |GNDIO0 | - | | | | | 33 |VCCIO0 | - | | | | | 34 | I_O | 0 |H12 | | | | 35 | I_O | 0 |H10 | | | | 36 | I_O | 0 |H6 | | | | 37 | I_O | 0 |H2 | | | | 38 |INCLK1 | 0 | | * |LVCMOS33 | Input |jTCK 39 |INCLK2 | 1 | | | | | 40 | VCC | - | | | | | 41 | I_O | 1 |I2 | | | | 42 | I_O | 1 |I6 | | | | 43 | I_O | 1 |I10 | | | | 44 | I_O | 1 |I12 | * |LVCMOS33 | Output|TESTEN 45 |VCCIO1 | - | | | | | 46 |GNDIO1 | - | | | | | 47 | I_O | 1 |J2 | * |LVCMOS33 | Output|PRBSEN 48 | I_O | 1 |J6 | * |LVCMOS33 | Output|LCKREFN 49 | I_O | 1 |J10 | * |LVCMOS33 | Output|ENABLE 50 | I_O | 1 |J12 | * |LVCMOS33 | Output|TX_ER 51 | GND | - | | | | | 52 | TMS | - | | | | | 53 | I_O | 1 |K12 | * |LVCMOS33 | Output|LOOPEN 54 | I_O | 1 |K10 | * |LVCMOS33 | Output|TX_EN 55 | I_O | 1 |K6 | * |LVCMOS33 | Output|TXD_15_ 56 | I_O | 1 |K2 | * |LVCMOS33 | Output|TXD_14_ 57 |GNDIO1 | - | | | | | 58 | I_O | 1 |L12 | * |LVCMOS33 | Output|TXD_13_ 59 | I_O | 1 |L10 | * |LVCMOS33 | Output|TXD_12_ 60 | I_O | 1 |L6 | * |LVCMOS33 | Output|TXD_11_ 61 | I_O | 1 |L4 | * |LVCMOS33 | Output|TXD_10_ 62 | IN3 | 1 | | | | | 63 |VCCIO1 | - | | | | | 64 | I_O | 1 |M4 | * |LVCMOS33 | Output|TXD_9_ 65 | I_O | 1 |M6 | * |LVCMOS33 | Output|TXD_8_ 66 | I_O | 1 |M10 | * |LVCMOS33 | Input |clk 67 | I_O | 1 |M12 | * |LVCMOS33 | Output|TXD_7_ 68 |GNDIO1 | - | | | | | 69 | I_O | 1 |N2 | * |LVCMOS33 | Output|TXD_6_ 70 | I_O | 1 |N6 | * |LVCMOS33 | Output|TXD_5_ 71 | I_O | 1 |N10 | * |LVCMOS33 | Output|TXD_4_ 72 | I_O | 1 |N12 | * |LVCMOS33 | Output|TXD_3_ 73 | IN4 | 1 | | | | | 74 | TDO | - | | | | | 75 | VCC | - | | | | | 76 | GND | - | | | | | 77 | IN5 | 1 | | | | | 78 | I_O | 1 |O12 | * |LVCMOS33 | Output|TXD_2_ 79 | I_O | 1 |O10 | * |LVCMOS33 | Output|TXD_1_ 80 | I_O | 1 |O6 | * |LVCMOS33 | Output|TXD_0_ 81 | I_O | 1 |O2 | * |LVCMOS33 | Input |FAULT 82 |GNDIO1 | - | | | | | 83 |VCCIO1 | - | | | | | 84 | I_O | 1 |P12 | * |LVCMOS33 | Output|EN 85 | I_O | 1 |P10 | | | | 86 | I_O | 1 |P6 | * |LVCMOS33 | Output|WP_EEP 87 | I_O/OE| 1 |P2 | * |LVCMOS33 | Input |jTMS 88 |INCLK3 | 1 | | * |LVCMOS33 | Input |jTDI 89 |INCLK0 | 0 | | | | | 90 | VCC | - | | | | | 91 | I_O/OE| 0 |A2 | | | | 92 | I_O | 0 |A6 | | | | 93 | I_O | 0 |A10 | | | | 94 | I_O | 0 |A12 | | | | 95 |VCCIO0 | - | | | | | 96 |GNDIO0 | - | | | | | 97 | I_O | 0 |B2 | * |LVCMOS33 | Bidir |SDA 98 | I_O | 0 |B6 | * |LVCMOS33 |Tri-Out|SCL 99 | I_O | 0 |B10 | * |LVCMOS33 | Input |DIS_JTG 100 | I_O | 0 |B12 | * |LVCMOS33 | Input |reset_n ----------------------------------------------------------------------------------------- <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal ---------------------------------------------------------- 99 B I/O 1 -----F---------- Up DIS_JTG 81 O I/O 2 ---D-----------P Up FAULT 20 F I/O 2 -------HI------- Up NI_D_0_ 19 F I/O 3 --C---G----L---- Up NI_D_1_ 17 E I/O 2 -B-----H-------- Up NI_D_2_ 16 E I/O 2 ----E--H-------- Up NI_D_3_ 15 E I/O 2 A---E----------- Up NI_D_4_ 14 E I/O 3 A----------L-N-- Up NI_D_5_ 11 D I/O 2 --------I--L---- Up NI_D_6_ 10 D I/O 2 AB-------------- Up NI_D_7_ 9 D I/O 2 A-------I------- Up NI_D_8_ 8 D I/O 1 --C------------- Up NI_D_9_ 6 C I/O 9 ABC-E-GHI--L-N-- Up NI_STR 5 C I/O ---------------- Up Reserved_Pin_274 66 M I/O 14 ABCDE-GHI-KLMNOP Up clk 38 -- INCLK 1 -----F---------- Up jTCK 88 -- INCLK 4 A----F---J----O- Up jTDI 87 P I/O 1 -----F---------- Up jTMS 100 B I/O 7 -----F---JKLMNO- Up reset_n ---------------------------------------------------------- Output_Signal_List
I C P R P O Output N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal -------------------------------------------------------------------------------- 84 P 1 - 1 1 COM ---------------- Slow Up EN 49 J 4 - 1 1 COM 8 --C--F----KLMNOP Slow Up ENABLE 48 J 0 - 0 1 COM ---------------- Slow Up LCKREFN 53 K 0 - 0 1 COM ---------------- Slow Up LOOPEN 47 J 4 - 1 1 COM ---------------- Slow Up PRBSEN 98 B 0 - 0 1 COM * ---------------- Slow Up SCL 3 C 1 - 1 1 COM ---------------- Slow Up SD2ANL 44 I 0 - 0 1 COM ---------------- Slow Up TESTEN 80 O 17 5 7 2 DFF * R * 3 ----E--------NO- Fast Up TXD_0_ 61 L 18 4 18 4 DFF * S * 1 -----------L---- Fast Up TXD_10_ 60 L 16 5 12 3 DFF * S * 1 -----------L---- Fast Up TXD_11_ 59 L 12 5 9 2 DFF * R * 2 ----------KL---- Fast Up TXD_12_ 58 L 12 5 9 2 DFF * R * 2 ----------KL---- Fast Up TXD_13_ 56 K 16 4 13 3 DFF * R * 1 ----------K----- Fast Up TXD_14_ 55 K 14 4 7 2 DFF * R * 1 ----------K----- Fast Up TXD_15_ 79 O 14 4 9 2 DFF * R * 2 -------------NO- Fast Up TXD_1_ 78 O 18 4 17 4 DFF * R * 2 -------------NO- Fast Up TXD_2_ 72 N 16 5 10 2 DFF * R * 1 -------------N-- Fast Up TXD_3_ 71 N 14 5 9 3 DFF * S * 2 ------------MN-- Fast Up TXD_4_ 70 N 14 4 9 3 DFF * S * 3 --------I---MN-- Fast Up TXD_5_ 69 N 16 4 12 3 DFF * S * 3 --------I---MN-- Fast Up TXD_6_ 67 M 14 4 6 2 DFF * S * 1 ------------M--- Fast Up TXD_7_ 65 M 17 5 6 2 DFF * S * 3 ----E------LM--- Fast Up TXD_8_ 64 M 14 4 8 2 DFF * S * 2 -----------LM--- Fast Up TXD_9_ 54 K 9 4 4 2 DFF R 3 ----E-----K----P Fast Up TX_EN 50 J 0 - 0 1 COM ---------------- Slow Up TX_ER 86 P 4 - 1 1 COM ---------------- Slow Up WP_EEP 21 F 22 2 14 3 COM * ---------------- Slow Up jTDO -------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Bidir_Signal_List
I C P R P O Bidir N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------------------- 97 B 0 - 0 1 COM * 1 -----F---------- Slow Up SDA ------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Buried_Signal_List
I C P R P Node N L Mc R E U C I F Fanout Mc GLB P LL PTs S Type E S P E R P Signal ----------------------------------------------------------------------------------- 14 K 4 - 5 1 COM 1 ----E----------- ix449 5 L 2 - 2 1 COM 1 ----E----------- ix521 6 L 2 - 2 1 COM 1 ----E----------- ix523 6 M 2 - 2 1 COM 1 --------I------- ix793 15 N 4 - 5 1 COM 1 --------I------- ix865 11 I 4 - 5 1 COM 1 ----E----------- ix867 13 F 2 1 1 1 DFF * R 3 ---D-F---------P j2c__bitcnt_0_ 7 F 3 1 2 1 DFF * R 3 ---D-F---------P j2c__bitcnt_1_ 1 F 4 1 3 1 DFF * R 3 ---D-F---------P j2c__bitcnt_2_ 0 J 4 - 4 1 COM 8 A-C--F---J--MNOP j2c__ix107 9 J 4 - 5 2 COM 2 -----F---J------ j2c__ix45 7 J 4 - 5 2 COM 2 -----F---J------ j2c__ix59 8 J 4 - 5 2 COM 2 -----F---J------ j2c__ix71 13 J 4 - 4 1 COM 10 A-C--F---JKLMNOP j2c__ix77 15 J 4 - 4 1 COM 7 A-C--F---J--M-OP j2c__ix85 14 J 4 - 4 1 COM 9 A-C--F---J-LMNOP j2c__ix99 12 F 2 - 1 1 COM 3 -----F---J----O- j2c__nx0 0 P 11 - 8 2 COM 1 -----F---------- j2c__nx330 2 P 11 - 8 2 COM 1 -----F---------- j2c__nx365 3 D 19 - 15 3 COM 1 -----F---------- j2c__nx414 14 F 4 1 3 2 DFF * S * 4 ---D-F---J----O- j2c__reg_cmdreg_0_ 6 O 4 1 2 2 DFF * S * 1 -----F---------- j2c__reg_cmdreg_1_ 5 O 4 1 2 1 DFF * S * 1 -----F---------- j2c__reg_cmdreg_2_ 4 F 4 1 2 1 DFF * R 3 -----F---J----O- j2c__reg_cmdreg_3_ 4 J 6 1 2 1 DFF * R * 8 A-C--F----KLMNO- j2c__reg_creg0hm_0_ 3 J 6 1 2 1 DFF * R * 8 A-C--F----KLMNO- j2c__reg_creg0hm_1_ 2 J 6 1 2 1 DFF * R * 8 A-C--F----KLMNO- j2c__reg_creg0hm_2_ 1 J 6 1 2 1 DFF * S * 8 A-C--F----KLMNO- j2c__reg_creg0hm_3_ 15 F 8 1 6 2 DFF * R * 1 ---------J------ j2c__reg_creg1hm_0_ 11 O 8 1 5 2 DFF * R * 1 ---------J------ j2c__reg_creg1hm_1_ 14 O 6 1 2 1 DFF * S * 1 ---------J------ j2c__reg_creg1hm_2_ 7 O 8 1 5 1 DFF * S * 1 ---------J------ j2c__reg_creg1hm_3_ 4 O 6 1 2 1 DFF * R * 1 ---------J------ j2c__reg_creg1hm_4_ 3 O 6 1 2 2 DFF * R * 1 ---------J------ j2c__reg_creg1hm_5_ 3 F 6 1 3 2 DFF * S * 1 ---------J------ j2c__reg_creg1hm_6_ 6 F 5 1 2 1 DFF * S * 2 ------------M-O- j2c__reg_rstout_n_i 11 F 4 - 2 1 COM 1 -----F---------- j2c__reg_rstout_n_i_0 1 M 1 1 2 1 DFF R 1 ---------J------ j2c__reg_shreg_0_ 15 L 1 1 1 1 DFF R 2 ---------J--M--- j2c__reg_shreg_1_ 10 L 1 1 1 1 DFF R 2 ---------J-L---- j2c__reg_shreg_2_ 5 F 1 1 2 1 DFF R 2 ---------J-L---- j2c__reg_shreg_3_ 15 O 1 1 2 2 DFF R 2 -----F--------O- j2c__reg_shreg_4_ 0 O 1 1 2 1 DFF R 2 -----F--------O- j2c__reg_shreg_5_ 2 F 1 1 2 2 DFF R 1 --------------O- j2c__reg_shreg_6_ 12 A 1 - 1 1 DFF R 2 -----F--------O- j2c__reg_shreg_7_ 9 E 4 - 4 1 COM 1 ------G--------- ni_nires__nx1078 9 O 3 1 3 1 DFF R 2 --C---G--------- ni_nires__reg_clear_n_i 7 I 4 - 2 1 DFF R * 1 ----E----------- ni_nires__reg_data0neg_0_ 13 G 4 - 3 1 DFF R * 1 ------G--------- ni_nires__reg_data0neg_1_ 9 B 4 - 2 2 DFF R * 1 ----E----------- ni_nires__reg_data0neg_2_ 15 E 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data0neg_3_ 11 E 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data0neg_4_ 7 N 4 - 4 2 DFF R * 1 -B-------------- ni_nires__reg_data0neg_5_ 15 I 4 - 2 1 DFF R * 1 ----E----------- ni_nires__reg_data0neg_6_ 5 B 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data0neg_7_ 3 I 4 - 2 1 DFF R * 1 -------H-------- ni_nires__reg_data0neg_8_ 0 C 4 - 3 1 DFF R * 1 ------G--------- ni_nires__reg_data0neg_9_ 3 H 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data0pos_0_ 6 C 4 - 2 1 DFF R * 1 -------H-------- ni_nires__reg_data0pos_1_ 7 H 4 - 2 1 DFF R * 1 ----E----------- ni_nires__reg_data0pos_2_ 11 H 4 - 2 2 DFF R * 1 -B-------------- ni_nires__reg_data0pos_3_ 15 A 4 - 2 2 DFF R * 1 -------H-------- ni_nires__reg_data0pos_4_ 1 L 4 - 2 2 DFF R * 1 -------H-------- ni_nires__reg_data0pos_5_ 7 L 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data0pos_6_ 5 A 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data0pos_7_ 9 A 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data0pos_8_ 10 C 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data0pos_9_ 8 I 4 - 2 2 DFF R * 1 ----E----------- ni_nires__reg_data1neg_0_ 14 G 4 - 3 2 DFF R * 1 ------G--------- ni_nires__reg_data1neg_1_ 10 B 4 - 2 2 DFF R * 1 ----E----------- ni_nires__reg_data1neg_2_ 0 E 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data1neg_3_ 12 E 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data1neg_4_ 8 N 4 - 4 2 DFF R * 1 -B-------------- ni_nires__reg_data1neg_5_ 0 I 4 - 2 1 DFF R * 1 ----E----------- ni_nires__reg_data1neg_6_ 6 B 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data1neg_7_ 4 I 4 - 2 1 DFF R * 1 -------H-------- ni_nires__reg_data1neg_8_ 4 C 4 - 3 1 DFF R * 1 ------G--------- ni_nires__reg_data1neg_9_ 4 H 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data1pos_0_ 7 C 4 - 2 1 DFF R * 1 -------H-------- ni_nires__reg_data1pos_1_ 8 H 4 - 2 1 DFF R * 1 ----E----------- ni_nires__reg_data1pos_2_ 12 H 4 - 2 2 DFF R * 1 -B-------------- ni_nires__reg_data1pos_3_ 0 A 4 - 2 1 DFF R * 1 -------H-------- ni_nires__reg_data1pos_4_ 3 A 4 - 2 2 DFF R * 1 -------H-------- ni_nires__reg_data1pos_5_ 8 L 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data1pos_6_ 6 A 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data1pos_7_ 10 A 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data1pos_8_ 11 C 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data1pos_9_ 6 I 4 - 2 2 DFF R * 1 ----E----------- ni_nires__reg_data2neg_0_ 12 G 4 - 3 2 DFF R * 1 ------G--------- ni_nires__reg_data2neg_1_ 8 B 4 - 2 1 DFF R * 1 ----E----------- ni_nires__reg_data2neg_2_ 14 E 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data2neg_3_ 4 E 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data2neg_4_ 4 N 4 - 4 1 DFF R * 1 -B-------------- ni_nires__reg_data2neg_5_ 14 I 4 - 2 1 DFF R * 1 ----E----------- ni_nires__reg_data2neg_6_ 4 B 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data2neg_7_ 2 I 4 - 2 1 DFF R * 1 -------H-------- ni_nires__reg_data2neg_8_ 15 C 4 - 3 1 DFF R * 1 ------G--------- ni_nires__reg_data2neg_9_ 2 H 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data2pos_0_ 11 L 4 - 2 2 DFF R * 1 -------H-------- ni_nires__reg_data2pos_1_ 6 H 4 - 2 1 DFF R * 1 ----E----------- ni_nires__reg_data2pos_2_ 10 H 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data2pos_3_ 14 A 4 - 2 2 DFF R * 1 -------H-------- ni_nires__reg_data2pos_4_ 13 L 4 - 2 1 DFF R * 1 -------H-------- ni_nires__reg_data2pos_5_ 3 L 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data2pos_6_ 4 A 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data2pos_7_ 8 A 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data2pos_8_ 9 C 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data2pos_9_ 9 I 4 - 2 2 DFF R * 1 ----E----------- ni_nires__reg_data3neg_0_ 15 G 4 - 3 1 DFF R * 1 ------G--------- ni_nires__reg_data3neg_1_ 11 B 4 - 2 2 DFF R * 1 ----E----------- ni_nires__reg_data3neg_2_ 1 E 4 - 2 2 DFF R * 1 -B-------------- ni_nires__reg_data3neg_3_ 13 E 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data3neg_4_ 9 N 4 - 4 1 DFF R * 1 -B-------------- ni_nires__reg_data3neg_5_ 1 I 4 - 2 1 DFF R * 1 ----E----------- ni_nires__reg_data3neg_6_ 7 B 4 - 2 2 DFF R * 1 ------G--------- ni_nires__reg_data3neg_7_ 5 I 4 - 2 1 DFF R * 1 -------H-------- ni_nires__reg_data3neg_8_ 5 C 4 - 3 1 DFF R * 1 ------G--------- ni_nires__reg_data3neg_9_ 5 H 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data3pos_0_ 8 C 4 - 2 1 DFF R * 1 -------H-------- ni_nires__reg_data3pos_1_ 9 H 4 - 2 1 DFF R * 1 ----E----------- ni_nires__reg_data3pos_2_ 13 H 4 - 2 2 DFF R * 1 -B-------------- ni_nires__reg_data3pos_3_ 2 A 4 - 2 2 DFF R * 1 -------H-------- ni_nires__reg_data3pos_4_ 2 L 4 - 2 1 DFF R * 1 -------H-------- ni_nires__reg_data3pos_5_ 9 L 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data3pos_6_ 7 A 4 - 2 1 DFF R * 1 ------G--------- ni_nires__reg_data3pos_7_ 11 A 4 - 2 2 DFF R * 1 -B-------------- ni_nires__reg_data3pos_8_ 12 C 4 - 2 1 DFF R * 1 -B-------------- ni_nires__reg_data3pos_9_ 8 E 7 1 5 1 DFF R 2 A-------------O- ni_nires__reg_data_out_0_ 0 B 7 1 5 1 DFF R 2 --C---------M--- ni_nires__reg_data_out_10_ 0 H 7 1 5 1 DFF R 1 ------------M--- ni_nires__reg_data_out_11_ 5 E 7 1 5 1 DFF R 3 --C--------LM--- ni_nires__reg_data_out_12_ 15 B 7 1 5 2 DFF R 3 --C--------LM--- ni_nires__reg_data_out_13_ 15 H 7 1 5 1 DFF R 3 --C--------L-N-- ni_nires__reg_data_out_14_ 14 H 7 1 5 1 DFF R 1 -------------N-- ni_nires__reg_data_out_15_ 3 G 7 1 4 1 DFF R 2 -------------N-P ni_nires__reg_data_out_16_ 2 G 7 1 4 1 DFF R 3 --C-------K----P ni_nires__reg_data_out_17_ 14 B 7 1 5 2 DFF R 3 --C------JK----- ni_nires__reg_data_out_18_ 13 B 7 1 5 2 DFF R 1 ---------J------ ni_nires__reg_data_out_19_ 7 G 7 1 4 1 DFF R 1 --------------O- ni_nires__reg_data_out_1_ 7 E 7 1 5 1 DFF R 2 A-------------O- ni_nires__reg_data_out_2_ 3 B 7 1 5 1 DFF R 3 A------------NO- ni_nires__reg_data_out_3_ 6 G 7 1 4 1 DFF R 3 A------------NO- ni_nires__reg_data_out_4_ 1 B 7 1 5 1 DFF R 2 A------------N-- ni_nires__reg_data_out_5_ 6 E 7 1 5 1 DFF R 3 A-----------MN-- ni_nires__reg_data_out_6_ 5 G 7 1 4 1 DFF R 3 A-----------MN-- ni_nires__reg_data_out_7_ 1 H 7 1 5 1 DFF R 3 A-----------MN-- ni_nires__reg_data_out_8_ 4 G 7 1 4 1 DFF R 1 ------------M--- ni_nires__reg_data_out_9_ 3 C 3 1 2 2 DFF * R 4 A-C----H---L---- ni_nires__reg_gray_cnt_0_ 2 C 3 1 2 2 DFF * R 4 A-C----H---L---- ni_nires__reg_gray_cnt_1_ 11 G 3 1 3 2 DFF * R 6 -BC-E-G-I----N-- ni_nires__reg_gray_cntf_0_ 10 G 3 1 3 2 DFF * R 6 -BC-E-G-I----N-- ni_nires__reg_gray_cntf_1_ 1 G 3 1 2 2 DFF * R 1 ----E----------- ni_nires__reg_new_cnt_0_ 0 G 3 1 2 1 DFF * R 1 ----E----------- ni_nires__reg_new_cnt_1_ 9 G 4 1 3 2 DFF * R * 4 -B--E-GH-------- ni_nires__reg_old_cnt_0_ 8 G 4 1 3 1 DFF * R * 4 -B--E-GH-------- ni_nires__reg_old_cnt_1_ 2 E 5 1 5 1 DFF R 1 ----------K----- ni_nires__reg_valid 3 E 6 2 6 2 DFF R 1 --------I------- ni_reg_ce_prty_bit_neg 10 E 4 3 3 1 DFF R 1 ---D------------ ni_reg_ce_prty_bit_pos 1 C 22 5 15 4 DFF R 1 ----------K----- ni_reg_prty_bit_neg_r 1 A 24 5 16 4 DFF R 1 ------------M--- ni_reg_prty_bit_pos_r 2 M 4 - 2 1 COM 5 A-C--------LM-O- nx1039 1 N 5 - 4 1 COM 2 A------------N-- nx1052 3 M 3 - 2 1 COM 2 A------------N-- nx1059 11 M 6 - 4 1 COM 2 A------------N-- nx1076 0 M 6 - 4 1 COM 2 A-----------M--- nx1099 8 F 3 - 2 1 COM 1 --------I------- nx12 7 M 5 - 1 1 COM 2 --C---------M--- nx1255 8 M 7 - 1 1 COM 1 ------------M--- nx1263 14 M 5 - 4 1 COM 2 --C---------M--- nx1265 2 N 5 - 4 1 COM 2 --C--------L---- nx1309 7 P 6 - 4 1 COM 3 --C-------KL---- nx1325 6 N 3 - 2 1 COM 2 --C--------L---- nx1333 11 J 6 - 4 2 COM 2 --C-------K----- nx1341 8 K 4 - 2 1 COM 5 ----------KLMNO- nx148 10 F 3 - 2 1 COM 1 ---D------------ nx197 9 F 3 - 2 1 COM 1 --C------------- nx20 14 P 8 - 1 1 COM 1 ---------------P nx96 12 O 5 - 1 1 COM 2 A-------------O- nx972 15 M 7 - 1 1 COM 1 --------------O- nx988 13 O 5 - 4 1 COM 3 A-----------M-O- nx990 4 K 4 1 2 1 DFF * R * 2 ----------K----P reg_ID_0_0_ 2 K 5 1 3 1 DFF * R * 2 ----------K----P reg_ID_0_1_ 15 K 6 1 4 1 DFF * R * 2 ----------K----P reg_ID_0_2_ 6 K 7 1 5 1 DFF * R * 2 ----------K----P reg_ID_0_3_ 8 P 8 1 3 1 DFF * R * 2 ----------K----P reg_ID_0_4_ 9 K 8 1 2 1 TFF * R * 1 ---------------P reg_ID_0_5_ 3 P 9 1 2 1 TFF * R * 1 ---------------P reg_ID_0_6_ 1 P 10 1 2 1 TFF * R * 1 ---------------P reg_ID_0_7_ 9 M 2 - 1 1 COM 4 ---D----I-K----P reg_ID_0_7__0 10 P 5 2 3 1 DFF * R * 1 ---------------P reg_ID_1_0_ 5 P 6 2 4 1 DFF * R * 1 ---------------P reg_ID_1_1_ 4 P 7 2 5 1 DFF * R * 1 ---------------P reg_ID_1_2_ 9 P 8 2 3 1 DFF * R * 1 ---------------P reg_ID_1_3_ 13 P 8 2 2 1 TFF * R * 1 ---------------P reg_ID_1_4_ 12 P 9 2 2 1 TFF * R * 1 ---------------P reg_ID_1_5_ 11 P 10 2 2 1 TFF * R * 1 ---------------P reg_ID_1_6_ 14 D 4 1 2 1 DFF * R * 2 ---D----I------- reg_ID_2_0_ 12 D 5 1 3 1 DFF * R * 2 ---D----I------- reg_ID_2_1_ 8 D 6 1 4 1 DFF * R * 2 ---D----I------- reg_ID_2_2_ 2 D 7 1 5 1 DFF * R * 2 ---D----I------- reg_ID_2_3_ 10 D 8 1 3 1 DFF * R * 2 ---D----I------- reg_ID_2_4_ 6 D 8 1 2 1 TFF * R * 2 ---D----I------- reg_ID_2_5_ 13 I 9 1 4 1 TFF * R * 2 ---D----I------- reg_ID_2_6_ 10 I 8 - 2 1 COM 2 ---D----I------- reg_ID_2_6__0 1 D 4 1 2 2 DFF * R * 1 ---D------------ reg_ID_3_0_ 13 D 5 1 3 1 DFF * R * 1 ---D------------ reg_ID_3_1_ 9 D 6 1 4 1 DFF * R * 1 ---D------------ reg_ID_3_2_ 7 D 7 1 5 1 DFF * R * 1 ---D------------ reg_ID_3_3_ 11 D 8 1 3 1 DFF * R * 1 ---D------------ reg_ID_3_4_ 0 D 8 1 2 1 TFF * R * 1 ---D------------ reg_ID_3_5_ 15 D 9 1 2 1 TFF * R * 1 ---D------------ reg_ID_3_6_ 4 D 8 - 2 1 COM 1 ---D------------ reg_ID_3_6__0 3 N 2 1 2 2 DFF R 2 ----------K--N-- reg_ni_pattcount_0_ 3 K 3 1 3 1 DFF R 1 ----------K----- reg_ni_pattcount_1_ 0 K 4 1 4 1 DFF R 1 ----------K----- reg_ni_pattcount_2_ 13 K 5 1 5 1 DFF R 1 ----------K----- reg_ni_pattcount_3_ 1 K 6 1 3 1 DFF R 1 ----------K----- reg_ni_pattcount_4_ 5 M 4 - 1 1 COM 5 ----------KLMNO- testpatt -- I 1 1 0 PTOE ---------------- SCL.OE -- C 1 1 0 PTOE ---------------- SDA.OE -- D 1 1 0 PTOE ---------------- jTDO.OE ----------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used OBP = ORP bypass used PostFit_Equations
EN = ENABLE ; (1 pterm, 1 signal) ENABLE = !( j2c__ix77 & j2c__ix99 & j2c__ix85 & !j2c__ix107 ) ; (1 pterm, 4 signals) LCKREFN = 0 ; (0 pterm, 0 signal) LOOPEN = 0 ; (0 pterm, 0 signal) PRBSEN = j2c__ix77 & !j2c__ix99 & j2c__ix85 & !j2c__ix107 ; (1 pterm, 4 signals) SCL = 0 ; (0 pterm, 0 signal) SCL.OE = nx12 ; (1 pterm, 1 signal) SD2ANL = ENABLE ; (1 pterm, 1 signal) SDA = 0 ; (0 pterm, 0 signal) SDA.OE = nx20 ; (1 pterm, 1 signal) TESTEN = 0 ; (0 pterm, 0 signal) TXD_0_.D = !( !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & nx972 & nx988 & !testpatt & !j2c__ix107 # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & nx988 & !testpatt & !j2c__reg_creg0hm_0_.Q # TXD_0_.Q & nx988 & testpatt # nx972 & nx988 & !testpatt & !ni_nires__reg_data_out_0_.Q # !ENABLE & nx988 ) ; (5 pterms, 14 signals) TXD_0_.C = clk ; (1 pterm, 1 signal) TXD_0_.CE = nx148 ; (1 pterm, 1 signal) TXD_0_.AR = !reset_n ; (1 pterm, 1 signal) TXD_10_.D = ENABLE & !j2c__ix77 & !j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_14_.Q # ENABLE & !j2c__ix77 & !j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_14_.Q # ENABLE & j2c__reg_creg0hm_1_.Q & !testpatt & nx1039 & j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1039 & j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_12_.Q # ENABLE & !TXD_10_.Q & !TXD_9_.Q & !TXD_8_.Q & testpatt # ENABLE & j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_13_.Q # ENABLE & TXD_10_.Q & TXD_8_.Q & testpatt # ENABLE & TXD_10_.Q & TXD_9_.Q & testpatt # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & nx1039 & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & nx1039 & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & !nx1039 & ni_nires__reg_data_out_12_.Q # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1039 & ni_nires__reg_data_out_12_.Q ; (15 pterms, 15 signals) TXD_10_.C = clk ; (1 pterm, 1 signal) TXD_10_.CE = nx148 ; (1 pterm, 1 signal) TXD_10_.AP = !reset_n ; (1 pterm, 1 signal) TXD_11_.D.X1 = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !nx1309 # ENABLE & !j2c__ix77 & !j2c__ix99 & j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_14_.Q # ENABLE & !j2c__ix77 & !j2c__ix99 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_14_.Q # ENABLE & j2c__ix99 & j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__ix99 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__ix77 & j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__ix77 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_13_.Q # ENABLE & !TXD_10_.Q & !TXD_9_.Q & !TXD_8_.Q & testpatt ; (8 pterms, 12 signals) TXD_11_.D.X2 = ENABLE & TXD_11_.Q & testpatt ; (1 pterm, 3 signals) TXD_11_.C = clk ; (1 pterm, 1 signal) TXD_11_.CE = nx148 ; (1 pterm, 1 signal) TXD_11_.AP = !reset_n ; (1 pterm, 1 signal) TXD_12_.D = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & !nx1333 # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & j2c__reg_creg0hm_0_.Q & !nx1309 # ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1309 # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !nx1333 # ENABLE & !TXD_12_.Q & testpatt # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1309 ; (6 pterms, 9 signals) TXD_12_.C = clk ; (1 pterm, 1 signal) TXD_12_.CE = nx148 ; (1 pterm, 1 signal) TXD_12_.AR = !reset_n ; (1 pterm, 1 signal) TXD_13_.D = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !nx1325 # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !nx1325 # ENABLE & TXD_13_.Q & !TXD_12_.Q & testpatt # ENABLE & !TXD_13_.Q & TXD_12_.Q & testpatt # ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1333 # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1333 ; (6 pterms, 9 signals) TXD_13_.C = clk ; (1 pterm, 1 signal) TXD_13_.CE = nx148 ; (1 pterm, 1 signal) TXD_13_.AR = !reset_n ; (1 pterm, 1 signal) TXD_14_.D = ENABLE & !TXD_14_.Q & TXD_13_.Q & TXD_12_.Q & testpatt # ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & j2c__reg_creg0hm_0_.Q & !nx1325 # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_17_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_17_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_17_.Q # ENABLE & !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_18_.Q # ENABLE & !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_18_.Q # ENABLE & !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_18_.Q # ENABLE & TXD_14_.Q & !TXD_12_.Q & testpatt # ENABLE & TXD_14_.Q & !TXD_13_.Q & testpatt # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1325 ; (11 pterms, 13 signals) TXD_14_.C = clk ; (1 pterm, 1 signal) TXD_14_.CE = nx148 ; (1 pterm, 1 signal) TXD_14_.AR = !reset_n ; (1 pterm, 1 signal) TXD_15_.D.X1 = ENABLE & !j2c__reg_creg0hm_3_.Q & !testpatt & !nx1341 # ENABLE & !j2c__ix77 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_18_.Q # ENABLE & j2c__ix77 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_17_.Q # ENABLE & TXD_14_.Q & TXD_13_.Q & TXD_12_.Q & testpatt ; (4 pterms, 10 signals) TXD_15_.D.X2 = ENABLE & TXD_15_.Q & testpatt ; (1 pterm, 3 signals) TXD_15_.C = clk ; (1 pterm, 1 signal) TXD_15_.CE = nx148 ; (1 pterm, 1 signal) TXD_15_.AR = !reset_n ; (1 pterm, 1 signal) TXD_1_.D = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & nx1039 & ni_nires__reg_data_out_3_.Q # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !nx1039 & ni_nires__reg_data_out_2_.Q # ENABLE & TXD_1_.Q & !TXD_0_.Q & testpatt # ENABLE & !TXD_1_.Q & TXD_0_.Q & testpatt # ENABLE & j2c__reg_creg0hm_1_.Q & !nx990 & !testpatt # ENABLE & j2c__reg_creg0hm_2_.Q & !nx990 & !testpatt # ENABLE & j2c__reg_creg0hm_3_.Q & !nx990 & !testpatt ; (7 pterms, 11 signals) TXD_1_.C = clk ; (1 pterm, 1 signal) TXD_1_.CE = nx148 ; (1 pterm, 1 signal) TXD_1_.AR = !reset_n ; (1 pterm, 1 signal) TXD_2_.D = ENABLE & !j2c__ix77 & !j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_4_.Q # ENABLE & !j2c__ix77 & !j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_4_.Q # ENABLE & j2c__reg_creg0hm_1_.Q & !testpatt & nx1039 & j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1039 & j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_2_.Q # ENABLE & !TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & testpatt # ENABLE & j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_3_.Q # ENABLE & TXD_2_.Q & !TXD_0_.Q & testpatt # ENABLE & TXD_2_.Q & !TXD_1_.Q & testpatt # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & nx1039 & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & nx1039 & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & !nx1039 & ni_nires__reg_data_out_2_.Q # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1039 & ni_nires__reg_data_out_2_.Q ; (15 pterms, 15 signals) TXD_2_.C = clk ; (1 pterm, 1 signal) TXD_2_.CE = nx148 ; (1 pterm, 1 signal) TXD_2_.AR = !reset_n ; (1 pterm, 1 signal) TXD_3_.D.X1 = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !nx1052 # ENABLE & !j2c__ix77 & !j2c__ix99 & j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_4_.Q # ENABLE & !j2c__ix77 & !j2c__ix99 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_4_.Q # ENABLE & j2c__ix99 & j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__ix99 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__ix77 & j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__ix77 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_3_.Q # ENABLE & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & testpatt ; (8 pterms, 12 signals) TXD_3_.D.X2 = ENABLE & TXD_3_.Q & testpatt ; (1 pterm, 3 signals) TXD_3_.C = clk ; (1 pterm, 1 signal) TXD_3_.CE = nx148 ; (1 pterm, 1 signal) TXD_3_.AR = !reset_n ; (1 pterm, 1 signal) TXD_4_.D = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & nx1059 & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_6_.Q # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !nx1059 & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_5_.Q # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & nx1059 & ni_nires__reg_data_out_6_.Q # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & !nx1052 & j2c__reg_creg0hm_0_.Q # ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1052 # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !nx1059 & ni_nires__reg_data_out_5_.Q # ENABLE & !TXD_4_.Q & testpatt # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1052 ; (8 pterms, 11 signals) TXD_4_.C = clk ; (1 pterm, 1 signal) TXD_4_.CE = nx148 ; (1 pterm, 1 signal) TXD_4_.AP = !reset_n ; (1 pterm, 1 signal) TXD_5_.D = ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & nx1059 & ni_nires__reg_data_out_6_.Q # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !nx1076 # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !nx1076 # ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1059 & ni_nires__reg_data_out_5_.Q # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & nx1059 & ni_nires__reg_data_out_6_.Q # ENABLE & !TXD_5_.Q & !TXD_4_.Q & testpatt # ENABLE & TXD_5_.Q & TXD_4_.Q & testpatt # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1059 & ni_nires__reg_data_out_5_.Q ; (8 pterms, 11 signals) TXD_5_.C = clk ; (1 pterm, 1 signal) TXD_5_.CE = nx148 ; (1 pterm, 1 signal) TXD_5_.AP = !reset_n ; (1 pterm, 1 signal) TXD_6_.D = ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1076 & j2c__reg_creg0hm_0_.Q # ENABLE & !TXD_6_.Q & !TXD_5_.Q & !TXD_4_.Q & testpatt # ENABLE & !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_8_.Q # ENABLE & !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_8_.Q # ENABLE & !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_8_.Q # ENABLE & TXD_6_.Q & TXD_4_.Q & testpatt # ENABLE & TXD_6_.Q & TXD_5_.Q & testpatt # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_7_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_7_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_7_.Q # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1076 ; (11 pterms, 13 signals) TXD_6_.C = clk ; (1 pterm, 1 signal) TXD_6_.CE = nx148 ; (1 pterm, 1 signal) TXD_6_.AP = !reset_n ; (1 pterm, 1 signal) TXD_7_.D.X1 = ENABLE & !j2c__reg_creg0hm_3_.Q & !testpatt & !nx1099 # ENABLE & !j2c__ix77 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_8_.Q # ENABLE & j2c__ix77 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_7_.Q # ENABLE & !TXD_6_.Q & !TXD_5_.Q & !TXD_4_.Q & testpatt ; (4 pterms, 10 signals) TXD_7_.D.X2 = ENABLE & TXD_7_.Q & testpatt ; (1 pterm, 3 signals) TXD_7_.C = clk ; (1 pterm, 1 signal) TXD_7_.CE = nx148 ; (1 pterm, 1 signal) TXD_7_.AP = !reset_n ; (1 pterm, 1 signal) TXD_8_.D = !( !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !testpatt & !j2c__ix107 & nx1255 & nx1263 # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & nx1263 # TXD_8_.Q & testpatt & nx1263 # !testpatt & nx1255 & nx1263 & !ni_nires__reg_data_out_10_.Q # !ENABLE & nx1263 ) ; (5 pterms, 14 signals) TXD_8_.C = clk ; (1 pterm, 1 signal) TXD_8_.CE = nx148 ; (1 pterm, 1 signal) TXD_8_.AP = !reset_n ; (1 pterm, 1 signal) TXD_9_.D = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & nx1039 & ni_nires__reg_data_out_13_.Q # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !nx1039 & ni_nires__reg_data_out_12_.Q # ENABLE & !TXD_9_.Q & !TXD_8_.Q & testpatt # ENABLE & TXD_9_.Q & TXD_8_.Q & testpatt # ENABLE & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1265 # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & !nx1265 # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1265 ; (7 pterms, 11 signals) TXD_9_.C = clk ; (1 pterm, 1 signal) TXD_9_.CE = nx148 ; (1 pterm, 1 signal) TXD_9_.AP = !reset_n ; (1 pterm, 1 signal) TX_EN.D = !( testpatt & !reg_ni_pattcount_2_.Q & !reg_ni_pattcount_1_.Q & !reg_ni_pattcount_0_.Q & !reg_ni_pattcount_4_.Q & !reg_ni_pattcount_3_.Q # !testpatt & !ni_nires__reg_valid.Q # !ENABLE ) ; (3 pterms, 8 signals) TX_EN.C = clk ; (1 pterm, 1 signal) TX_ER = 0 ; (0 pterm, 0 signal) WP_EEP = !( j2c__ix77 & !j2c__ix99 & j2c__ix85 & j2c__ix107 ) ; (1 pterm, 4 signals) ix449.X1 = !TXD_14_.Q & !TXD_13_.Q & !ni_reg_prty_bit_neg_r.Q # !TXD_14_.Q & TXD_13_.Q & ni_reg_prty_bit_neg_r.Q # TXD_14_.Q & !TXD_13_.Q & ni_reg_prty_bit_neg_r.Q # TXD_14_.Q & TXD_13_.Q & !ni_reg_prty_bit_neg_r.Q ; (4 pterms, 3 signals) ix449.X2 = !TXD_15_.Q ; (1 pterm, 1 signal) ix521 = TXD_12_.Q & !TXD_11_.Q # !TXD_12_.Q & TXD_11_.Q ; (2 pterms, 2 signals) ix523 = TXD_10_.Q & !TXD_9_.Q # !TXD_10_.Q & TXD_9_.Q ; (2 pterms, 2 signals) ix793 = TXD_7_.Q & !ni_reg_prty_bit_pos_r.Q # !TXD_7_.Q & ni_reg_prty_bit_pos_r.Q ; (2 pterms, 2 signals) ix865.X1 = !TXD_3_.Q & !TXD_2_.Q & !TXD_1_.Q # !TXD_3_.Q & TXD_2_.Q & TXD_1_.Q # TXD_3_.Q & !TXD_2_.Q & TXD_1_.Q # TXD_3_.Q & TXD_2_.Q & !TXD_1_.Q ; (4 pterms, 3 signals) ix865.X2 = !TXD_4_.Q ; (1 pterm, 1 signal) ix867.X1 = !TXD_5_.Q & !ix793 & !ix865 # !TXD_5_.Q & ix793 & ix865 # TXD_5_.Q & !ix793 & ix865 # TXD_5_.Q & ix793 & !ix865 ; (4 pterms, 3 signals) ix867.X2 = !TXD_6_.Q ; (1 pterm, 1 signal) j2c__bitcnt_0_.D = !j2c__bitcnt_0_.Q ; (1 pterm, 1 signal) j2c__bitcnt_0_.C = !jTCK ; (1 pterm, 1 signal) j2c__bitcnt_0_.AR = !j2c__nx0 ; (1 pterm, 1 signal) j2c__bitcnt_1_.D = j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q # !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q ; (2 pterms, 2 signals) j2c__bitcnt_1_.C = !jTCK ; (1 pterm, 1 signal) j2c__bitcnt_1_.AR = !j2c__nx0 ; (1 pterm, 1 signal) j2c__bitcnt_2_.D = j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !j2c__bitcnt_0_.Q & j2c__bitcnt_2_.Q ; (3 pterms, 3 signals) j2c__bitcnt_2_.C = !jTCK ; (1 pterm, 1 signal) j2c__bitcnt_2_.AR = !j2c__nx0 ; (1 pterm, 1 signal) j2c__ix107 = !j2c__reg_creg1hm_2_.Q & j2c__ix59 & j2c__ix71 & !j2c__ix45 # j2c__reg_creg1hm_2_.Q & !j2c__ix71 # j2c__reg_creg1hm_2_.Q & !j2c__ix59 # j2c__reg_creg1hm_2_.Q & j2c__ix45 ; (4 pterms, 4 signals) j2c__ix45.X1 = !j2c__reg_creg1hm_5_.Q & !j2c__reg_creg1hm_4_.Q & !j2c__reg_creg1hm_3_.Q # !j2c__reg_creg1hm_5_.Q & j2c__reg_creg1hm_4_.Q & j2c__reg_creg1hm_3_.Q # j2c__reg_creg1hm_5_.Q & !j2c__reg_creg1hm_4_.Q & j2c__reg_creg1hm_3_.Q # j2c__reg_creg1hm_5_.Q & j2c__reg_creg1hm_4_.Q & !j2c__reg_creg1hm_3_.Q ; (4 pterms, 3 signals) j2c__ix45.X2 = !j2c__reg_creg1hm_6_.Q ; (1 pterm, 1 signal) j2c__ix59.X1 = !j2c__reg_creg1hm_6_.Q & !j2c__reg_creg1hm_5_.Q & !j2c__reg_creg1hm_1_.Q # !j2c__reg_creg1hm_6_.Q & j2c__reg_creg1hm_5_.Q & j2c__reg_creg1hm_1_.Q # j2c__reg_creg1hm_6_.Q & !j2c__reg_creg1hm_5_.Q & j2c__reg_creg1hm_1_.Q # j2c__reg_creg1hm_6_.Q & j2c__reg_creg1hm_5_.Q & !j2c__reg_creg1hm_1_.Q ; (4 pterms, 3 signals) j2c__ix59.X2 = !j2c__reg_creg1hm_2_.Q ; (1 pterm, 1 signal) j2c__ix71.X1 = !j2c__reg_creg1hm_6_.Q & !j2c__reg_creg1hm_4_.Q & !j2c__reg_creg1hm_0_.Q # !j2c__reg_creg1hm_6_.Q & j2c__reg_creg1hm_4_.Q & j2c__reg_creg1hm_0_.Q # j2c__reg_creg1hm_6_.Q & !j2c__reg_creg1hm_4_.Q & j2c__reg_creg1hm_0_.Q # j2c__reg_creg1hm_6_.Q & j2c__reg_creg1hm_4_.Q & !j2c__reg_creg1hm_0_.Q ; (4 pterms, 3 signals) j2c__ix71.X2 = !j2c__reg_creg1hm_2_.Q ; (1 pterm, 1 signal) j2c__ix77 = j2c__ix59 & j2c__ix71 & !j2c__reg_creg1hm_6_.Q & j2c__ix45 # !j2c__ix71 & j2c__reg_creg1hm_6_.Q # !j2c__ix59 & j2c__reg_creg1hm_6_.Q # j2c__reg_creg1hm_6_.Q & !j2c__ix45 ; (4 pterms, 4 signals) j2c__ix85 = !j2c__ix59 & j2c__ix71 & !j2c__reg_creg1hm_4_.Q & j2c__ix45 # !j2c__ix71 & j2c__reg_creg1hm_4_.Q # j2c__ix59 & j2c__reg_creg1hm_4_.Q # j2c__reg_creg1hm_4_.Q & !j2c__ix45 ; (4 pterms, 4 signals) j2c__ix99 = j2c__ix59 & !j2c__ix71 & !j2c__reg_creg1hm_5_.Q & j2c__ix45 # j2c__ix71 & j2c__reg_creg1hm_5_.Q # !j2c__ix59 & j2c__reg_creg1hm_5_.Q # j2c__reg_creg1hm_5_.Q & !j2c__ix45 ; (4 pterms, 4 signals) j2c__nx0 = !( !DIS_JTG & !jTMS ) ; (1 pterm, 2 signals) j2c__nx330 = reg_ID_1_0_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # reg_ID_1_1_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # reg_ID_1_2_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # reg_ID_1_3_.Q & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # reg_ID_1_4_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # reg_ID_1_5_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # reg_ID_1_6_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # FAULT & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q ; (8 pterms, 11 signals) j2c__nx365 = !reg_ID_0_4_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !reg_ID_0_5_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !reg_ID_0_6_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !reg_ID_0_7_.Q & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !reg_ID_0_0_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !reg_ID_0_1_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !reg_ID_0_2_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !reg_ID_0_3_.Q & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q ; (8 pterms, 11 signals) j2c__nx414 = j2c__reg_cmdreg_0_.Q & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & reg_ID_3_3_.Q # j2c__reg_cmdreg_0_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & reg_ID_3_5_.Q & j2c__bitcnt_2_.Q # j2c__reg_cmdreg_0_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & reg_ID_3_6_.Q & j2c__bitcnt_2_.Q # j2c__reg_cmdreg_0_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & reg_ID_3_1_.Q # j2c__reg_cmdreg_0_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & reg_ID_3_2_.Q # j2c__reg_cmdreg_0_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q & reg_ID_3_4_.Q # !j2c__reg_cmdreg_0_.Q & reg_ID_2_3_.Q & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !j2c__reg_cmdreg_0_.Q & reg_ID_2_5_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !j2c__reg_cmdreg_0_.Q & reg_ID_2_6_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !j2c__reg_cmdreg_0_.Q & j2c__bitcnt_0_.Q & reg_ID_2_1_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !j2c__reg_cmdreg_0_.Q & reg_ID_2_2_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !j2c__reg_cmdreg_0_.Q & reg_ID_2_4_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !j2c__reg_cmdreg_0_.Q & !j2c__bitcnt_0_.Q & reg_ID_2_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # FAULT & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # j2c__reg_cmdreg_0_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & reg_ID_3_0_.Q ; (15 pterms, 19 signals) j2c__reg_cmdreg_0_.D = j2c__reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c__reg_cmdreg_0_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_cmdreg_0_.CE = jTDI ; (1 pterm, 1 signal) j2c__reg_cmdreg_0_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_cmdreg_1_.D = j2c__reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c__reg_cmdreg_1_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_cmdreg_1_.CE = jTDI ; (1 pterm, 1 signal) j2c__reg_cmdreg_1_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_cmdreg_2_.D = j2c__reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c__reg_cmdreg_2_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_cmdreg_2_.CE = jTDI ; (1 pterm, 1 signal) j2c__reg_cmdreg_2_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_cmdreg_3_.D = jTDI & j2c__reg_shreg_7_.Q ; (1 pterm, 2 signals) j2c__reg_cmdreg_3_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_cmdreg_3_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg0hm_0_.D = j2c__reg_shreg_0_.Q ; (1 pterm, 1 signal) j2c__reg_creg0hm_0_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg0hm_0_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg0hm_0_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg0hm_1_.D = j2c__reg_shreg_1_.Q ; (1 pterm, 1 signal) j2c__reg_creg0hm_1_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg0hm_1_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg0hm_1_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg0hm_2_.D = j2c__reg_shreg_2_.Q ; (1 pterm, 1 signal) j2c__reg_creg0hm_2_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg0hm_2_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg0hm_2_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg0hm_3_.D = j2c__reg_shreg_3_.Q ; (1 pterm, 1 signal) j2c__reg_creg0hm_3_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg0hm_3_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg0hm_3_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_0_.D = j2c__reg_shreg_4_.Q & !j2c__reg_shreg_5_.Q & !j2c__reg_shreg_7_.Q # !j2c__reg_shreg_4_.Q & j2c__reg_shreg_5_.Q & !j2c__reg_shreg_7_.Q # !j2c__reg_shreg_4_.Q & !j2c__reg_shreg_5_.Q & j2c__reg_shreg_7_.Q # j2c__reg_shreg_4_.Q & j2c__reg_shreg_5_.Q & j2c__reg_shreg_7_.Q ; (4 pterms, 3 signals) j2c__reg_creg1hm_0_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_0_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_0_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_1_.D = j2c__reg_shreg_4_.Q & !j2c__reg_shreg_6_.Q & !j2c__reg_shreg_7_.Q # !j2c__reg_shreg_4_.Q & j2c__reg_shreg_6_.Q & !j2c__reg_shreg_7_.Q # !j2c__reg_shreg_4_.Q & !j2c__reg_shreg_6_.Q & j2c__reg_shreg_7_.Q # j2c__reg_shreg_4_.Q & j2c__reg_shreg_6_.Q & j2c__reg_shreg_7_.Q ; (4 pterms, 3 signals) j2c__reg_creg1hm_1_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_1_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_1_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_2_.D = j2c__reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c__reg_creg1hm_2_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_2_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_2_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_3_.D = j2c__reg_shreg_5_.Q & !j2c__reg_shreg_6_.Q & !j2c__reg_shreg_7_.Q # !j2c__reg_shreg_5_.Q & j2c__reg_shreg_6_.Q & !j2c__reg_shreg_7_.Q # !j2c__reg_shreg_5_.Q & !j2c__reg_shreg_6_.Q & j2c__reg_shreg_7_.Q # j2c__reg_shreg_5_.Q & j2c__reg_shreg_6_.Q & j2c__reg_shreg_7_.Q ; (4 pterms, 3 signals) j2c__reg_creg1hm_3_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_3_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_3_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_4_.D = j2c__reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c__reg_creg1hm_4_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_4_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_4_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_5_.D = j2c__reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c__reg_creg1hm_5_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_5_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_5_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_6_.D = j2c__reg_shreg_7_.Q ; (1 pterm, 1 signal) j2c__reg_creg1hm_6_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_6_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_6_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_rstout_n_i.D = j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q ; (1 pterm, 3 signals) j2c__reg_rstout_n_i.C = !jTCK ; (1 pterm, 1 signal) j2c__reg_rstout_n_i.CE = j2c__reg_rstout_n_i_0 ; (1 pterm, 1 signal) j2c__reg_rstout_n_i.AP = !j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_rstout_n_i_0 = j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # j2c__reg_cmdreg_3_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q ; (2 pterms, 4 signals) j2c__reg_shreg_0_.D = j2c__reg_shreg_1_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_0_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_1_.D = j2c__reg_shreg_2_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_1_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_2_.D = j2c__reg_shreg_3_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_2_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_3_.D = j2c__reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_3_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_4_.D = j2c__reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_4_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_5_.D = j2c__reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_5_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_6_.D = j2c__reg_shreg_7_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_6_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_7_.D = jTDI ; (1 pterm, 1 signal) j2c__reg_shreg_7_.C = jTCK ; (1 pterm, 1 signal) jTDO.X1 = !DIS_JTG & !j2c__reg_cmdreg_0_.Q & !j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q & !j2c__nx365 # !DIS_JTG & j2c__reg_cmdreg_0_.Q & !j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q & j2c__nx330 # !DIS_JTG & !j2c__reg_cmdreg_2_.Q & j2c__reg_cmdreg_1_.Q & j2c__nx414 # !DIS_JTG & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q & j2c__reg_creg0hm_0_.Q # !DIS_JTG & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q & j2c__ix107 # !DIS_JTG & j2c__reg_creg0hm_2_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q # !DIS_JTG & j2c__ix99 & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q # !DIS_JTG & j2c__reg_creg0hm_1_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q # !DIS_JTG & j2c__ix85 & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q # !DIS_JTG & j2c__reg_creg0hm_3_.Q & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q # !DIS_JTG & j2c__ix77 & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q # !DIS_JTG & !j2c__ix59 & !j2c__ix71 & !j2c__ix45 & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & j2c__reg_cmdreg_1_.Q # DIS_JTG & SDA.PIN ; (13 pterms, 22 signals) jTDO.X2 = !DIS_JTG & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__reg_cmdreg_2_.Q & j2c__reg_cmdreg_1_.Q ; (1 pterm, 5 signals) jTDO.OE = nx197 ; (1 pterm, 1 signal) ni_nires__nx1078 = ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_new_cnt_1_.Q # !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_new_cnt_1_.Q # ni_nires__reg_old_cnt_0_.Q & !ni_nires__reg_new_cnt_0_.Q # !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_new_cnt_0_.Q ; (4 pterms, 4 signals) ni_nires__reg_clear_n_i.D = reset_n & j2c__reg_rstout_n_i.Q ; (1 pterm, 2 signals) ni_nires__reg_clear_n_i.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data0neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_0_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_1_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_2_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_3_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_4_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_5_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_6_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_7_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_8_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_9_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_0_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_1_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_2_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_3_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_4_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_5_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_6_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_7_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_8_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_9_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_0_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_1_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_2_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_3_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_4_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_5_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_6_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_7_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_8_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_9_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_0_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_1_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_2_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_3_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_4_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_5_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_6_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_7_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_8_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_9_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_0_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_1_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_2_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_3_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_4_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_5_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_6_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_7_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_8_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_9_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_0_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_1_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_2_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_3_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_4_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_5_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_6_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_7_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_8_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_9_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_0_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_1_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_2_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_3_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_4_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_5_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_6_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_7_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_8_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_9_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_0_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_1_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_2_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_3_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_4_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_5_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_6_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_7_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_8_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_9_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data_out_0_.D = !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data0neg_0_.Q # ni_nires__reg_data2neg_0_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data1neg_0_.Q # ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data3neg_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_0_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_10_.D = ni_nires__reg_data0pos_0_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_0_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_0_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_0_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_10_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_11_.D = ni_nires__reg_data0pos_1_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_1_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_1_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_1_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_11_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_12_.D = ni_nires__reg_data0pos_2_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_2_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_2_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_2_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_12_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_13_.D = ni_nires__reg_data0pos_3_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_3_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_3_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_3_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_13_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_14_.D = ni_nires__reg_data0pos_4_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_4_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_4_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_4_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_14_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_15_.D = ni_nires__reg_data0pos_5_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_5_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_5_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_5_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_15_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_16_.D = ni_nires__reg_data0pos_6_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_6_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_6_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_6_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_16_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_17_.D = ni_nires__reg_data0pos_7_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_7_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_7_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_7_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_17_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_18_.D = ni_nires__reg_data0pos_8_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_8_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_8_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_8_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_18_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_19_.D = ni_nires__reg_data0pos_9_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_9_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_9_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_9_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_19_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_1_.D = !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data0neg_1_.Q # ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data2neg_1_.Q # !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data1neg_1_.Q # ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data3neg_1_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_1_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_2_.D = !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data0neg_2_.Q # ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data2neg_2_.Q # !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data1neg_2_.Q # ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data3neg_2_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_2_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_3_.D = !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data0neg_3_.Q # ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data2neg_3_.Q # !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data1neg_3_.Q # ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data3neg_3_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_3_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_4_.D = ni_nires__reg_data0neg_4_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3neg_4_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1neg_4_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2neg_4_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_4_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_5_.D = ni_nires__reg_data0neg_5_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3neg_5_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1neg_5_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2neg_5_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_5_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_6_.D = ni_nires__reg_data0neg_6_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3neg_6_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1neg_6_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2neg_6_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_6_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_7_.D = ni_nires__reg_data0neg_7_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3neg_7_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1neg_7_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2neg_7_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_7_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_8_.D = ni_nires__reg_data0neg_8_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3neg_8_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1neg_8_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2neg_8_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_8_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_9_.D = ni_nires__reg_data0neg_9_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3neg_9_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1neg_9_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2neg_9_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_9_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_gray_cnt_0_.D = !ni_nires__reg_gray_cnt_1_.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cnt_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_gray_cnt_0_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cnt_1_.D = ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cnt_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_gray_cnt_1_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cntf_0_.D = !ni_nires__reg_gray_cntf_1_.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cntf_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_gray_cntf_0_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cntf_1_.D = ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cntf_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_gray_cntf_1_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_new_cnt_0_.D = ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 1 signal) ni_nires__reg_new_cnt_0_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_new_cnt_0_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_new_cnt_1_.D = ni_nires__reg_gray_cntf_1_.Q ; (1 pterm, 1 signal) ni_nires__reg_new_cnt_1_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_new_cnt_1_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_0_.D = !ni_nires__reg_old_cnt_1_.Q ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_0_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_0_.CE = ni_nires__nx1078 ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_0_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_1_.D = ni_nires__reg_old_cnt_0_.Q ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_1_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_1_.CE = ni_nires__nx1078 ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_1_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_valid.D = ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_new_cnt_1_.Q # !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_new_cnt_1_.Q # ni_nires__reg_old_cnt_0_.Q & !ni_nires__reg_new_cnt_0_.Q # !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_new_cnt_0_.Q ; (4 pterms, 4 signals) ni_nires__reg_valid.C = clk ; (1 pterm, 1 signal) ni_reg_ce_prty_bit_neg.D.X1 = TX_EN.Q & !ix449 & !ix521 & !ix523 # TX_EN.Q & !ix449 & ix521 & ix523 # TX_EN.Q & ix449 & !ix521 & ix523 # TX_EN.Q & ix449 & ix521 & !ix523 ; (4 pterms, 4 signals) ni_reg_ce_prty_bit_neg.D.X2 = TX_EN.Q & !TXD_8_.Q ; (1 pterm, 2 signals) ni_reg_ce_prty_bit_neg.C = clk ; (1 pterm, 1 signal) ni_reg_ce_prty_bit_pos.D = TX_EN.Q & TXD_0_.Q & !ix867 # TX_EN.Q & !TXD_0_.Q & ix867 ; (2 pterms, 3 signals) ni_reg_ce_prty_bit_pos.C = clk ; (1 pterm, 1 signal) ni_reg_prty_bit_neg_r.D = !( !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !j2c__ix107 & !j2c__reg_creg0hm_0_.Q & nx1255 # !j2c__ix77 & !j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_14_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !j2c__reg_creg0hm_0_.Q & nx1255 & !ni_nires__reg_data_out_10_.Q # j2c__ix77 & !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_17_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !nx1039 & !j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_12_.Q # !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_18_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & nx1039 & !j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_13_.Q # j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_13_.Q # j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_13_.Q # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !j2c__reg_creg0hm_0_.Q & nx1309 # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & nx1333 # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !j2c__reg_creg0hm_0_.Q & nx1325 # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & nx1265 # j2c__reg_creg0hm_3_.Q & nx1341 ) ; (14 pterms, 21 signals) ni_reg_prty_bit_neg_r.C = clk ; (1 pterm, 1 signal) ni_reg_prty_bit_pos_r.D = !( !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & nx972 & !j2c__ix107 & !j2c__reg_creg0hm_0_.Q # !j2c__ix77 & !j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_4_.Q # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !nx1059 & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_5_.Q # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & nx1059 & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_6_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !nx1039 & !j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_2_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & nx1039 & !j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_3_.Q # j2c__ix77 & !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_7_.Q # !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_8_.Q # j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_3_.Q # j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_3_.Q # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & nx1052 & !j2c__reg_creg0hm_0_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & nx972 & !j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_0_.Q # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & nx1076 & !j2c__reg_creg0hm_0_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & nx990 & j2c__reg_creg0hm_0_.Q # j2c__reg_creg0hm_3_.Q & nx1099 ) ; (15 pterms, 23 signals) ni_reg_prty_bit_pos_r.C = clk ; (1 pterm, 1 signal) nx1039 = !j2c__ix77 & !j2c__ix99 & !j2c__ix85 # !j2c__ix77 & !j2c__ix99 & !j2c__ix107 ; (2 pterms, 4 signals) nx1052 = nx1059 & !j2c__ix107 & !ni_nires__reg_data_out_5_.Q # !j2c__ix99 & nx1059 & !ni_nires__reg_data_out_5_.Q # j2c__ix99 & j2c__ix107 & !ni_nires__reg_data_out_4_.Q # !nx1059 & !ni_nires__reg_data_out_4_.Q ; (4 pterms, 5 signals) nx1059 = !j2c__ix77 & !j2c__ix99 # !j2c__ix77 & !j2c__ix85 ; (2 pterms, 3 signals) nx1076.X1 = j2c__ix77 & !ni_nires__reg_data_out_6_.Q # !j2c__ix77 & j2c__ix99 & j2c__ix85 & j2c__ix107 & !ni_nires__reg_data_out_7_.Q & ni_nires__reg_data_out_6_.Q # !j2c__ix77 & j2c__ix99 & j2c__ix85 & j2c__ix107 & ni_nires__reg_data_out_7_.Q & !ni_nires__reg_data_out_6_.Q ; (3 pterms, 6 signals) nx1076.X2 = !j2c__ix77 & !ni_nires__reg_data_out_7_.Q ; (1 pterm, 2 signals) nx1099.X1 = !j2c__ix77 & !ni_nires__reg_data_out_9_.Q # j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__ix107 & ni_nires__reg_data_out_9_.Q & !ni_nires__reg_data_out_8_.Q # j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__ix107 & !ni_nires__reg_data_out_9_.Q & ni_nires__reg_data_out_8_.Q ; (3 pterms, 6 signals) nx1099.X2 = j2c__ix77 & !ni_nires__reg_data_out_8_.Q ; (1 pterm, 2 signals) nx12 = DIS_JTG & !jTCK # !ENABLE ; (2 pterms, 3 signals) nx1255 = !( !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__ix107 & ni_nires__reg_data_out_11_.Q ) ; (1 pterm, 5 signals) nx1263 = !( ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & !nx1265 ) ; (1 pterm, 7 signals) nx1265 = !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !ni_nires__reg_data_out_12_.Q # j2c__ix85 & !ni_nires__reg_data_out_11_.Q # j2c__ix99 & !ni_nires__reg_data_out_11_.Q # j2c__ix77 & !ni_nires__reg_data_out_11_.Q ; (4 pterms, 5 signals) nx1309 = nx1059 & !j2c__ix107 & !ni_nires__reg_data_out_15_.Q # !j2c__ix99 & nx1059 & !ni_nires__reg_data_out_15_.Q # j2c__ix99 & j2c__ix107 & !ni_nires__reg_data_out_14_.Q # !nx1059 & !ni_nires__reg_data_out_14_.Q ; (4 pterms, 5 signals) nx1325.X1 = j2c__ix77 & !ni_nires__reg_data_out_16_.Q # !j2c__ix77 & j2c__ix99 & j2c__ix85 & j2c__ix107 & !ni_nires__reg_data_out_17_.Q & ni_nires__reg_data_out_16_.Q # !j2c__ix77 & j2c__ix99 & j2c__ix85 & j2c__ix107 & ni_nires__reg_data_out_17_.Q & !ni_nires__reg_data_out_16_.Q ; (3 pterms, 6 signals) nx1325.X2 = !j2c__ix77 & !ni_nires__reg_data_out_17_.Q ; (1 pterm, 2 signals) nx1333 = nx1059 & !ni_nires__reg_data_out_16_.Q # !nx1059 & !ni_nires__reg_data_out_15_.Q ; (2 pterms, 3 signals) nx1341.X1 = !j2c__ix77 & !ni_nires__reg_data_out_19_.Q # j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__ix107 & ni_nires__reg_data_out_19_.Q & !ni_nires__reg_data_out_18_.Q # j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__ix107 & !ni_nires__reg_data_out_19_.Q & ni_nires__reg_data_out_18_.Q ; (3 pterms, 6 signals) nx1341.X2 = j2c__ix77 & !ni_nires__reg_data_out_18_.Q ; (1 pterm, 2 signals) nx148 = !( ENABLE & !TX_EN.Q & testpatt # ENABLE & !testpatt & !ni_nires__reg_valid.Q ) ; (2 pterms, 4 signals) nx197 = DIS_JTG # jTCK & j2c__nx0 ; (2 pterms, 3 signals) nx20 = DIS_JTG & !jTMS # !ENABLE ; (2 pterms, 3 signals) nx96 = reg_ID_0_7_.Q & reg_ID_0_6_.Q & reg_ID_0_5_.Q & reg_ID_0_4_.Q & reg_ID_0_3_.Q & reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q ; (1 pterm, 8 signals) nx972 = !( !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__ix107 & ni_nires__reg_data_out_1_.Q ) ; (1 pterm, 5 signals) nx988 = !( ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !nx990 & !testpatt & !j2c__reg_creg0hm_0_.Q ) ; (1 pterm, 7 signals) nx990 = !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !ni_nires__reg_data_out_2_.Q # j2c__ix85 & !ni_nires__reg_data_out_1_.Q # j2c__ix99 & !ni_nires__reg_data_out_1_.Q # j2c__ix77 & !ni_nires__reg_data_out_1_.Q ; (4 pterms, 5 signals) reg_ID_0_0_.D = !reg_ID_0_0_.Q ; (1 pterm, 1 signal) reg_ID_0_0_.C = clk ; (1 pterm, 1 signal) reg_ID_0_0_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_0_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_1_.D = reg_ID_0_1_.Q & !reg_ID_0_0_.Q # !reg_ID_0_1_.Q & reg_ID_0_0_.Q ; (2 pterms, 2 signals) reg_ID_0_1_.C = clk ; (1 pterm, 1 signal) reg_ID_0_1_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_1_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_2_.D = !reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q # reg_ID_0_2_.Q & !reg_ID_0_1_.Q # reg_ID_0_2_.Q & !reg_ID_0_0_.Q ; (3 pterms, 3 signals) reg_ID_0_2_.C = clk ; (1 pterm, 1 signal) reg_ID_0_2_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_2_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_3_.D = !reg_ID_0_3_.Q & reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q # reg_ID_0_3_.Q & !reg_ID_0_1_.Q # reg_ID_0_3_.Q & !reg_ID_0_2_.Q # reg_ID_0_3_.Q & !reg_ID_0_0_.Q ; (4 pterms, 4 signals) reg_ID_0_3_.C = clk ; (1 pterm, 1 signal) reg_ID_0_3_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_3_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_4_.D.X1 = reg_ID_0_4_.Q ; (1 pterm, 1 signal) reg_ID_0_4_.D.X2 = reg_ID_0_3_.Q & reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q ; (1 pterm, 4 signals) reg_ID_0_4_.C = clk ; (1 pterm, 1 signal) reg_ID_0_4_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_4_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_5_.T = reg_ID_0_4_.Q & reg_ID_0_3_.Q & reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q ; (1 pterm, 5 signals) reg_ID_0_5_.C = clk ; (1 pterm, 1 signal) reg_ID_0_5_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_5_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_6_.T = reg_ID_0_5_.Q & reg_ID_0_4_.Q & reg_ID_0_3_.Q & reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q ; (1 pterm, 6 signals) reg_ID_0_6_.C = clk ; (1 pterm, 1 signal) reg_ID_0_6_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_6_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_7_.T = reg_ID_0_6_.Q & reg_ID_0_5_.Q & reg_ID_0_4_.Q & reg_ID_0_3_.Q & reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q ; (1 pterm, 7 signals) reg_ID_0_7_.C = clk ; (1 pterm, 1 signal) reg_ID_0_7_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_7_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_7__0 = !( reset_n & j2c__reg_rstout_n_i.Q ) ; (1 pterm, 2 signals) reg_ID_1_0_.D = reg_ID_1_0_.Q & !nx96 # !reg_ID_1_0_.Q & nx96 ; (2 pterms, 2 signals) reg_ID_1_0_.C = clk ; (1 pterm, 1 signal) reg_ID_1_0_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_0_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_1_1_.D = !reg_ID_1_1_.Q & reg_ID_1_0_.Q & nx96 # reg_ID_1_1_.Q & !reg_ID_1_0_.Q # reg_ID_1_1_.Q & !nx96 ; (3 pterms, 3 signals) reg_ID_1_1_.C = clk ; (1 pterm, 1 signal) reg_ID_1_1_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_1_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_1_2_.D = !reg_ID_1_2_.Q & reg_ID_1_1_.Q & reg_ID_1_0_.Q & nx96 # reg_ID_1_2_.Q & !reg_ID_1_0_.Q # reg_ID_1_2_.Q & !reg_ID_1_1_.Q # reg_ID_1_2_.Q & !nx96 ; (4 pterms, 4 signals) reg_ID_1_2_.C = clk ; (1 pterm, 1 signal) reg_ID_1_2_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_2_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_1_3_.D.X1 = reg_ID_1_3_.Q ; (1 pterm, 1 signal) reg_ID_1_3_.D.X2 = reg_ID_1_2_.Q & reg_ID_1_1_.Q & reg_ID_1_0_.Q & nx96 ; (1 pterm, 4 signals) reg_ID_1_3_.C = clk ; (1 pterm, 1 signal) reg_ID_1_3_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_3_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_1_4_.T = reg_ID_1_3_.Q & reg_ID_1_2_.Q & reg_ID_1_1_.Q & reg_ID_1_0_.Q & nx96 ; (1 pterm, 5 signals) reg_ID_1_4_.C = clk ; (1 pterm, 1 signal) reg_ID_1_4_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_4_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_1_5_.T = reg_ID_1_4_.Q & reg_ID_1_3_.Q & reg_ID_1_2_.Q & reg_ID_1_1_.Q & reg_ID_1_0_.Q & nx96 ; (1 pterm, 6 signals) reg_ID_1_5_.C = clk ; (1 pterm, 1 signal) reg_ID_1_5_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_5_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_1_6_.T = reg_ID_1_5_.Q & reg_ID_1_4_.Q & reg_ID_1_3_.Q & reg_ID_1_2_.Q & reg_ID_1_1_.Q & reg_ID_1_0_.Q & nx96 ; (1 pterm, 7 signals) reg_ID_1_6_.C = clk ; (1 pterm, 1 signal) reg_ID_1_6_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_6_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_0_.D = !reg_ID_2_0_.Q ; (1 pterm, 1 signal) reg_ID_2_0_.C = clk ; (1 pterm, 1 signal) reg_ID_2_0_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_0_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_1_.D = reg_ID_2_1_.Q & !reg_ID_2_0_.Q # !reg_ID_2_1_.Q & reg_ID_2_0_.Q ; (2 pterms, 2 signals) reg_ID_2_1_.C = clk ; (1 pterm, 1 signal) reg_ID_2_1_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_1_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_2_.D = !reg_ID_2_2_.Q & reg_ID_2_1_.Q & reg_ID_2_0_.Q # reg_ID_2_2_.Q & !reg_ID_2_1_.Q # reg_ID_2_2_.Q & !reg_ID_2_0_.Q ; (3 pterms, 3 signals) reg_ID_2_2_.C = clk ; (1 pterm, 1 signal) reg_ID_2_2_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_2_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_3_.D = !reg_ID_2_3_.Q & reg_ID_2_2_.Q & reg_ID_2_1_.Q & reg_ID_2_0_.Q # reg_ID_2_3_.Q & !reg_ID_2_1_.Q # reg_ID_2_3_.Q & !reg_ID_2_2_.Q # reg_ID_2_3_.Q & !reg_ID_2_0_.Q ; (4 pterms, 4 signals) reg_ID_2_3_.C = clk ; (1 pterm, 1 signal) reg_ID_2_3_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_3_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_4_.D.X1 = reg_ID_2_4_.Q ; (1 pterm, 1 signal) reg_ID_2_4_.D.X2 = reg_ID_2_3_.Q & reg_ID_2_2_.Q & reg_ID_2_1_.Q & reg_ID_2_0_.Q ; (1 pterm, 4 signals) reg_ID_2_4_.C = clk ; (1 pterm, 1 signal) reg_ID_2_4_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_4_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_5_.T = reg_ID_2_4_.Q & reg_ID_2_3_.Q & reg_ID_2_2_.Q & reg_ID_2_1_.Q & reg_ID_2_0_.Q ; (1 pterm, 5 signals) reg_ID_2_5_.C = clk ; (1 pterm, 1 signal) reg_ID_2_5_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_5_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_6_.T = reg_ID_2_5_.Q & reg_ID_2_4_.Q & reg_ID_2_3_.Q & reg_ID_2_2_.Q & reg_ID_2_1_.Q & reg_ID_2_0_.Q ; (1 pterm, 6 signals) reg_ID_2_6_.C = clk ; (1 pterm, 1 signal) reg_ID_2_6_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_6_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_6__0 = !ni_reg_ce_prty_bit_neg.Q # reg_ID_2_6_.Q & reg_ID_2_5_.Q & reg_ID_2_4_.Q & reg_ID_2_3_.Q & reg_ID_2_2_.Q & reg_ID_2_1_.Q & reg_ID_2_0_.Q ; (2 pterms, 8 signals) reg_ID_3_0_.D = !reg_ID_3_0_.Q ; (1 pterm, 1 signal) reg_ID_3_0_.C = clk ; (1 pterm, 1 signal) reg_ID_3_0_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_0_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_1_.D = reg_ID_3_1_.Q & !reg_ID_3_0_.Q # !reg_ID_3_1_.Q & reg_ID_3_0_.Q ; (2 pterms, 2 signals) reg_ID_3_1_.C = clk ; (1 pterm, 1 signal) reg_ID_3_1_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_1_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_2_.D = !reg_ID_3_2_.Q & reg_ID_3_1_.Q & reg_ID_3_0_.Q # reg_ID_3_2_.Q & !reg_ID_3_1_.Q # reg_ID_3_2_.Q & !reg_ID_3_0_.Q ; (3 pterms, 3 signals) reg_ID_3_2_.C = clk ; (1 pterm, 1 signal) reg_ID_3_2_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_2_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_3_.D = !reg_ID_3_3_.Q & reg_ID_3_2_.Q & reg_ID_3_1_.Q & reg_ID_3_0_.Q # reg_ID_3_3_.Q & !reg_ID_3_1_.Q # reg_ID_3_3_.Q & !reg_ID_3_2_.Q # reg_ID_3_3_.Q & !reg_ID_3_0_.Q ; (4 pterms, 4 signals) reg_ID_3_3_.C = clk ; (1 pterm, 1 signal) reg_ID_3_3_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_3_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_4_.D.X1 = reg_ID_3_4_.Q ; (1 pterm, 1 signal) reg_ID_3_4_.D.X2 = reg_ID_3_3_.Q & reg_ID_3_2_.Q & reg_ID_3_1_.Q & reg_ID_3_0_.Q ; (1 pterm, 4 signals) reg_ID_3_4_.C = clk ; (1 pterm, 1 signal) reg_ID_3_4_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_4_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_5_.T = reg_ID_3_4_.Q & reg_ID_3_3_.Q & reg_ID_3_2_.Q & reg_ID_3_1_.Q & reg_ID_3_0_.Q ; (1 pterm, 5 signals) reg_ID_3_5_.C = clk ; (1 pterm, 1 signal) reg_ID_3_5_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_5_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_6_.T = reg_ID_3_5_.Q & reg_ID_3_4_.Q & reg_ID_3_3_.Q & reg_ID_3_2_.Q & reg_ID_3_1_.Q & reg_ID_3_0_.Q ; (1 pterm, 6 signals) reg_ID_3_6_.C = clk ; (1 pterm, 1 signal) reg_ID_3_6_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_6_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_6__0 = !ni_reg_ce_prty_bit_pos.Q # reg_ID_3_6_.Q & reg_ID_3_5_.Q & reg_ID_3_4_.Q & reg_ID_3_3_.Q & reg_ID_3_2_.Q & reg_ID_3_1_.Q & reg_ID_3_0_.Q ; (2 pterms, 8 signals) reg_ni_pattcount_0_.D = !reg_ni_pattcount_0_.Q ; (1 pterm, 1 signal) reg_ni_pattcount_0_.C = clk ; (1 pterm, 1 signal) reg_ni_pattcount_1_.D = reg_ni_pattcount_1_.Q & !reg_ni_pattcount_0_.Q # !reg_ni_pattcount_1_.Q & reg_ni_pattcount_0_.Q ; (2 pterms, 2 signals) reg_ni_pattcount_1_.C = clk ; (1 pterm, 1 signal) reg_ni_pattcount_2_.D = !reg_ni_pattcount_2_.Q & reg_ni_pattcount_1_.Q & reg_ni_pattcount_0_.Q # reg_ni_pattcount_2_.Q & !reg_ni_pattcount_1_.Q # reg_ni_pattcount_2_.Q & !reg_ni_pattcount_0_.Q ; (3 pterms, 3 signals) reg_ni_pattcount_2_.C = clk ; (1 pterm, 1 signal) reg_ni_pattcount_3_.D = reg_ni_pattcount_2_.Q & reg_ni_pattcount_1_.Q & reg_ni_pattcount_0_.Q & !reg_ni_pattcount_3_.Q # !reg_ni_pattcount_0_.Q & reg_ni_pattcount_3_.Q # !reg_ni_pattcount_1_.Q & reg_ni_pattcount_3_.Q # !reg_ni_pattcount_2_.Q & reg_ni_pattcount_3_.Q ; (4 pterms, 4 signals) reg_ni_pattcount_3_.C = clk ; (1 pterm, 1 signal) reg_ni_pattcount_4_.D.X1 = reg_ni_pattcount_2_.Q & reg_ni_pattcount_1_.Q & reg_ni_pattcount_0_.Q & reg_ni_pattcount_3_.Q ; (1 pterm, 4 signals) reg_ni_pattcount_4_.D.X2 = reg_ni_pattcount_4_.Q ; (1 pterm, 1 signal) reg_ni_pattcount_4_.C = clk ; (1 pterm, 1 signal) testpatt = j2c__ix77 & j2c__ix99 & !j2c__ix85 & !j2c__ix107 ; (1 pterm, 4 signals)