-- VHDL netlist-file
library mach;
use mach.components.all;

library ieee;
use ieee.std_logic_1164.all;
entity top_ni is
  port (
    NI_D : in std_logic_vector(9 downto 0);
    NI_STR : in std_logic;
    reset_n : in std_logic;
    clk : in std_logic;
    TESTEN : out std_logic;
    PRBSEN : out std_logic;
    LCKREFN : out std_logic;
    ENABLE : out std_logic;
    LOOPEN : out std_logic;
    TX_ER : out std_logic;
    DIS_JTG : in std_logic;
    FAULT : in std_logic;
    EN : out std_logic;
    SD2ANL : out std_logic;
    WP_EEP : out std_logic;
    SCL : out std_logic;
    SDA : inout std_logic;
    jTCK : in std_logic;
    jTDI : in std_logic;
    jTDO : out std_logic;
    jTMS : in std_logic;
    TXD : out std_logic_vector(15 downto 0);
    TX_EN : out std_logic
  );
end top_ni;

architecture NetList of top_ni is

  signal NI_D_9XPIN : std_logic;
  signal NI_STRPIN : std_logic;
  signal reset_nPIN : std_logic;
  signal clkPIN : std_logic;
  signal PRBSENCOM : std_logic;
  signal ENABLECOM : std_logic;
  signal DIS_JTGPIN : std_logic;
  signal FAULTPIN : std_logic;
  signal ENCOM : std_logic;
  signal SD2ANLCOM : std_logic;
  signal WP_EEPCOM : std_logic;
  signal SDAPIN : std_logic;
  signal jTCKPIN : std_logic;
  signal jTDIPIN : std_logic;
  signal jTDOCOM : std_logic;
  signal jTMSPIN : std_logic;
  signal NI_D_8XPIN : std_logic;
  signal NI_D_7XPIN : std_logic;
  signal NI_D_6XPIN : std_logic;
  signal NI_D_5XPIN : std_logic;
  signal NI_D_4XPIN : std_logic;
  signal NI_D_3XPIN : std_logic;
  signal NI_D_2XPIN : std_logic;
  signal NI_D_1XPIN : std_logic;
  signal NI_D_0XPIN : std_logic;
  signal TXD_4XQ : std_logic;
  signal TXD_3XQ : std_logic;
  signal TXD_2XQ : std_logic;
  signal TXD_1XQ : std_logic;
  signal TXD_0XQ : std_logic;
  signal TX_ENQ : std_logic;
  signal TXD_15XQ : std_logic;
  signal TXD_14XQ : std_logic;
  signal TXD_13XQ : std_logic;
  signal TXD_12XQ : std_logic;
  signal TXD_11XQ : std_logic;
  signal TXD_10XQ : std_logic;
  signal TXD_9XQ : std_logic;
  signal TXD_8XQ : std_logic;
  signal TXD_7XQ : std_logic;
  signal TXD_6XQ : std_logic;
  signal TXD_5XQ : std_logic;
  signal ni_nires_reg_data0pos_1_busQ : std_logic;
  signal ni_nires_reg_data2pos_1_busQ : std_logic;
  signal ni_nires_reg_data_out_10_busQ : std_logic;
  signal ni_nires_reg_data3pos_0_busQ : std_logic;
  signal ni_nires_reg_data1pos_0_busQ : std_logic;
  signal ni_nires_reg_data0pos_0_busQ : std_logic;
  signal ni_nires_reg_data2pos_0_busQ : std_logic;
  signal ni_nires_reg_data_out_12_busQ : std_logic;
  signal ni_nires_reg_data3pos_2_busQ : std_logic;
  signal ni_nires_reg_data1pos_2_busQ : std_logic;
  signal ni_nires_reg_data0pos_2_busQ : std_logic;
  signal ni_nires_reg_data2pos_2_busQ : std_logic;
  signal ni_nires_reg_data_out_13_busQ : std_logic;
  signal ni_nires_reg_data3pos_3_busQ : std_logic;
  signal ni_nires_reg_data1pos_3_busQ : std_logic;
  signal ni_nires_reg_data0pos_3_busQ : std_logic;
  signal ni_nires_reg_data2pos_3_busQ : std_logic;
  signal ni_nires_reg_data_out_14_busQ : std_logic;
  signal ni_nires_reg_data3pos_4_busQ : std_logic;
  signal ni_nires_reg_data1pos_4_busQ : std_logic;
  signal ni_nires_reg_data0pos_4_busQ : std_logic;
  signal ni_nires_reg_data2pos_4_busQ : std_logic;
  signal ni_nires_reg_data_out_15_busQ : std_logic;
  signal ni_nires_reg_data3pos_5_busQ : std_logic;
  signal ni_nires_reg_data1pos_5_busQ : std_logic;
  signal ni_nires_reg_data0pos_5_busQ : std_logic;
  signal ni_nires_reg_data2pos_5_busQ : std_logic;
  signal ni_nires_reg_data_out_16_busQ : std_logic;
  signal ni_nires_reg_data3pos_6_busQ : std_logic;
  signal ni_nires_reg_data1pos_6_busQ : std_logic;
  signal ni_nires_reg_data0pos_6_busQ : std_logic;
  signal ni_nires_reg_data2pos_6_busQ : std_logic;
  signal j2c_reg_creg1hm_2_busQ : std_logic;
  signal ni_nires_reg_data_out_17_busQ : std_logic;
  signal j2c_reg_cmdreg_0_busQ : std_logic;
  signal ni_nires_reg_data3pos_7_busQ : std_logic;
  signal ni_nires_reg_data1pos_7_busQ : std_logic;
  signal j2c_reg_shreg_4_busQ : std_logic;
  signal ni_nires_reg_data0pos_7_busQ : std_logic;
  signal j2c_reg_shreg_5_busQ : std_logic;
  signal ni_nires_reg_data2pos_7_busQ : std_logic;
  signal j2c_reg_shreg_6_busQ : std_logic;
  signal j2c_reg_shreg_7_busQ : std_logic;
  signal j2c_reg_cmdreg_3_busQ : std_logic;
  signal ni_nires_reg_data_out_18_busQ : std_logic;
  signal ni_nires_reg_data3pos_8_busQ : std_logic;
  signal ni_nires_reg_data1pos_8_busQ : std_logic;
  signal j2c_reg_creg1hm_6_busQ : std_logic;
  signal ni_nires_reg_data0pos_8_busQ : std_logic;
  signal j2c_reg_creg1hm_5_busQ : std_logic;
  signal ni_nires_reg_data2pos_8_busQ : std_logic;
  signal j2c_reg_creg1hm_4_busQ : std_logic;
  signal j2c_reg_creg1hm_3_busQ : std_logic;
  signal ni_nires_reg_data_out_19_busQ : std_logic;
  signal ni_nires_reg_data3pos_9_busQ : std_logic;
  signal ni_nires_reg_data1pos_9_busQ : std_logic;
  signal j2c_reg_creg1hm_1_busQ : std_logic;
  signal ni_nires_reg_data0pos_9_busQ : std_logic;
  signal ni_nires_reg_data2pos_9_busQ : std_logic;
  signal j2c_reg_creg1hm_0_busQ : std_logic;
  signal j2c_reg_cmdreg_2_busQ : std_logic;
  signal j2c_reg_cmdreg_1_busQ : std_logic;
  signal ID_3_5_busQ : std_logic;
  signal ni_reg_ce_prty_bit_posQ : std_logic;
  signal ni_reg_prty_bit_pos_rQ : std_logic;
  signal ni_pattcount_2_busQ : std_logic;
  signal ni_pattcount_1_busQ : std_logic;
  signal ni_pattcount_0_busQ : std_logic;
  signal ni_pattcount_4_busQ : std_logic;
  signal ni_pattcount_3_busQ : std_logic;
  signal ID_3_6_busQ : std_logic;
  signal ID_3_4_busQ : std_logic;
  signal ID_3_3_busQ : std_logic;
  signal ID_3_2_busQ : std_logic;
  signal ni_nires_reg_validQ : std_logic;
  signal ID_3_1_busQ : std_logic;
  signal ni_nires_reg_new_cnt_0_busQ : std_logic;
  signal ID_3_0_busQ : std_logic;
  signal ni_nires_reg_gray_cntf_0_busQ : std_logic;
  signal j2c_reg_clearQ : std_logic;
  signal ni_nires_reg_gray_cntf_1_busQ : std_logic;
  signal ni_nires_reg_clear_n_iQ : std_logic;
  signal j2c_reg_rstout_n_iQ : std_logic;
  signal j2c_bitcnt_2_busQ : std_logic;
  signal j2c_bitcnt_1_busQ : std_logic;
  signal j2c_bitcnt_0_busQ : std_logic;
  signal ID_2_5_busQ : std_logic;
  signal ni_reg_ce_prty_bit_negQ : std_logic;
  signal ni_reg_prty_bit_neg_rQ : std_logic;
  signal ni_nires_reg_old_cnt_0_busQ : std_logic;
  signal ni_nires_reg_old_cnt_1_busQ : std_logic;
  signal ni_nires_reg_new_cnt_1_busQ : std_logic;
  signal ni_nires_reg_data_out_1_busQ : std_logic;
  signal ID_2_6_busQ : std_logic;
  signal ni_nires_reg_data3neg_1_busQ : std_logic;
  signal ID_2_4_busQ : std_logic;
  signal ni_nires_reg_data1neg_1_busQ : std_logic;
  signal ID_2_3_busQ : std_logic;
  signal ID_2_2_busQ : std_logic;
  signal ni_nires_reg_data0neg_1_busQ : std_logic;
  signal ID_2_1_busQ : std_logic;
  signal ID_2_0_busQ : std_logic;
  signal ni_nires_reg_data2neg_1_busQ : std_logic;
  signal ni_nires_reg_data_out_0_busQ : std_logic;
  signal ni_nires_reg_data3neg_0_busQ : std_logic;
  signal ni_nires_reg_data1neg_0_busQ : std_logic;
  signal ni_nires_reg_data0neg_0_busQ : std_logic;
  signal ni_nires_reg_data2neg_0_busQ : std_logic;
  signal j2c_reg_creg0hm_4_busQ : std_logic;
  signal j2c_reg_shreg_1_busQ : std_logic;
  signal j2c_reg_shreg_2_busQ : std_logic;
  signal j2c_reg_shreg_3_busQ : std_logic;
  signal j2c_reg_creg0hm_6_busQ : std_logic;
  signal j2c_reg_creg0hm_5_busQ : std_logic;
  signal j2c_reg_creg0hm_2_busQ : std_logic;
  signal ID_0_6_busQ : std_logic;
  signal j2c_reg_shreg_0_busQ : std_logic;
  signal ID_0_5_busQ : std_logic;
  signal j2c_reg_creg0hm_1_busQ : std_logic;
  signal ID_0_4_busQ : std_logic;
  signal ID_0_3_busQ : std_logic;
  signal ID_0_2_busQ : std_logic;
  signal ID_0_1_busQ : std_logic;
  signal ID_0_0_busQ : std_logic;
  signal j2c_reg_creg0hm_3_busQ : std_logic;
  signal j2c_reg_creg0hm_0_busQ : std_logic;
  signal ID_0_7_busQ : std_logic;
  signal ID_1_4_busQ : std_logic;
  signal ID_1_3_busQ : std_logic;
  signal ID_1_2_busQ : std_logic;
  signal ni_nires_reg_data_out_2_busQ : std_logic;
  signal ID_1_1_busQ : std_logic;
  signal ni_nires_reg_data3neg_2_busQ : std_logic;
  signal ID_1_0_busQ : std_logic;
  signal ni_nires_reg_data1neg_2_busQ : std_logic;
  signal ni_nires_reg_data0neg_2_busQ : std_logic;
  signal ni_nires_reg_data2neg_2_busQ : std_logic;
  signal ni_nires_reg_data_out_3_busQ : std_logic;
  signal ni_nires_reg_data3neg_3_busQ : std_logic;
  signal ni_nires_reg_data1neg_3_busQ : std_logic;
  signal ni_nires_reg_data0neg_3_busQ : std_logic;
  signal ni_nires_reg_data2neg_3_busQ : std_logic;
  signal ID_1_5_busQ : std_logic;
  signal ID_1_6_busQ : std_logic;
  signal ni_nires_reg_data_out_4_busQ : std_logic;
  signal ni_nires_reg_data3neg_4_busQ : std_logic;
  signal ni_nires_reg_data1neg_4_busQ : std_logic;
  signal ni_nires_reg_data0neg_4_busQ : std_logic;
  signal ni_nires_reg_data2neg_4_busQ : std_logic;
  signal ni_nires_reg_data_out_5_busQ : std_logic;
  signal ni_nires_reg_data3neg_5_busQ : std_logic;
  signal ni_nires_reg_data1neg_5_busQ : std_logic;
  signal ni_nires_reg_data0neg_5_busQ : std_logic;
  signal ni_nires_reg_data2neg_5_busQ : std_logic;
  signal ni_nires_reg_data_out_6_busQ : std_logic;
  signal ni_nires_reg_data3neg_6_busQ : std_logic;
  signal ni_nires_reg_data1neg_6_busQ : std_logic;
  signal ni_nires_reg_data0neg_6_busQ : std_logic;
  signal ni_nires_reg_data2neg_6_busQ : std_logic;
  signal ni_nires_reg_data_out_7_busQ : std_logic;
  signal ni_nires_reg_data3neg_7_busQ : std_logic;
  signal ni_nires_reg_data1neg_7_busQ : std_logic;
  signal ni_nires_reg_data0neg_7_busQ : std_logic;
  signal ni_nires_reg_data2neg_7_busQ : std_logic;
  signal ni_nires_reg_data_out_8_busQ : std_logic;
  signal ni_nires_reg_data3neg_8_busQ : std_logic;
  signal ni_nires_reg_data1neg_8_busQ : std_logic;
  signal ni_nires_reg_data0neg_8_busQ : std_logic;
  signal ni_nires_reg_data2neg_8_busQ : std_logic;
  signal ni_nires_reg_data_out_9_busQ : std_logic;
  signal ni_nires_reg_data3neg_9_busQ : std_logic;
  signal ni_nires_reg_data1neg_9_busQ : std_logic;
  signal ni_nires_reg_data0neg_9_busQ : std_logic;
  signal ni_nires_reg_data2neg_9_busQ : std_logic;
  signal ni_nires_reg_data_out_11_busQ : std_logic;
  signal ni_nires_reg_data3pos_1_busQ : std_logic;
  signal ni_nires_reg_gray_cnt_1_busQ : std_logic;
  signal ni_nires_reg_gray_cnt_0_busQ : std_logic;
  signal ni_nires_reg_data1pos_1_busQ : std_logic;
  signal T_0 : std_logic;
  signal T_1 : std_logic;
  signal T_2 : std_logic;
  signal T_3 : std_logic;
  signal SCL_OE : std_logic;
  signal SDA_OE : std_logic;
  signal T_4 : std_logic;
  signal TXD_4X_D : std_logic;
  signal TXD_3X_D_X1 : std_logic;
  signal TXD_3X_D_X2 : std_logic;
  signal TXD_2X_D : std_logic;
  signal TXD_1X_D : std_logic;
  signal TXD_0X_D : std_logic;
  signal T_5 : std_logic;
  signal TXD_15X_D_X1 : std_logic;
  signal TXD_15X_D_X2 : std_logic;
  signal TXD_14X_D : std_logic;
  signal TXD_13X_D : std_logic;
  signal TXD_12X_D : std_logic;
  signal TXD_11X_D_X1 : std_logic;
  signal TXD_11X_D_X2 : std_logic;
  signal TXD_10X_D : std_logic;
  signal TXD_9X_D : std_logic;
  signal TXD_8X_D : std_logic;
  signal TXD_7X_D_X1 : std_logic;
  signal TXD_7X_D_X2 : std_logic;
  signal TXD_6X_D : std_logic;
  signal TXD_5X_D : std_logic;
  signal ni_nires_reg_data0pos_1_bus_CE : std_logic;
  signal nx2236 : std_logic;
  signal ni_nires_reg_data2pos_1_bus_CE : std_logic;
  signal ni_nires_reg_data_out_10_bus_D : std_logic;
  signal ni_nires_reg_data3pos_0_bus_CE : std_logic;
  signal ni_nires_reg_data1pos_0_bus_CE : std_logic;
  signal nx1195 : std_logic;
  signal ni_nires_reg_data0pos_0_bus_CE : std_logic;
  signal ni_nires_reg_data2pos_0_bus_CE : std_logic;
  signal ni_nires_reg_data_out_12_bus_D : std_logic;
  signal ni_nires_reg_data3pos_2_bus_CE : std_logic;
  signal nx2272_X1 : std_logic;
  signal nx2272_X2 : std_logic;
  signal ni_nires_reg_data1pos_2_bus_CE : std_logic;
  signal ni_nires_reg_data0pos_2_bus_CE : std_logic;
  signal ix1266 : std_logic;
  signal ni_nires_reg_data2pos_2_bus_CE : std_logic;
  signal nx1271 : std_logic;
  signal ni_nires_reg_data_out_13_bus_D : std_logic;
  signal ni_nires_reg_data3pos_3_bus_CE : std_logic;
  signal ni_nires_reg_data1pos_3_bus_CE : std_logic;
  signal nx2294 : std_logic;
  signal ni_nires_reg_data0pos_3_bus_CE : std_logic;
  signal nx1361 : std_logic;
  signal ni_nires_reg_data2pos_3_bus_CE : std_logic;
  signal ni_nires_reg_data_out_14_bus_D : std_logic;
  signal ni_nires_reg_data3pos_4_bus_CE : std_logic;
  signal ni_nires_reg_data1pos_4_bus_CE : std_logic;
  signal ni_nires_reg_data0pos_4_bus_CE : std_logic;
  signal ni_nires_reg_data2pos_4_bus_CE : std_logic;
  signal ni_nires_reg_data_out_15_bus_D : std_logic;
  signal ni_nires_reg_data3pos_5_bus_CE : std_logic;
  signal ni_nires_reg_data1pos_5_bus_CE : std_logic;
  signal ni_nires_reg_data0pos_5_bus_CE : std_logic;
  signal ni_nires_reg_data2pos_5_bus_CE : std_logic;
  signal ni_nires_reg_data_out_16_bus_D : std_logic;
  signal ni_nires_reg_data3pos_6_bus_CE : std_logic;
  signal ni_nires_reg_data1pos_6_bus_CE : std_logic;
  signal ni_nires_reg_data0pos_6_bus_CE : std_logic;
  signal ni_nires_reg_data2pos_6_bus_CE : std_logic;
  signal jTDO_OE : std_logic;
  signal j2c_reg_creg1hm_2_bus_C : std_logic;
  signal j2c_reg_creg1hm_2_bus_CE : std_logic;
  signal j2c_reg_creg1hm_2_bus_AP : std_logic;
  signal ni_nires_reg_data_out_17_bus_D : std_logic;
  signal j2c_reg_cmdreg_0_bus_C : std_logic;
  signal j2c_reg_cmdreg_0_bus_AP : std_logic;
  signal ni_nires_reg_data3pos_7_bus_CE : std_logic;
  signal j2c_reg_clear_AR : std_logic;
  signal ni_nires_reg_data1pos_7_bus_CE : std_logic;
  signal ni_nires_reg_data0pos_7_bus_CE : std_logic;
  signal ni_nires_reg_data2pos_7_bus_CE : std_logic;
  signal j2c_reg_cmdreg_3_bus_D : std_logic;
  signal j2c_reg_cmdreg_3_bus_C : std_logic;
  signal j2c_reg_cmdreg_3_bus_AR : std_logic;
  signal ni_nires_reg_data_out_18_bus_D : std_logic;
  signal ni_nires_reg_data3pos_8_bus_CE : std_logic;
  signal ni_nires_reg_data1pos_8_bus_CE : std_logic;
  signal j2c_reg_creg1hm_6_bus_C : std_logic;
  signal j2c_reg_creg1hm_6_bus_CE : std_logic;
  signal j2c_reg_creg1hm_6_bus_AP : std_logic;
  signal ni_nires_reg_data0pos_8_bus_CE : std_logic;
  signal j2c_reg_creg1hm_5_bus_C : std_logic;
  signal j2c_reg_creg1hm_5_bus_CE : std_logic;
  signal j2c_reg_creg1hm_5_bus_AR : std_logic;
  signal ni_nires_reg_data2pos_8_bus_CE : std_logic;
  signal j2c_reg_creg1hm_4_bus_C : std_logic;
  signal j2c_reg_creg1hm_4_bus_CE : std_logic;
  signal j2c_reg_creg1hm_4_bus_AR : std_logic;
  signal j2c_reg_creg1hm_3_bus_D : std_logic;
  signal j2c_reg_creg1hm_3_bus_C : std_logic;
  signal j2c_reg_creg1hm_3_bus_CE : std_logic;
  signal j2c_reg_creg1hm_3_bus_AP : std_logic;
  signal ni_nires_reg_data_out_19_bus_D : std_logic;
  signal ni_nires_reg_data3pos_9_bus_CE : std_logic;
  signal ix47_X1 : std_logic;
  signal ni_nires_reg_data1pos_9_bus_CE : std_logic;
  signal nx1519 : std_logic;
  signal j2c_reg_creg1hm_1_bus_D : std_logic;
  signal j2c_reg_creg1hm_1_bus_C : std_logic;
  signal j2c_reg_creg1hm_1_bus_CE : std_logic;
  signal j2c_reg_creg1hm_1_bus_AR : std_logic;
  signal ni_nires_reg_data0pos_9_bus_CE : std_logic;
  signal ix1524 : std_logic;
  signal ni_nires_reg_data2pos_9_bus_CE : std_logic;
  signal ix1578 : std_logic;
  signal ix59_X1 : std_logic;
  signal j2c_reg_creg1hm_0_bus_D : std_logic;
  signal j2c_reg_creg1hm_0_bus_C : std_logic;
  signal j2c_reg_creg1hm_0_bus_CE : std_logic;
  signal j2c_reg_creg1hm_0_bus_AR : std_logic;
  signal j2c_reg_cmdreg_2_bus_C : std_logic;
  signal j2c_reg_cmdreg_2_bus_AP : std_logic;
  signal j2c_reg_cmdreg_1_bus_C : std_logic;
  signal j2c_reg_cmdreg_1_bus_AP : std_logic;
  signal nx1595 : std_logic;
  signal ix1598 : std_logic;
  signal ix71_X1 : std_logic;
  signal ix1610 : std_logic;
  signal ID_3_5_bus_T : std_logic;
  signal ni_reg_ce_prty_bit_pos_D : std_logic;
  signal ni_reg_prty_bit_pos_r_D : std_logic;
  signal ni_pattcount_2_bus_D : std_logic;
  signal ni_pattcount_1_bus_D : std_logic;
  signal ni_pattcount_0_bus_D : std_logic;
  signal ix1641_X1 : std_logic;
  signal ix1647_X1 : std_logic;
  signal nx1647 : std_logic;
  signal ni_pattcount_4_bus_D_X1 : std_logic;
  signal ni_pattcount_3_bus_D : std_logic;
  signal ID_3_6_bus_T : std_logic;
  signal ID_3_4_bus_D_X2 : std_logic;
  signal ID_3_3_bus_D : std_logic;
  signal ID_3_2_bus_D : std_logic;
  signal ni_nires_reg_valid_D : std_logic;
  signal ID_3_1_bus_D : std_logic;
  signal ni_nires_reg_new_cnt_0_bus_AR : std_logic;
  signal ID_3_0_bus_D : std_logic;
  signal ni_nires_reg_gray_cntf_0_bus_D : std_logic;
  signal ni_nires_reg_gray_cntf_0_bus_C : std_logic;
  signal ni_nires_reg_gray_cntf_0_bus_AR : std_logic;
  signal T_6 : std_logic;
  signal j2c_reg_clear_C : std_logic;
  signal ni_nires_reg_gray_cntf_1_bus_C : std_logic;
  signal ni_nires_reg_gray_cntf_1_bus_AR : std_logic;
  signal ni_nires_reg_clear_n_i_D : std_logic;
  signal j2c_reg_rstout_n_i_D : std_logic;
  signal j2c_reg_rstout_n_i_C : std_logic;
  signal j2c_bitcnt_2_bus_D : std_logic;
  signal j2c_bitcnt_2_bus_C : std_logic;
  signal nx1717 : std_logic;
  signal j2c_bitcnt_1_bus_D : std_logic;
  signal j2c_bitcnt_1_bus_C : std_logic;
  signal j2c_bitcnt_0_bus_D : std_logic;
  signal j2c_bitcnt_0_bus_C : std_logic;
  signal nx1725 : std_logic;
  signal ID_2_5_bus_T : std_logic;
  signal ni_reg_ce_prty_bit_neg_D_X1 : std_logic;
  signal ni_reg_ce_prty_bit_neg_D_X2 : std_logic;
  signal ni_reg_prty_bit_neg_r_D : std_logic;
  signal ni_nires_reg_old_cnt_0_bus_D : std_logic;
  signal ni_nires_reg_old_cnt_0_bus_AR : std_logic;
  signal ni_nires_reg_old_cnt_0_bus_CE : std_logic;
  signal nx1759 : std_logic;
  signal ni_nires_reg_old_cnt_1_bus_AR : std_logic;
  signal ix1771_X1 : std_logic;
  signal ix1773 : std_logic;
  signal ix1775 : std_logic;
  signal ni_nires_reg_new_cnt_1_bus_AR : std_logic;
  signal TXD_4X_CE : std_logic;
  signal ni_nires_reg_data_out_1_bus_D : std_logic;
  signal ID_2_6_bus_T : std_logic;
  signal ni_nires_reg_data3neg_1_bus_C : std_logic;
  signal ni_nires_reg_data3neg_1_bus_CE : std_logic;
  signal ID_2_4_bus_D_X2 : std_logic;
  signal ni_nires_reg_data1neg_1_bus_C : std_logic;
  signal ni_nires_reg_data1neg_1_bus_CE : std_logic;
  signal ID_2_3_bus_D : std_logic;
  signal ID_2_2_bus_D : std_logic;
  signal ni_nires_reg_data0neg_1_bus_C : std_logic;
  signal ni_nires_reg_data0neg_1_bus_CE : std_logic;
  signal ID_2_1_bus_D : std_logic;
  signal ID_2_0_bus_D : std_logic;
  signal ni_nires_reg_data2neg_1_bus_C : std_logic;
  signal ni_nires_reg_data2neg_1_bus_CE : std_logic;
  signal nx1815_X1 : std_logic;
  signal nx1815_X2 : std_logic;
  signal ni_nires_reg_data_out_0_bus_D : std_logic;
  signal ni_nires_reg_data3neg_0_bus_C : std_logic;
  signal ni_nires_reg_data3neg_0_bus_CE : std_logic;
  signal ni_nires_reg_data1neg_0_bus_C : std_logic;
  signal ni_nires_reg_data1neg_0_bus_CE : std_logic;
  signal ni_nires_reg_data0neg_0_bus_C : std_logic;
  signal ni_nires_reg_data0neg_0_bus_CE : std_logic;
  signal ni_nires_reg_data2neg_0_bus_C : std_logic;
  signal ni_nires_reg_data2neg_0_bus_CE : std_logic;
  signal j2c_reg_creg0hm_4_bus_C : std_logic;
  signal j2c_reg_creg0hm_4_bus_CE : std_logic;
  signal j2c_reg_creg0hm_4_bus_AR : std_logic;
  signal nx1851 : std_logic;
  signal j2c_reg_creg0hm_6_bus_C : std_logic;
  signal j2c_reg_creg0hm_6_bus_CE : std_logic;
  signal j2c_reg_creg0hm_6_bus_AP : std_logic;
  signal j2c_reg_creg0hm_5_bus_C : std_logic;
  signal j2c_reg_creg0hm_5_bus_CE : std_logic;
  signal j2c_reg_creg0hm_5_bus_AR : std_logic;
  signal nx1912 : std_logic;
  signal j2c_reg_creg0hm_2_bus_C : std_logic;
  signal j2c_reg_creg0hm_2_bus_CE : std_logic;
  signal j2c_reg_creg0hm_2_bus_AR : std_logic;
  signal ID_0_6_bus_T : std_logic;
  signal ID_0_5_bus_T : std_logic;
  signal j2c_reg_creg0hm_1_bus_D : std_logic;
  signal j2c_reg_creg0hm_1_bus_C : std_logic;
  signal j2c_reg_creg0hm_1_bus_CE : std_logic;
  signal j2c_reg_creg0hm_1_bus_AP : std_logic;
  signal ID_0_4_bus_D_X2 : std_logic;
  signal ID_0_3_bus_D : std_logic;
  signal ID_0_2_bus_D : std_logic;
  signal ID_0_1_bus_D : std_logic;
  signal ID_0_0_bus_D : std_logic;
  signal ix373_X1 : std_logic;
  signal j2c_reg_creg0hm_3_bus_D : std_logic;
  signal j2c_reg_creg0hm_3_bus_C : std_logic;
  signal j2c_reg_creg0hm_3_bus_CE : std_logic;
  signal j2c_reg_creg0hm_3_bus_AP : std_logic;
  signal nx1909 : std_logic;
  signal ix385_X1 : std_logic;
  signal j2c_reg_creg0hm_0_bus_D : std_logic;
  signal j2c_reg_creg0hm_0_bus_C : std_logic;
  signal j2c_reg_creg0hm_0_bus_CE : std_logic;
  signal j2c_reg_creg0hm_0_bus_AP : std_logic;
  signal ix397_X1 : std_logic;
  signal ID_0_7_bus_T : std_logic;
  signal ID_1_4_bus_T : std_logic;
  signal ID_1_3_bus_D_X2 : std_logic;
  signal ID_1_2_bus_D : std_logic;
  signal nx1949 : std_logic;
  signal ni_nires_reg_data_out_2_bus_D : std_logic;
  signal ID_1_1_bus_D : std_logic;
  signal ni_nires_reg_data3neg_2_bus_C : std_logic;
  signal ni_nires_reg_data3neg_2_bus_CE : std_logic;
  signal ID_1_0_bus_D : std_logic;
  signal ni_nires_reg_data1neg_2_bus_C : std_logic;
  signal ni_nires_reg_data1neg_2_bus_CE : std_logic;
  signal ni_nires_reg_data0neg_2_bus_C : std_logic;
  signal ni_nires_reg_data0neg_2_bus_CE : std_logic;
  signal ni_nires_reg_data2neg_2_bus_C : std_logic;
  signal ni_nires_reg_data2neg_2_bus_CE : std_logic;
  signal nx1967 : std_logic;
  signal ni_nires_reg_data_out_3_bus_D : std_logic;
  signal ni_nires_reg_data3neg_3_bus_C : std_logic;
  signal ni_nires_reg_data3neg_3_bus_CE : std_logic;
  signal ni_nires_reg_data1neg_3_bus_C : std_logic;
  signal ni_nires_reg_data1neg_3_bus_CE : std_logic;
  signal ni_nires_reg_data0neg_3_bus_C : std_logic;
  signal ni_nires_reg_data0neg_3_bus_CE : std_logic;
  signal ni_nires_reg_data2neg_3_bus_C : std_logic;
  signal ni_nires_reg_data2neg_3_bus_CE : std_logic;
  signal ID_1_5_bus_T : std_logic;
  signal ID_1_6_bus_T : std_logic;
  signal ni_nires_reg_data_out_4_bus_D : std_logic;
  signal ni_nires_reg_data3neg_4_bus_C : std_logic;
  signal ni_nires_reg_data3neg_4_bus_CE : std_logic;
  signal ni_nires_reg_data1neg_4_bus_C : std_logic;
  signal ni_nires_reg_data1neg_4_bus_CE : std_logic;
  signal ni_nires_reg_data0neg_4_bus_C : std_logic;
  signal ni_nires_reg_data0neg_4_bus_CE : std_logic;
  signal ni_nires_reg_data2neg_4_bus_C : std_logic;
  signal ni_nires_reg_data2neg_4_bus_CE : std_logic;
  signal ni_nires_reg_data_out_5_bus_D : std_logic;
  signal ni_nires_reg_data3neg_5_bus_C : std_logic;
  signal ni_nires_reg_data3neg_5_bus_CE : std_logic;
  signal ni_nires_reg_data1neg_5_bus_C : std_logic;
  signal ni_nires_reg_data1neg_5_bus_CE : std_logic;
  signal ni_nires_reg_data0neg_5_bus_C : std_logic;
  signal ni_nires_reg_data0neg_5_bus_CE : std_logic;
  signal ni_nires_reg_data2neg_5_bus_C : std_logic;
  signal ni_nires_reg_data2neg_5_bus_CE : std_logic;
  signal ni_nires_reg_data_out_6_bus_D : std_logic;
  signal ni_nires_reg_data3neg_6_bus_C : std_logic;
  signal ni_nires_reg_data3neg_6_bus_CE : std_logic;
  signal ni_nires_reg_data1neg_6_bus_C : std_logic;
  signal ni_nires_reg_data1neg_6_bus_CE : std_logic;
  signal ni_nires_reg_data0neg_6_bus_C : std_logic;
  signal ni_nires_reg_data0neg_6_bus_CE : std_logic;
  signal ni_nires_reg_data2neg_6_bus_C : std_logic;
  signal ni_nires_reg_data2neg_6_bus_CE : std_logic;
  signal ni_nires_reg_data_out_7_bus_D : std_logic;
  signal ni_nires_reg_data3neg_7_bus_C : std_logic;
  signal ni_nires_reg_data3neg_7_bus_CE : std_logic;
  signal ni_nires_reg_data1neg_7_bus_C : std_logic;
  signal ni_nires_reg_data1neg_7_bus_CE : std_logic;
  signal ni_nires_reg_data0neg_7_bus_C : std_logic;
  signal ni_nires_reg_data0neg_7_bus_CE : std_logic;
  signal ni_nires_reg_data2neg_7_bus_C : std_logic;
  signal ni_nires_reg_data2neg_7_bus_CE : std_logic;
  signal ni_nires_reg_data_out_8_bus_D : std_logic;
  signal ni_nires_reg_data3neg_8_bus_C : std_logic;
  signal ni_nires_reg_data3neg_8_bus_CE : std_logic;
  signal ni_nires_reg_data1neg_8_bus_C : std_logic;
  signal ni_nires_reg_data1neg_8_bus_CE : std_logic;
  signal ni_nires_reg_data0neg_8_bus_C : std_logic;
  signal ni_nires_reg_data0neg_8_bus_CE : std_logic;
  signal ni_nires_reg_data2neg_8_bus_C : std_logic;
  signal ni_nires_reg_data2neg_8_bus_CE : std_logic;
  signal ni_nires_reg_data_out_9_bus_D : std_logic;
  signal ni_nires_reg_data3neg_9_bus_C : std_logic;
  signal ni_nires_reg_data3neg_9_bus_CE : std_logic;
  signal ni_nires_reg_data1neg_9_bus_C : std_logic;
  signal ni_nires_reg_data1neg_9_bus_CE : std_logic;
  signal ni_nires_reg_data0neg_9_bus_C : std_logic;
  signal ni_nires_reg_data0neg_9_bus_CE : std_logic;
  signal ni_nires_reg_data2neg_9_bus_C : std_logic;
  signal ni_nires_reg_data2neg_9_bus_CE : std_logic;
  signal ix1084 : std_logic;
  signal nx2210 : std_logic;
  signal ni_nires_reg_data_out_11_bus_D : std_logic;
  signal ni_nires_reg_data3pos_1_bus_CE : std_logic;
  signal ni_nires_reg_gray_cnt_1_bus_AR : std_logic;
  signal ni_nires_reg_gray_cnt_0_bus_D : std_logic;
  signal ni_nires_reg_gray_cnt_0_bus_AR : std_logic;
  signal ix1160 : std_logic;
  signal ni_nires_reg_data1pos_1_bus_CE : std_logic;
  signal ix1164 : std_logic;
  signal ID_3_5_X0 : std_logic;
  signal j2c_reg_clear_CE : std_logic;
  signal ID_2_5_X0 : std_logic;
  signal TXD_3X_D : std_logic;
  signal TXD_15X_D : std_logic;
  signal TXD_11X_D : std_logic;
  signal TXD_7X_D : std_logic;
  signal nx2272 : std_logic;
  signal ix47 : std_logic;
  signal ix59 : std_logic;
  signal ix71 : std_logic;
  signal ix1641 : std_logic;
  signal ix1647 : std_logic;
  signal ni_pattcount_4_bus_D : std_logic;
  signal ID_3_4_bus_D : std_logic;
  signal ni_reg_ce_prty_bit_neg_D : std_logic;
  signal ix1771 : std_logic;
  signal ID_2_4_bus_D : std_logic;
  signal nx1815 : std_logic;
  signal ID_0_4_bus_D : std_logic;
  signal ix373 : std_logic;
  signal ix385 : std_logic;
  signal ix397 : std_logic;
  signal ID_1_3_bus_D : std_logic;
  signal TX_EN_D : std_logic;
  signal ID_3_5_bus_CE : std_logic;
  signal ID_3_6_bus_CE : std_logic;
  signal ID_3_4_bus_CE : std_logic;
  signal ID_3_3_bus_CE : std_logic;
  signal ID_3_2_bus_CE : std_logic;
  signal ID_3_1_bus_CE : std_logic;
  signal ID_3_0_bus_CE : std_logic;
  signal j2c_reg_clear_D : std_logic;
  signal ID_2_5_bus_CE : std_logic;
  signal ID_2_6_bus_CE : std_logic;
  signal ID_2_4_bus_CE : std_logic;
  signal ID_2_3_bus_CE : std_logic;
  signal ID_2_2_bus_CE : std_logic;
  signal ID_2_1_bus_CE : std_logic;
  signal ID_2_0_bus_CE : std_logic;
  signal T_7 : std_logic;
  signal T_8 : std_logic;
  signal T_9 : std_logic;
  signal T_10 : std_logic;
  signal T_11 : std_logic;
  signal T_12 : std_logic;
  signal T_13 : std_logic;
  signal T_14 : std_logic;
  signal T_15 : std_logic;
  signal T_16 : std_logic;
  signal T_17 : std_logic;
  signal T_18 : std_logic;
  signal T_19 : std_logic;
  signal T_20 : std_logic;
  signal T_21 : std_logic;
  signal T_22 : std_logic;
  signal T_23 : std_logic;
  signal T_24 : std_logic;
  signal T_25 : std_logic;
  signal T_26 : std_logic;
  signal T_27 : std_logic;
  signal T_28 : std_logic;
  signal T_29 : std_logic;
  signal T_30 : std_logic;
  signal T_31 : std_logic;
  signal T_32 : std_logic;
  signal T_33 : std_logic;
  signal T_34 : std_logic;
  signal T_35 : std_logic;
  signal T_36 : std_logic;
  signal T_37 : std_logic;
  signal T_38 : std_logic;
  signal T_39 : std_logic;
  signal T_40 : std_logic;
  signal T_41 : std_logic;
  signal T_42 : std_logic;
  signal T_43 : std_logic;
  signal T_44 : std_logic;
  signal T_45 : std_logic;
  signal T_46 : std_logic;
  signal T_47 : std_logic;
  signal T_48 : std_logic;
  signal T_49 : std_logic;
  signal T_50 : std_logic;
  signal T_51 : std_logic;
  signal T_52 : std_logic;
  signal T_53 : std_logic;
  signal T_54 : std_logic;
  signal T_55 : std_logic;
  signal T_56 : std_logic;
  signal T_57 : std_logic;
  signal T_58 : std_logic;
  signal T_59 : std_logic;
  signal T_60 : std_logic;
  signal T_61 : std_logic;
  signal T_62 : std_logic;
  signal T_63 : std_logic;
  signal T_64 : std_logic;
  signal T_65 : std_logic;
  signal T_66 : std_logic;
  signal T_67 : std_logic;
  signal T_68 : std_logic;
  signal T_69 : std_logic;
  signal T_70 : std_logic;
  signal T_71 : std_logic;
  signal T_72 : std_logic;
  signal T_73 : std_logic;
  signal T_74 : std_logic;
  signal T_75 : std_logic;
  signal T_76 : std_logic;
  signal T_77 : std_logic;
  signal T_78 : std_logic;
  signal T_79 : std_logic;
  signal T_80 : std_logic;
  signal T_81 : std_logic;
  signal T_82 : std_logic;
  signal T_83 : std_logic;
  signal T_84 : std_logic;
  signal T_85 : std_logic;
  signal T_86 : std_logic;
  signal T_87 : std_logic;
  signal T_88 : std_logic;
  signal T_89 : std_logic;
  signal T_90 : std_logic;
  signal T_91 : std_logic;
  signal T_92 : std_logic;
  signal T_93 : std_logic;
  signal T_94 : std_logic;
  signal T_95 : std_logic;
  signal T_96 : std_logic;
  signal T_97 : std_logic;
  signal T_98 : std_logic;
  signal T_99 : std_logic;
  signal T_100 : std_logic;
  signal T_101 : std_logic;
  signal T_102 : std_logic;
  signal T_103 : std_logic;
  signal T_104 : std_logic;
  signal T_105 : std_logic;
  signal T_106 : std_logic;
  signal T_107 : std_logic;
  signal T_108 : std_logic;
  signal T_109 : std_logic;
  signal T_110 : std_logic;
  signal T_111 : std_logic;
  signal T_112 : std_logic;
  signal T_113 : std_logic;
  signal T_114 : std_logic;
  signal T_115 : std_logic;
  signal T_116 : std_logic;
  signal T_117 : std_logic;
  signal T_118 : std_logic;
  signal T_119 : std_logic;
  signal T_120 : std_logic;
  signal T_121 : std_logic;
  signal T_122 : std_logic;
  signal T_123 : std_logic;
  signal T_124 : std_logic;
  signal T_125 : std_logic;
  signal T_126 : std_logic;
  signal T_127 : std_logic;
  signal T_128 : std_logic;
  signal T_129 : std_logic;
  signal T_130 : std_logic;
  signal T_131 : std_logic;
  signal T_132 : std_logic;
  signal T_133 : std_logic;
  signal T_134 : std_logic;
  signal T_135 : std_logic;
  signal T_136 : std_logic;
  signal T_137 : std_logic;
  signal T_138 : std_logic;
  signal T_139 : std_logic;
  signal T_140 : std_logic;
  signal T_141 : std_logic;
  signal T_142 : std_logic;
  signal T_143 : std_logic;
  signal T_144 : std_logic;
  signal T_145 : std_logic;
  signal T_146 : std_logic;
  signal T_147 : std_logic;
  signal T_148 : std_logic;
  signal T_149 : std_logic;
  signal T_150 : std_logic;
  signal T_151 : std_logic;
  signal T_152 : std_logic;
  signal T_153 : std_logic;
  signal T_154 : std_logic;
  signal T_155 : std_logic;
  signal T_156 : std_logic;
  signal T_157 : std_logic;
  signal T_158 : std_logic;
  signal T_159 : std_logic;
  signal T_160 : std_logic;
  signal T_161 : std_logic;
  signal T_162 : std_logic;
  signal T_163 : std_logic;
  signal T_164 : std_logic;
  signal T_165 : std_logic;
  signal T_166 : std_logic;
  signal T_167 : std_logic;
  signal T_168 : std_logic;
  signal T_169 : std_logic;
  signal T_170 : std_logic;
  signal T_171 : std_logic;
  signal T_172 : std_logic;
  signal T_173 : std_logic;
  signal T_174 : std_logic;
  signal T_175 : std_logic;
  signal T_176 : std_logic;
  signal T_177 : std_logic;
  signal T_178 : std_logic;
  signal T_179 : std_logic;
  signal T_180 : std_logic;
  signal T_181 : std_logic;
  signal T_182 : std_logic;
  signal T_183 : std_logic;
  signal T_184 : std_logic;
  signal T_185 : std_logic;
  signal T_186 : std_logic;
  signal T_187 : std_logic;
  signal T_188 : std_logic;
  signal T_189 : std_logic;
  signal T_190 : std_logic;
  signal T_191 : std_logic;
  signal T_192 : std_logic;
  signal T_193 : std_logic;
  signal T_194 : std_logic;
  signal T_195 : std_logic;
  signal T_196 : std_logic;
  signal T_197 : std_logic;
  signal T_198 : std_logic;
  signal T_199 : std_logic;
  signal T_200 : std_logic;
  signal T_201 : std_logic;
  signal T_202 : std_logic;
  signal T_203 : std_logic;
  signal T_204 : std_logic;
  signal T_205 : std_logic;
  signal T_206 : std_logic;
  signal T_207 : std_logic;
  signal T_208 : std_logic;
  signal T_209 : std_logic;
  signal T_210 : std_logic;
  signal T_211 : std_logic;
  signal T_212 : std_logic;
  signal T_213 : std_logic;
  signal T_214 : std_logic;
  signal T_215 : std_logic;
  signal T_216 : std_logic;
  signal T_217 : std_logic;
  signal T_218 : std_logic;
  signal T_219 : std_logic;
  signal T_220 : std_logic;
  signal T_221 : std_logic;
  signal T_222 : std_logic;
  signal T_223 : std_logic;
  signal T_224 : std_logic;
  signal T_225 : std_logic;
  signal T_226 : std_logic;
  signal T_227 : std_logic;
  signal T_228 : std_logic;
  signal T_229 : std_logic;
  signal T_230 : std_logic;
  signal T_231 : std_logic;
  signal T_232 : std_logic;
  signal T_233 : std_logic;
  signal T_234 : std_logic;
  signal T_235 : std_logic;
  signal T_236 : std_logic;
  signal T_237 : std_logic;
  signal T_238 : std_logic;
  signal T_239 : std_logic;
  signal T_240 : std_logic;
  signal T_241 : std_logic;
  signal T_242 : std_logic;
  signal T_243 : std_logic;
  signal T_244 : std_logic;
  signal T_245 : std_logic;
  signal T_246 : std_logic;
  signal T_247 : std_logic;
  signal T_248 : std_logic;
  signal T_249 : std_logic;
  signal T_250 : std_logic;
  signal T_251 : std_logic;
  signal T_252 : std_logic;
  signal T_253 : std_logic;
  signal T_254 : std_logic;
  signal T_255 : std_logic;
  signal T_256 : std_logic;
  signal T_257 : std_logic;
  signal T_258 : std_logic;
  signal T_259 : std_logic;
  signal T_260 : std_logic;
  signal T_261 : std_logic;
  signal T_262 : std_logic;
  signal T_263 : std_logic;
  signal T_264 : std_logic;
  signal T_265 : std_logic;
  signal T_266 : std_logic;
  signal T_267 : std_logic;
  signal T_268 : std_logic;
  signal T_269 : std_logic;
  signal T_270 : std_logic;
  signal T_271 : std_logic;
  signal T_272 : std_logic;
  signal T_273 : std_logic;
  signal T_274 : std_logic;
  signal T_275 : std_logic;
  signal T_276 : std_logic;
  signal T_277 : std_logic;
  signal T_278 : std_logic;
  signal T_279 : std_logic;
  signal T_280 : std_logic;
  signal T_281 : std_logic;
  signal T_282 : std_logic;
  signal T_283 : std_logic;
  signal T_284 : std_logic;
  signal T_285 : std_logic;
  signal T_286 : std_logic;
  signal T_287 : std_logic;
  signal T_288 : std_logic;
  signal T_289 : std_logic;
  signal T_290 : std_logic;
  signal T_291 : std_logic;
  signal T_292 : std_logic;
  signal T_293 : std_logic;
  signal T_294 : std_logic;
  signal T_295 : std_logic;
  signal T_296 : std_logic;
  signal T_297 : std_logic;
  signal T_298 : std_logic;
  signal T_299 : std_logic;
  signal T_300 : std_logic;
  signal T_301 : std_logic;
  signal T_302 : std_logic;
  signal T_303 : std_logic;
  signal T_304 : std_logic;
  signal T_305 : std_logic;
  signal T_306 : std_logic;
  signal T_307 : std_logic;
  signal T_308 : std_logic;
  signal T_309 : std_logic;
  signal T_310 : std_logic;
  signal T_311 : std_logic;
  signal T_312 : std_logic;
  signal T_313 : std_logic;
  signal T_314 : std_logic;
  signal T_315 : std_logic;
  signal T_316 : std_logic;
  signal T_317 : std_logic;
  signal T_318 : std_logic;
  signal T_319 : std_logic;
  signal T_320 : std_logic;
  signal T_321 : std_logic;
  signal T_322 : std_logic;
  signal T_323 : std_logic;
  signal T_324 : std_logic;
  signal T_325 : std_logic;
  signal T_326 : std_logic;
  signal T_327 : std_logic;
  signal T_328 : std_logic;
  signal T_329 : std_logic;
  signal T_330 : std_logic;
  signal T_331 : std_logic;
  signal T_332 : std_logic;
  signal T_333 : std_logic;
  signal T_334 : std_logic;
  signal T_335 : std_logic;
  signal T_336 : std_logic;
  signal T_337 : std_logic;
  signal T_338 : std_logic;
  signal T_339 : std_logic;
  signal T_340 : std_logic;
  signal T_341 : std_logic;
  signal T_342 : std_logic;
  signal T_343 : std_logic;
  signal T_344 : std_logic;
  signal T_345 : std_logic;
  signal T_346 : std_logic;
  signal T_347 : std_logic;
  signal T_348 : std_logic;
  signal T_349 : std_logic;
  signal T_350 : std_logic;
  signal T_351 : std_logic;
  signal T_352 : std_logic;
  signal T_353 : std_logic;
  signal T_354 : std_logic;
  signal T_355 : std_logic;
  signal T_356 : std_logic;
  signal T_357 : std_logic;
  signal T_358 : std_logic;
  signal T_359 : std_logic;
  signal T_360 : std_logic;
  signal T_361 : std_logic;
  signal T_362 : std_logic;
  signal T_363 : std_logic;
  signal T_364 : std_logic;
  signal T_365 : std_logic;
  signal T_366 : std_logic;
  signal T_367 : std_logic;
  signal T_368 : std_logic;
  signal T_369 : std_logic;
  signal T_370 : std_logic;
  signal T_371 : std_logic;
  signal T_372 : std_logic;
  signal T_373 : std_logic;
  signal T_374 : std_logic;
  signal T_375 : std_logic;
  signal T_376 : std_logic;
  signal T_377 : std_logic;
  signal T_378 : std_logic;
  signal T_379 : std_logic;
  signal T_380 : std_logic;
  signal T_381 : std_logic;
  signal T_382 : std_logic;
  signal T_383 : std_logic;
  signal T_384 : std_logic;
  signal T_385 : std_logic;
  signal T_386 : std_logic;
  signal T_387 : std_logic;
  signal T_388 : std_logic;
  signal T_389 : std_logic;
  signal T_390 : std_logic;
  signal T_391 : std_logic;
  signal T_392 : std_logic;
  signal T_393 : std_logic;
  signal T_394 : std_logic;
  signal T_395 : std_logic;
  signal T_396 : std_logic;
  signal T_397 : std_logic;
  signal T_398 : std_logic;
  signal T_399 : std_logic;
  signal T_400 : std_logic;
  signal T_401 : std_logic;
  signal T_402 : std_logic;
  signal T_403 : std_logic;
  signal T_404 : std_logic;
  signal T_405 : std_logic;
  signal T_406 : std_logic;
  signal T_407 : std_logic;
  signal T_408 : std_logic;
  signal T_409 : std_logic;
  signal T_410 : std_logic;
  signal T_411 : std_logic;
  signal T_412 : std_logic;
  signal T_413 : std_logic;
  signal T_414 : std_logic;
  signal T_415 : std_logic;
  signal T_416 : std_logic;
  signal T_417 : std_logic;
  signal T_418 : std_logic;
  signal T_419 : std_logic;
  signal T_420 : std_logic;
  signal T_421 : std_logic;
  signal T_422 : std_logic;
  signal T_423 : std_logic;
  signal T_424 : std_logic;
  signal T_425 : std_logic;
  signal T_426 : std_logic;
  signal T_427 : std_logic;
  signal T_428 : std_logic;
  signal T_429 : std_logic;
  signal T_430 : std_logic;
  signal T_431 : std_logic;
  signal T_432 : std_logic;
  signal T_433 : std_logic;
  signal T_434 : std_logic;
  signal T_435 : std_logic;
  signal T_436 : std_logic;
  signal T_437 : std_logic;
  signal T_438 : std_logic;
  signal T_439 : std_logic;
  signal T_440 : std_logic;
  signal T_441 : std_logic;
  signal T_442 : std_logic;
  signal T_443 : std_logic;
  signal T_444 : std_logic;
  signal T_445 : std_logic;
  signal T_446 : std_logic;
  signal T_447 : std_logic;
  signal T_448 : std_logic;
  signal T_449 : std_logic;
  signal T_450 : std_logic;
  signal T_451 : std_logic;
  signal T_452 : std_logic;
  signal T_453 : std_logic;
  signal T_454 : std_logic;
  signal T_455 : std_logic;
  signal T_456 : std_logic;
  signal T_457 : std_logic;
  signal T_458 : std_logic;
  signal T_459 : std_logic;
  signal T_460 : std_logic;
  signal T_461 : std_logic;
  signal T_462 : std_logic;
  signal T_463 : std_logic;
  signal T_464 : std_logic;
  signal T_465 : std_logic;
  signal T_466 : std_logic;
  signal T_467 : std_logic;
  signal T_468 : std_logic;
  signal T_469 : std_logic;
  signal T_470 : std_logic;
  signal T_471 : std_logic;
  signal T_472 : std_logic;
  signal T_473 : std_logic;
  signal T_474 : std_logic;
  signal T_475 : std_logic;
  signal T_476 : std_logic;
  signal T_477 : std_logic;
  signal T_478 : std_logic;
  signal T_479 : std_logic;
  signal T_480 : std_logic;
  signal T_481 : std_logic;
  signal T_482 : std_logic;
  signal T_483 : std_logic;
  signal T_484 : std_logic;
  signal T_485 : std_logic;
  signal T_486 : std_logic;
  signal T_487 : std_logic;
  signal T_488 : std_logic;
  signal T_489 : std_logic;
  signal T_490 : std_logic;
  signal T_491 : std_logic;
  signal T_492 : std_logic;
  signal T_493 : std_logic;
  signal T_494 : std_logic;
  signal T_495 : std_logic;
  signal T_496 : std_logic;
  signal T_497 : std_logic;
  signal T_498 : std_logic;
  signal T_499 : std_logic;
  signal T_500 : std_logic;
  signal T_501 : std_logic;
  signal T_502 : std_logic;
  signal T_503 : std_logic;
  signal T_504 : std_logic;
  signal T_505 : std_logic;
  signal T_506 : std_logic;
  signal T_507 : std_logic;
  signal T_508 : std_logic;
  signal T_509 : std_logic;
  signal T_510 : std_logic;
  signal T_511 : std_logic;
  signal T_512 : std_logic;
  signal T_513 : std_logic;
  signal T_514 : std_logic;
  signal T_515 : std_logic;
  signal T_516 : std_logic;
  signal T_517 : std_logic;
  signal T_518 : std_logic;
  signal T_519 : std_logic;
  signal T_520 : std_logic;
  signal T_521 : std_logic;
  signal T_522 : std_logic;
  signal T_523 : std_logic;
  signal T_524 : std_logic;
  signal T_525 : std_logic;
  signal T_526 : std_logic;
  signal T_527 : std_logic;
  signal T_528 : std_logic;
  signal T_529 : std_logic;
  signal T_530 : std_logic;
  signal T_531 : std_logic;
  signal T_532 : std_logic;
  signal T_533 : std_logic;
  signal T_534 : std_logic;
  signal T_535 : std_logic;
  signal T_536 : std_logic;
  signal T_537 : std_logic;
  signal T_538 : std_logic;
  signal T_539 : std_logic;
  signal T_540 : std_logic;
  signal T_541 : std_logic;
  signal T_542 : std_logic;
  signal T_543 : std_logic;
  signal T_544 : std_logic;
  signal T_545 : std_logic;
  signal T_546 : std_logic;
  signal T_547 : std_logic;
  signal T_548 : std_logic;
  signal T_549 : std_logic;
  signal T_550 : std_logic;
  signal T_551 : std_logic;
  signal T_552 : std_logic;
  signal T_553 : std_logic;
  signal T_554 : std_logic;
  signal T_555 : std_logic;
  signal T_556 : std_logic;
  signal T_557 : std_logic;
  signal T_558 : std_logic;
  signal T_559 : std_logic;
  signal T_560 : std_logic;
  signal T_561 : std_logic;
  signal T_562 : std_logic;
  signal T_563 : std_logic;
  signal T_564 : std_logic;
  signal T_565 : std_logic;
  signal T_566 : std_logic;
  signal T_567 : std_logic;
  signal T_568 : std_logic;
  signal T_569 : std_logic;
  signal T_570 : std_logic;
  signal T_571 : std_logic;
  signal T_572 : std_logic;
  signal T_573 : std_logic;
  signal T_574 : std_logic;
  signal T_575 : std_logic;
  signal T_576 : std_logic;
  signal T_577 : std_logic;
  signal T_578 : std_logic;
  signal T_579 : std_logic;
  signal T_580 : std_logic;
  signal T_581 : std_logic;
  signal T_582 : std_logic;
  signal T_583 : std_logic;
  signal T_584 : std_logic;
  signal T_585 : std_logic;
  signal T_586 : std_logic;
  signal T_587 : std_logic;
  signal T_588 : std_logic;
  signal T_589 : std_logic;
  signal T_590 : std_logic;
  signal T_591 : std_logic;
  signal T_592 : std_logic;
  signal T_593 : std_logic;
  signal T_594 : std_logic;
  signal T_595 : std_logic;
  signal T_596 : std_logic;
  signal T_597 : std_logic;
  signal T_598 : std_logic;
  signal T_599 : std_logic;
  signal T_600 : std_logic;
  signal T_601 : std_logic;
  signal T_602 : std_logic;
  signal T_603 : std_logic;
  signal T_604 : std_logic;
  signal T_605 : std_logic;
  signal T_606 : std_logic;
  signal T_607 : std_logic;
  signal T_608 : std_logic;
  signal T_609 : std_logic;
  signal T_610 : std_logic;
  signal T_611 : std_logic;
  signal T_612 : std_logic;
  signal T_613 : std_logic;
  signal T_614 : std_logic;
  signal T_615 : std_logic;
  signal T_616 : std_logic;
  signal T_617 : std_logic;
  signal T_618 : std_logic;
  signal T_619 : std_logic;
  signal T_620 : std_logic;
  signal T_621 : std_logic;
  signal T_622 : std_logic;
  signal T_623 : std_logic;
  signal T_624 : std_logic;
  signal T_625 : std_logic;
  signal T_626 : std_logic;
  signal T_627 : std_logic;
  signal T_628 : std_logic;
  signal T_629 : std_logic;
  signal T_630 : std_logic;
  signal T_631 : std_logic;
  signal T_632 : std_logic;
  signal T_633 : std_logic;
  signal T_634 : std_logic;
  signal T_635 : std_logic;
  signal T_636 : std_logic;
  signal T_637 : std_logic;
  signal T_638 : std_logic;
  signal T_639 : std_logic;
  signal T_640 : std_logic;
  signal T_641 : std_logic;
  signal T_642 : std_logic;
  signal T_643 : std_logic;
  signal T_644 : std_logic;
  signal T_645 : std_logic;
  signal T_646 : std_logic;
  signal T_647 : std_logic;
  signal T_648 : std_logic;
  signal T_649 : std_logic;
  signal T_650 : std_logic;
  signal T_651 : std_logic;
  signal T_652 : std_logic;
  signal T_653 : std_logic;
  signal T_654 : std_logic;
  signal T_655 : std_logic;
  signal T_656 : std_logic;
  signal T_657 : std_logic;
  signal T_658 : std_logic;
  signal T_659 : std_logic;
  signal T_660 : std_logic;
  signal T_661 : std_logic;
  signal T_662 : std_logic;
  signal T_663 : std_logic;
  signal T_664 : std_logic;
  signal T_665 : std_logic;
  signal T_666 : std_logic;
  signal T_667 : std_logic;
  signal T_668 : std_logic;
  signal T_669 : std_logic;
  signal T_670 : std_logic;
  signal T_671 : std_logic;
  signal T_672 : std_logic;
  signal T_673 : std_logic;
  signal T_674 : std_logic;
  signal T_675 : std_logic;
  signal T_676 : std_logic;
  signal T_677 : std_logic;
  signal T_678 : std_logic;
  signal T_679 : std_logic;
  signal T_680 : std_logic;
  signal T_681 : std_logic;
  signal T_682 : std_logic;
  signal T_683 : std_logic;
  signal T_684 : std_logic;
  signal T_685 : std_logic;
  signal T_686 : std_logic;
  signal T_687 : std_logic;
  signal T_688 : std_logic;
  signal T_689 : std_logic;
  signal T_690 : std_logic;
  signal T_691 : std_logic;
  signal T_692 : std_logic;
  signal T_693 : std_logic;
  signal T_694 : std_logic;
  signal T_695 : std_logic;
  signal T_696 : std_logic;
  signal T_697 : std_logic;
  signal T_698 : std_logic;
  signal T_699 : std_logic;
  signal T_700 : std_logic;
  signal T_701 : std_logic;
  signal T_702 : std_logic;
  signal T_703 : std_logic;
  signal T_704 : std_logic;
  signal T_705 : std_logic;
  signal T_706 : std_logic;
  signal T_707 : std_logic;
  signal T_708 : std_logic;
  signal T_709 : std_logic;
  signal T_710 : std_logic;
  signal T_711 : std_logic;
  signal T_712 : std_logic;
  signal T_713 : std_logic;
  signal T_714 : std_logic;
  signal T_715 : std_logic;
  signal T_716 : std_logic;
  signal T_717 : std_logic;
  signal T_718 : std_logic;
  signal T_719 : std_logic;
  signal T_720 : std_logic;
  signal T_721 : std_logic;
  signal T_722 : std_logic;
  signal T_723 : std_logic;
  signal T_724 : std_logic;
  signal T_725 : std_logic;
  signal T_726 : std_logic;
  signal T_727 : std_logic;
  signal T_728 : std_logic;
  signal T_729 : std_logic;
  signal T_730 : std_logic;
  signal T_731 : std_logic;
  signal T_732 : std_logic;
  signal T_733 : std_logic;
  signal T_734 : std_logic;
  signal T_735 : std_logic;
  signal T_736 : std_logic;
  signal T_737 : std_logic;
  signal T_738 : std_logic;
  signal T_739 : std_logic;
  signal T_740 : std_logic;
  signal T_741 : std_logic;
  signal T_742 : std_logic;
  signal T_743 : std_logic;
  signal T_744 : std_logic;
  signal T_745 : std_logic;
  signal T_746 : std_logic;
  signal T_747 : std_logic;
  signal T_748 : std_logic;
  signal T_749 : std_logic;
  signal T_750 : std_logic;
  signal T_751 : std_logic;
  signal T_752 : std_logic;
  signal T_753 : std_logic;
  signal T_754 : std_logic;
  signal T_755 : std_logic;
  signal T_756 : std_logic;
  signal T_757 : std_logic;
  signal T_758 : std_logic;
  signal T_759 : std_logic;
  signal T_760 : std_logic;
  signal T_761 : std_logic;
  signal T_762 : std_logic;
  signal T_763 : std_logic;
  signal T_764 : std_logic;
  signal T_765 : std_logic;
  signal T_766 : std_logic;
  signal T_767 : std_logic;
  signal T_768 : std_logic;
  signal T_769 : std_logic;
  signal T_770 : std_logic;
  signal T_771 : std_logic;
  signal T_772 : std_logic;
  signal T_773 : std_logic;
  signal T_774 : std_logic;
  signal T_775 : std_logic;
  signal T_776 : std_logic;
  signal T_777 : std_logic;
  signal T_778 : std_logic;
  signal T_779 : std_logic;
  signal T_780 : std_logic;
  signal T_781 : std_logic;
  signal T_782 : std_logic;
  signal T_783 : std_logic;
  signal T_784 : std_logic;
  signal T_785 : std_logic;
  signal T_786 : std_logic;
  signal T_787 : std_logic;
  signal T_788 : std_logic;
  signal T_789 : std_logic;
  signal T_790 : std_logic;
  signal T_791 : std_logic;
  signal T_792 : std_logic;
  signal GND_net : std_logic;
  signal FF_ID_3_5_bus_T1 : std_logic;
  signal FF_ID_3_6_bus_T1 : std_logic;
  signal FF_ID_2_5_bus_T1 : std_logic;
  signal FF_ID_2_6_bus_T1 : std_logic;
  signal FF_ID_0_6_bus_T1 : std_logic;
  signal FF_ID_0_5_bus_T1 : std_logic;
  signal FF_ID_0_7_bus_T1 : std_logic;
  signal FF_ID_1_4_bus_T1 : std_logic;
  signal FF_ID_1_5_bus_T1 : std_logic;
  signal FF_ID_1_6_bus_T1 : std_logic;
  signal GATE_PRBSEN_B : std_logic;
  signal GATE_PRBSEN_A : std_logic;
  signal GATE_T_0_A : std_logic;
  signal GATE_T_1_A : std_logic;
  signal GATE_T_2_A : std_logic;
  signal GATE_T_3_DN : std_logic;
  signal GATE_SCL_OE_A : std_logic;
  signal GATE_SDA_OE_A : std_logic;
  signal GATE_TXD_11X_D_X2_DN : std_logic;
  signal GATE_TXD_7X_D_X2_DN : std_logic;
  signal GATE_ni_nires_reg_data3pos_0_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1pos_0_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3pos_2_bus_CE_A : std_logic;
  signal GATE_nx2272_X2_A : std_logic;
  signal GATE_ni_nires_reg_data1pos_2_bus_CE_A : std_logic;
  signal GATE_nx1271_B : std_logic;
  signal GATE_nx1271_A : std_logic;
  signal GATE_ni_nires_reg_data3pos_3_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1pos_3_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3pos_4_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1pos_4_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3pos_5_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1pos_5_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3pos_6_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1pos_6_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg1hm_2_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg1hm_2_bus_CE_B : std_logic;
  signal GATE_ni_nires_reg_data3pos_7_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1pos_7_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3pos_8_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1pos_8_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg1hm_6_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg1hm_6_bus_CE_B : std_logic;
  signal GATE_j2c_reg_creg1hm_5_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg1hm_5_bus_CE_B : std_logic;
  signal GATE_j2c_reg_creg1hm_4_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg1hm_4_bus_CE_B : std_logic;
  signal GATE_j2c_reg_creg1hm_3_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg1hm_3_bus_CE_B : std_logic;
  signal GATE_ni_nires_reg_data3pos_9_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1pos_9_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg1hm_1_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg1hm_1_bus_CE_B : std_logic;
  signal GATE_j2c_reg_creg1hm_0_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg1hm_0_bus_CE_B : std_logic;
  signal GATE_ni_reg_ce_prty_bit_neg_D_X2_A : std_logic;
  signal GATE_ni_nires_reg_data3neg_1_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1neg_1_bus_CE_A : std_logic;
  signal GATE_nx1815_X2_A : std_logic;
  signal GATE_ni_nires_reg_data3neg_0_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1neg_0_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg0hm_4_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg0hm_4_bus_CE_B : std_logic;
  signal GATE_j2c_reg_creg0hm_6_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg0hm_6_bus_CE_B : std_logic;
  signal GATE_j2c_reg_creg0hm_5_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg0hm_5_bus_CE_B : std_logic;
  signal GATE_j2c_reg_creg0hm_2_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg0hm_2_bus_CE_B : std_logic;
  signal GATE_j2c_reg_creg0hm_1_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg0hm_1_bus_CE_B : std_logic;
  signal GATE_j2c_reg_creg0hm_3_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg0hm_3_bus_CE_B : std_logic;
  signal GATE_j2c_reg_creg0hm_0_bus_CE_A : std_logic;
  signal GATE_j2c_reg_creg0hm_0_bus_CE_B : std_logic;
  signal GATE_ni_nires_reg_data3neg_2_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1neg_2_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3neg_3_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1neg_3_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3neg_4_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1neg_4_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3neg_5_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1neg_5_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3neg_6_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1neg_6_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3neg_7_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1neg_7_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3neg_8_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1neg_8_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3neg_9_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1neg_9_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data3pos_1_bus_CE_A : std_logic;
  signal GATE_ni_nires_reg_data1pos_1_bus_CE_A : std_logic;
  signal GATE_ID_3_5_X0_A : std_logic;
  signal GATE_ID_2_5_X0_A : std_logic;
  signal GATE_ix47_Y : std_logic;
  signal GATE_ix59_Y : std_logic;
  signal GATE_ix71_Y : std_logic;
  signal GATE_ix1641_Y : std_logic;
  signal GATE_ix1647_Y : std_logic;
  signal GATE_ix1771_Y : std_logic;
  signal GATE_ix373_Y : std_logic;
  signal GATE_ix385_Y : std_logic;
  signal GATE_ix397_Y : std_logic;
  signal GATE_T_7_DN : std_logic;
  signal GATE_T_8_A : std_logic;
  signal GATE_T_9_A : std_logic;
  signal GATE_T_10_A : std_logic;
  signal GATE_T_12_A : std_logic;
  signal GATE_T_13_A : std_logic;
  signal GATE_T_14_A : std_logic;
  signal GATE_T_15_DN : std_logic;
  signal GATE_T_16_B : std_logic;
  signal GATE_T_16_A : std_logic;
  signal GATE_T_17_A : std_logic;
  signal GATE_T_18_B : std_logic;
  signal GATE_T_18_A : std_logic;
  signal GATE_T_21_DN : std_logic;
  signal GATE_T_22_DN : std_logic;
  signal GATE_T_23_B : std_logic;
  signal GATE_T_23_A : std_logic;
  signal GATE_T_24_A : std_logic;
  signal GATE_T_24_B : std_logic;
  signal GATE_T_26_DN : std_logic;
  signal GATE_T_27_B : std_logic;
  signal GATE_T_27_A : std_logic;
  signal GATE_T_28_B : std_logic;
  signal GATE_T_28_A : std_logic;
  signal GATE_T_29_A : std_logic;
  signal GATE_T_32_DN : std_logic;
  signal GATE_T_33_DN : std_logic;
  signal GATE_T_34_B : std_logic;
  signal GATE_T_34_A : std_logic;
  signal GATE_T_35_A : std_logic;
  signal GATE_T_35_B : std_logic;
  signal GATE_T_37_A : std_logic;
  signal GATE_T_38_A : std_logic;
  signal GATE_T_39_A : std_logic;
  signal GATE_T_39_B : std_logic;
  signal GATE_T_42_A : std_logic;
  signal GATE_T_42_B : std_logic;
  signal GATE_T_43_A : std_logic;
  signal GATE_T_44_A : std_logic;
  signal GATE_T_46_A : std_logic;
  signal GATE_T_46_B : std_logic;
  signal GATE_T_47_A : std_logic;
  signal GATE_T_48_A : std_logic;
  signal GATE_T_50_A : std_logic;
  signal GATE_T_50_B : std_logic;
  signal GATE_T_51_A : std_logic;
  signal GATE_T_52_A : std_logic;
  signal GATE_T_54_A : std_logic;
  signal GATE_T_54_B : std_logic;
  signal GATE_T_55_A : std_logic;
  signal GATE_T_56_A : std_logic;
  signal GATE_T_58_A : std_logic;
  signal GATE_T_58_B : std_logic;
  signal GATE_T_59_A : std_logic;
  signal GATE_T_60_A : std_logic;
  signal GATE_T_62_A : std_logic;
  signal GATE_T_62_B : std_logic;
  signal GATE_T_63_A : std_logic;
  signal GATE_T_64_A : std_logic;
  signal GATE_T_66_A : std_logic;
  signal GATE_T_66_B : std_logic;
  signal GATE_T_67_A : std_logic;
  signal GATE_T_68_A : std_logic;
  signal GATE_T_69_A : std_logic;
  signal GATE_T_70_A : std_logic;
  signal GATE_T_71_A : std_logic;
  signal GATE_T_73_A : std_logic;
  signal GATE_T_73_B : std_logic;
  signal GATE_T_74_A : std_logic;
  signal GATE_T_75_A : std_logic;
  signal GATE_T_76_A : std_logic;
  signal GATE_T_77_A : std_logic;
  signal GATE_T_78_A : std_logic;
  signal GATE_T_79_A : std_logic;
  signal GATE_T_80_A : std_logic;
  signal GATE_T_80_B : std_logic;
  signal GATE_T_81_A : std_logic;
  signal GATE_T_81_B : std_logic;
  signal GATE_T_82_A : std_logic;
  signal GATE_T_82_B : std_logic;
  signal GATE_T_84_A : std_logic;
  signal GATE_T_84_B : std_logic;
  signal GATE_T_85_A : std_logic;
  signal GATE_T_85_B : std_logic;
  signal GATE_T_86_A : std_logic;
  signal GATE_T_86_B : std_logic;
  signal GATE_T_88_A : std_logic;
  signal GATE_T_89_A : std_logic;
  signal GATE_T_90_A : std_logic;
  signal GATE_T_91_A : std_logic;
  signal GATE_T_92_A : std_logic;
  signal GATE_T_93_A : std_logic;
  signal GATE_T_94_A : std_logic;
  signal GATE_T_95_A : std_logic;
  signal GATE_T_95_B : std_logic;
  signal GATE_T_96_A : std_logic;
  signal GATE_T_96_B : std_logic;
  signal GATE_T_97_A : std_logic;
  signal GATE_T_97_B : std_logic;
  signal GATE_T_100_A : std_logic;
  signal GATE_T_100_B : std_logic;
  signal GATE_T_101_A : std_logic;
  signal GATE_T_102_A : std_logic;
  signal GATE_T_103_A : std_logic;
  signal GATE_T_104_A : std_logic;
  signal GATE_T_105_A : std_logic;
  signal GATE_T_106_A : std_logic;
  signal GATE_T_107_A : std_logic;
  signal GATE_T_108_A : std_logic;
  signal GATE_T_109_A : std_logic;
  signal GATE_T_111_A : std_logic;
  signal GATE_T_111_B : std_logic;
  signal GATE_T_112_A : std_logic;
  signal GATE_T_113_A : std_logic;
  signal GATE_T_114_A : std_logic;
  signal GATE_T_115_A : std_logic;
  signal GATE_T_116_A : std_logic;
  signal GATE_T_117_A : std_logic;
  signal GATE_T_119_A : std_logic;
  signal GATE_T_122_A : std_logic;
  signal GATE_T_123_A : std_logic;
  signal GATE_T_126_A : std_logic;
  signal GATE_T_127_A : std_logic;
  signal GATE_T_128_A : std_logic;
  signal GATE_T_129_A : std_logic;
  signal GATE_T_129_B : std_logic;
  signal GATE_T_130_A : std_logic;
  signal GATE_T_131_DN : std_logic;
  signal GATE_T_132_B : std_logic;
  signal GATE_T_132_A : std_logic;
  signal GATE_T_133_A : std_logic;
  signal GATE_T_133_B : std_logic;
  signal GATE_T_134_A : std_logic;
  signal GATE_T_134_B : std_logic;
  signal GATE_T_135_A : std_logic;
  signal GATE_T_137_A : std_logic;
  signal GATE_T_138_A : std_logic;
  signal GATE_T_139_A : std_logic;
  signal GATE_T_140_B : std_logic;
  signal GATE_T_140_A : std_logic;
  signal GATE_T_142_A : std_logic;
  signal GATE_T_143_A : std_logic;
  signal GATE_T_144_A : std_logic;
  signal GATE_T_145_A : std_logic;
  signal GATE_T_146_A : std_logic;
  signal GATE_T_147_A : std_logic;
  signal GATE_T_148_A : std_logic;
  signal GATE_T_149_A : std_logic;
  signal GATE_T_150_A : std_logic;
  signal GATE_T_151_A : std_logic;
  signal GATE_T_152_A : std_logic;
  signal GATE_T_153_A : std_logic;
  signal GATE_T_154_A : std_logic;
  signal GATE_T_155_A : std_logic;
  signal GATE_T_156_A : std_logic;
  signal GATE_T_157_A : std_logic;
  signal GATE_T_158_A : std_logic;
  signal GATE_T_159_A : std_logic;
  signal GATE_T_161_A : std_logic;
  signal GATE_T_162_A : std_logic;
  signal GATE_T_164_A : std_logic;
  signal GATE_T_168_A : std_logic;
  signal GATE_T_169_A : std_logic;
  signal GATE_T_170_A : std_logic;
  signal GATE_T_171_A : std_logic;
  signal GATE_T_172_A : std_logic;
  signal GATE_T_172_B : std_logic;
  signal GATE_T_173_DN : std_logic;
  signal GATE_T_174_B : std_logic;
  signal GATE_T_174_A : std_logic;
  signal GATE_T_175_A : std_logic;
  signal GATE_T_175_B : std_logic;
  signal GATE_T_176_A : std_logic;
  signal GATE_T_176_B : std_logic;
  signal GATE_T_177_A : std_logic;
  signal GATE_T_179_B : std_logic;
  signal GATE_T_179_A : std_logic;
  signal GATE_T_180_B : std_logic;
  signal GATE_T_180_A : std_logic;
  signal GATE_T_181_B : std_logic;
  signal GATE_T_181_A : std_logic;
  signal GATE_T_184_A : std_logic;
  signal GATE_T_185_A : std_logic;
  signal GATE_T_186_A : std_logic;
  signal GATE_T_188_A : std_logic;
  signal GATE_T_189_A : std_logic;
  signal GATE_T_190_A : std_logic;
  signal GATE_T_192_A : std_logic;
  signal GATE_T_192_B : std_logic;
  signal GATE_T_193_A : std_logic;
  signal GATE_T_193_B : std_logic;
  signal GATE_T_194_A : std_logic;
  signal GATE_T_194_B : std_logic;
  signal GATE_T_196_A : std_logic;
  signal GATE_T_196_B : std_logic;
  signal GATE_T_197_A : std_logic;
  signal GATE_T_197_B : std_logic;
  signal GATE_T_198_A : std_logic;
  signal GATE_T_198_B : std_logic;
  signal GATE_T_200_A : std_logic;
  signal GATE_T_200_B : std_logic;
  signal GATE_T_201_A : std_logic;
  signal GATE_T_202_A : std_logic;
  signal GATE_T_204_A : std_logic;
  signal GATE_T_204_B : std_logic;
  signal GATE_T_205_A : std_logic;
  signal GATE_T_205_B : std_logic;
  signal GATE_T_206_A : std_logic;
  signal GATE_T_206_B : std_logic;
  signal GATE_T_208_A : std_logic;
  signal GATE_T_208_B : std_logic;
  signal GATE_T_209_A : std_logic;
  signal GATE_T_210_A : std_logic;
  signal GATE_T_212_A : std_logic;
  signal GATE_T_212_B : std_logic;
  signal GATE_T_213_A : std_logic;
  signal GATE_T_214_A : std_logic;
  signal GATE_T_216_A : std_logic;
  signal GATE_T_216_B : std_logic;
  signal GATE_T_217_A : std_logic;
  signal GATE_T_218_A : std_logic;
  signal GATE_T_220_A : std_logic;
  signal GATE_T_220_B : std_logic;
  signal GATE_T_221_A : std_logic;
  signal GATE_T_222_A : std_logic;
  signal GATE_T_224_A : std_logic;
  signal GATE_T_224_B : std_logic;
  signal GATE_T_225_A : std_logic;
  signal GATE_T_226_A : std_logic;
  signal GATE_T_228_A : std_logic;
  signal GATE_T_228_B : std_logic;
  signal GATE_T_229_A : std_logic;
  signal GATE_T_230_A : std_logic;
  signal GATE_T_232_A : std_logic;
  signal GATE_T_232_B : std_logic;
  signal GATE_T_233_A : std_logic;
  signal GATE_T_234_A : std_logic;
  signal GATE_T_236_A : std_logic;
  signal GATE_T_236_B : std_logic;
  signal GATE_T_237_A : std_logic;
  signal GATE_T_238_A : std_logic;
  signal GATE_T_242_A : std_logic;
  signal GATE_T_242_B : std_logic;
  signal GATE_T_244_A : std_logic;
  signal GATE_T_245_A : std_logic;
  signal GATE_T_246_DN : std_logic;
  signal GATE_T_247_A : std_logic;
  signal GATE_T_247_B : std_logic;
  signal GATE_T_248_A : std_logic;
  signal GATE_T_255_A : std_logic;
  signal GATE_T_257_A : std_logic;
  signal GATE_T_259_DN : std_logic;
  signal GATE_T_260_DN : std_logic;
  signal GATE_T_261_DN : std_logic;
  signal GATE_T_262_DN : std_logic;
  signal GATE_T_263_A : std_logic;
  signal GATE_T_264_A : std_logic;
  signal GATE_T_266_DN : std_logic;
  signal GATE_T_267_DN : std_logic;
  signal GATE_T_268_B : std_logic;
  signal GATE_T_268_A : std_logic;
  signal GATE_T_269_B : std_logic;
  signal GATE_T_269_A : std_logic;
  signal GATE_T_270_A : std_logic;
  signal GATE_T_270_B : std_logic;
  signal GATE_T_274_A : std_logic;
  signal GATE_T_275_A : std_logic;
  signal GATE_T_276_A : std_logic;
  signal GATE_T_277_A : std_logic;
  signal GATE_T_278_A : std_logic;
  signal GATE_T_280_DN : std_logic;
  signal GATE_T_281_B : std_logic;
  signal GATE_T_281_A : std_logic;
  signal GATE_T_282_DN : std_logic;
  signal GATE_T_285_B : std_logic;
  signal GATE_T_285_A : std_logic;
  signal GATE_T_287_A : std_logic;
  signal GATE_T_287_B : std_logic;
  signal GATE_T_289_A : std_logic;
  signal GATE_T_290_A : std_logic;
  signal GATE_T_292_A : std_logic;
  signal GATE_T_297_A : std_logic;
  signal GATE_T_298_A : std_logic;
  signal GATE_T_299_A : std_logic;
  signal GATE_T_300_A : std_logic;
  signal GATE_T_301_A : std_logic;
  signal GATE_T_303_A : std_logic;
  signal GATE_T_304_A : std_logic;
  signal GATE_T_306_A : std_logic;
  signal GATE_T_307_A : std_logic;
  signal GATE_T_308_A : std_logic;
  signal GATE_T_308_B : std_logic;
  signal GATE_T_309_A : std_logic;
  signal GATE_T_311_A : std_logic;
  signal GATE_T_312_A : std_logic;
  signal GATE_T_321_A : std_logic;
  signal GATE_T_323_A : std_logic;
  signal GATE_T_324_DN : std_logic;
  signal GATE_T_325_DN : std_logic;
  signal GATE_T_326_DN : std_logic;
  signal GATE_T_327_DN : std_logic;
  signal GATE_T_328_A : std_logic;
  signal GATE_T_330_A : std_logic;
  signal GATE_T_331_B : std_logic;
  signal GATE_T_331_A : std_logic;
  signal GATE_T_332_B : std_logic;
  signal GATE_T_332_A : std_logic;
  signal GATE_T_333_DN : std_logic;
  signal GATE_T_334_DN : std_logic;
  signal GATE_T_335_A : std_logic;
  signal GATE_T_336_A : std_logic;
  signal GATE_T_339_A : std_logic;
  signal GATE_T_340_A : std_logic;
  signal GATE_T_341_A : std_logic;
  signal GATE_T_342_A : std_logic;
  signal GATE_T_344_A : std_logic;
  signal GATE_T_345_B : std_logic;
  signal GATE_T_345_A : std_logic;
  signal GATE_T_346_DN : std_logic;
  signal GATE_T_347_A : std_logic;
  signal GATE_T_348_A : std_logic;
  signal GATE_T_349_A : std_logic;
  signal GATE_T_352_A : std_logic;
  signal GATE_T_355_B : std_logic;
  signal GATE_T_355_A : std_logic;
  signal GATE_T_357_A : std_logic;
  signal GATE_T_357_B : std_logic;
  signal GATE_T_358_A : std_logic;
  signal GATE_T_360_A : std_logic;
  signal GATE_T_361_A : std_logic;
  signal GATE_T_363_A : std_logic;
  signal GATE_T_365_A : std_logic;
  signal GATE_T_368_A : std_logic;
  signal GATE_T_373_A : std_logic;
  signal GATE_T_380_DN : std_logic;
  signal GATE_T_381_B : std_logic;
  signal GATE_T_381_A : std_logic;
  signal GATE_T_382_DN : std_logic;
  signal GATE_T_383_B : std_logic;
  signal GATE_T_383_A : std_logic;
  signal GATE_T_384_A : std_logic;
  signal GATE_T_392_A : std_logic;
  signal GATE_T_393_A : std_logic;
  signal GATE_T_394_A : std_logic;
  signal GATE_T_395_A : std_logic;
  signal GATE_T_404_A : std_logic;
  signal GATE_T_405_A : std_logic;
  signal GATE_T_408_A : std_logic;
  signal GATE_T_411_A : std_logic;
  signal GATE_T_412_A : std_logic;
  signal GATE_T_414_A : std_logic;
  signal GATE_T_417_A : std_logic;
  signal GATE_T_418_A : std_logic;
  signal GATE_T_419_A : std_logic;
  signal GATE_T_421_A : std_logic;
  signal GATE_T_422_A : std_logic;
  signal GATE_T_423_A : std_logic;
  signal GATE_T_425_A : std_logic;
  signal GATE_T_426_A : std_logic;
  signal GATE_T_427_A : std_logic;
  signal GATE_T_428_A : std_logic;
  signal GATE_T_429_A : std_logic;
  signal GATE_T_430_A : std_logic;
  signal GATE_T_431_A : std_logic;
  signal GATE_T_432_A : std_logic;
  signal GATE_T_433_A : std_logic;
  signal GATE_T_434_A : std_logic;
  signal GATE_T_435_A : std_logic;
  signal GATE_T_436_A : std_logic;
  signal GATE_T_437_A : std_logic;
  signal GATE_T_438_A : std_logic;
  signal GATE_T_439_A : std_logic;
  signal GATE_T_440_A : std_logic;
  signal GATE_T_441_A : std_logic;
  signal GATE_T_442_A : std_logic;
  signal GATE_T_444_DN : std_logic;
  signal GATE_T_445_DN : std_logic;
  signal GATE_T_446_DN : std_logic;
  signal GATE_T_447_A : std_logic;
  signal GATE_T_449_A : std_logic;
  signal GATE_T_455_A : std_logic;
  signal GATE_T_456_A : std_logic;
  signal GATE_T_459_A : std_logic;
  signal GATE_T_462_A : std_logic;
  signal GATE_T_464_A : std_logic;
  signal GATE_T_465_A : std_logic;
  signal GATE_T_466_A : std_logic;
  signal GATE_T_468_A : std_logic;
  signal GATE_T_469_A : std_logic;
  signal GATE_T_470_A : std_logic;
  signal GATE_T_472_A : std_logic;
  signal GATE_T_473_A : std_logic;
  signal GATE_T_474_A : std_logic;
  signal GATE_T_482_A : std_logic;
  signal GATE_T_490_A : std_logic;
  signal GATE_T_519_A : std_logic;
  signal GATE_T_521_A : std_logic;
  signal GATE_T_523_A : std_logic;
  signal GATE_T_525_A : std_logic;
  signal GATE_T_526_A : std_logic;
  signal GATE_T_527_A : std_logic;
  signal GATE_T_528_A : std_logic;
  signal GATE_T_531_A : std_logic;
  signal GATE_T_532_A : std_logic;
  signal GATE_T_534_A : std_logic;
  signal GATE_T_535_A : std_logic;
  signal GATE_T_549_A : std_logic;
  signal GATE_T_550_A : std_logic;
  signal GATE_T_553_A : std_logic;
  signal GATE_T_555_A : std_logic;
  signal GATE_T_557_A : std_logic;
  signal GATE_T_559_A : std_logic;
  signal GATE_T_560_A : std_logic;
  signal GATE_T_561_A : std_logic;
  signal GATE_T_562_A : std_logic;
  signal GATE_T_564_A : std_logic;
  signal GATE_T_565_A : std_logic;
  signal GATE_T_578_A : std_logic;
  signal GATE_T_580_A : std_logic;
  signal GATE_T_581_A : std_logic;
  signal GATE_T_583_A : std_logic;
  signal GATE_T_588_A : std_logic;
  signal GATE_T_589_A : std_logic;
  signal GATE_T_591_A : std_logic;
  signal GATE_T_592_A : std_logic;
  signal GATE_T_593_A : std_logic;
  signal GATE_T_600_A : std_logic;
  signal GATE_T_602_A : std_logic;
  signal GATE_T_607_A : std_logic;
  signal GATE_T_609_A : std_logic;
  signal GATE_T_611_A : std_logic;
  signal GATE_T_613_A : std_logic;
  signal GATE_T_615_A : std_logic;
  signal GATE_T_617_A : std_logic;
  signal GATE_T_620_A : std_logic;
  signal GATE_T_623_A : std_logic;
  signal GATE_T_635_A : std_logic;
  signal GATE_T_637_A : std_logic;
  signal GATE_T_638_A : std_logic;
  signal GATE_T_640_A : std_logic;
  signal GATE_T_641_A : std_logic;
  signal GATE_T_647_A : std_logic;
  signal GATE_T_649_A : std_logic;
  signal GATE_T_650_A : std_logic;
  signal GATE_T_651_A : std_logic;
  signal GATE_T_654_A : std_logic;
  signal GATE_T_660_A : std_logic;
  signal GATE_T_662_A : std_logic;
  signal GATE_T_667_A : std_logic;
  signal GATE_T_669_A : std_logic;
  signal GATE_T_671_A : std_logic;
  signal GATE_T_673_A : std_logic;
  signal GATE_T_675_A : std_logic;
  signal GATE_T_677_A : std_logic;
  signal GATE_T_680_A : std_logic;
  signal GATE_T_683_A : std_logic;
  signal GATE_T_697_A : std_logic;
  signal GATE_T_698_A : std_logic;
  signal GATE_T_699_A : std_logic;
  signal GATE_T_700_A : std_logic;
  signal GATE_T_701_A : std_logic;
  signal GATE_T_703_A : std_logic;
  signal GATE_T_706_A : std_logic;
  signal GATE_T_708_A : std_logic;
  signal GATE_T_713_A : std_logic;
  signal GATE_T_717_A : std_logic;
  signal GATE_T_718_A : std_logic;
  signal GATE_T_719_A : std_logic;
  signal GATE_T_720_A : std_logic;
  signal GATE_T_721_A : std_logic;
  signal GATE_T_723_A : std_logic;
  signal GATE_T_724_A : std_logic;
  signal GATE_T_726_A : std_logic;
  signal GATE_T_732_A : std_logic;
  signal GATE_T_734_A : std_logic;
  signal GATE_T_740_A : std_logic;
  signal GATE_T_742_A : std_logic;
  signal GATE_T_746_A : std_logic;
  signal GATE_T_747_A : std_logic;
  signal GATE_T_748_A : std_logic;
  signal GATE_T_749_A : std_logic;
  signal GATE_T_751_A : std_logic;
  signal GATE_T_754_A : std_logic;
  signal GATE_T_756_A : std_logic;
  signal GATE_T_760_A : std_logic;
  signal GATE_T_761_A : std_logic;
  signal GATE_T_763_A : std_logic;
  signal GATE_T_764_A : std_logic;
  signal GATE_T_767_A : std_logic;
  signal GATE_T_768_A : std_logic;
  signal GATE_T_769_A : std_logic;
  signal GATE_T_770_A : std_logic;
  signal GATE_T_771_A : std_logic;
  signal GATE_T_773_A : std_logic;
  signal GATE_T_775_A : std_logic;
  signal GATE_T_776_A : std_logic;
  signal GATE_T_779_A : std_logic;
  signal GATE_T_781_A : std_logic;
  signal GATE_T_782_A : std_logic;
  signal GATE_T_783_A : std_logic;
  signal GATE_T_784_A : std_logic;
  signal GATE_T_785_A : std_logic;
  signal GATE_T_787_A : std_logic;
  signal GATE_T_788_A : std_logic;
  signal GATE_T_792_A : std_logic;

begin
  GND_I_I_1:   GND port map ( X=>GND_net );
  IN_NI_D_9_XI_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>NI_D_9XPIN, 
            I0=>NI_D(9) );
  IN_NI_STR_I_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>NI_STRPIN, 
            I0=>NI_STR );
  IN_reset_n_I_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>reset_nPIN, 
            I0=>reset_n );
  IN_clk_I_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>clkPIN, 
            I0=>clk );
  OUT_TESTEN_I_1:   OBUF port map ( O=>TESTEN, 
            I0=>GND_net );
  OUT_PRBSEN_I_1:   OBUF port map ( O=>PRBSEN, 
            I0=>PRBSENCOM );
  OUT_LCKREFN_I_1:   OBUF port map ( O=>LCKREFN, 
            I0=>GND_net );
  OUT_ENABLE_I_1:   OBUF port map ( O=>ENABLE, 
            I0=>ENABLECOM );
  OUT_LOOPEN_I_1:   OBUF port map ( O=>LOOPEN, 
            I0=>GND_net );
  OUT_TX_ER_I_1:   OBUF port map ( O=>TX_ER, 
            I0=>GND_net );
  IN_DIS_JTG_I_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>DIS_JTGPIN, 
            I0=>DIS_JTG );
  IN_FAULT_I_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>FAULTPIN, 
            I0=>FAULT );
  OUT_EN_I_1:   OBUF port map ( O=>EN, 
            I0=>ENCOM );
  OUT_SD2ANL_I_1:   OBUF port map ( O=>SD2ANL, 
            I0=>SD2ANLCOM );
  OUT_WP_EEP_I_1:   OBUF port map ( O=>WP_EEP, 
            I0=>WP_EEPCOM );
  OUT_SCL_I_1:   BUFTH port map ( I0=>GND_net, 
            O=>SCL, 
            OE=>SCL_OE );
  OUT_SDA_I_1:   BI_DIR
 generic map( PULL => "Up")
 port map ( O=>SDAPIN, 
            I0=>GND_net, 
            IO=>SDA, 
            OE=>SDA_OE );
  IN_jTCK_I_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>jTCKPIN, 
            I0=>jTCK );
  IN_jTDI_I_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>jTDIPIN, 
            I0=>jTDI );
  OUT_jTDO_I_1:   BUFTH port map ( I0=>jTDOCOM, 
            O=>jTDO, 
            OE=>jTDO_OE );
  IN_jTMS_I_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>jTMSPIN, 
            I0=>jTMS );
  IN_NI_D_8_XI_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>NI_D_8XPIN, 
            I0=>NI_D(8) );
  IN_NI_D_7_XI_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>NI_D_7XPIN, 
            I0=>NI_D(7) );
  IN_NI_D_6_XI_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>NI_D_6XPIN, 
            I0=>NI_D(6) );
  IN_NI_D_5_XI_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>NI_D_5XPIN, 
            I0=>NI_D(5) );
  IN_NI_D_4_XI_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>NI_D_4XPIN, 
            I0=>NI_D(4) );
  IN_NI_D_3_XI_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>NI_D_3XPIN, 
            I0=>NI_D(3) );
  IN_NI_D_2_XI_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>NI_D_2XPIN, 
            I0=>NI_D(2) );
  IN_NI_D_1_XI_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>NI_D_1XPIN, 
            I0=>NI_D(1) );
  IN_NI_D_0_XI_1:   IBUF
 generic map( PULL => "Up")
 port map ( O=>NI_D_0XPIN, 
            I0=>NI_D(0) );
  OUT_TXD_4_XI_1:   OBUF port map ( O=>TXD(4), 
            I0=>TXD_4XQ );
  OUT_TXD_3_XI_1:   OBUF port map ( O=>TXD(3), 
            I0=>TXD_3XQ );
  OUT_TXD_2_XI_1:   OBUF port map ( O=>TXD(2), 
            I0=>TXD_2XQ );
  OUT_TXD_1_XI_1:   OBUF port map ( O=>TXD(1), 
            I0=>TXD_1XQ );
  OUT_TXD_0_XI_1:   OBUF port map ( O=>TXD(0), 
            I0=>TXD_0XQ );
  OUT_TX_EN_I_1:   OBUF port map ( O=>TX_EN, 
            I0=>TX_ENQ );
  OUT_TXD_15_XI_1:   OBUF port map ( O=>TXD(15), 
            I0=>TXD_15XQ );
  OUT_TXD_14_XI_1:   OBUF port map ( O=>TXD(14), 
            I0=>TXD_14XQ );
  OUT_TXD_13_XI_1:   OBUF port map ( O=>TXD(13), 
            I0=>TXD_13XQ );
  OUT_TXD_12_XI_1:   OBUF port map ( O=>TXD(12), 
            I0=>TXD_12XQ );
  OUT_TXD_11_XI_1:   OBUF port map ( O=>TXD(11), 
            I0=>TXD_11XQ );
  OUT_TXD_10_XI_1:   OBUF port map ( O=>TXD(10), 
            I0=>TXD_10XQ );
  OUT_TXD_9_XI_1:   OBUF port map ( O=>TXD(9), 
            I0=>TXD_9XQ );
  OUT_TXD_8_XI_1:   OBUF port map ( O=>TXD(8), 
            I0=>TXD_8XQ );
  OUT_TXD_7_XI_1:   OBUF port map ( O=>TXD(7), 
            I0=>TXD_7XQ );
  OUT_TXD_6_XI_1:   OBUF port map ( O=>TXD(6), 
            I0=>TXD_6XQ );
  OUT_TXD_5_XI_1:   OBUF port map ( O=>TXD(5), 
            I0=>TXD_5XQ );
  FF_TXD_4_XI_1:   DFFC port map ( D=>TXD_4X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_4XQ, 
            CLK=>clkPIN );
  FF_TXD_3_XI_1:   DFFC port map ( D=>TXD_3X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_3XQ, 
            CLK=>clkPIN );
  FF_TXD_2_XI_1:   DFFC port map ( D=>TXD_2X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_2XQ, 
            CLK=>clkPIN );
  FF_TXD_1_XI_1:   DFFC port map ( D=>TXD_1X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_1XQ, 
            CLK=>clkPIN );
  FF_TXD_0_XI_1:   DFFC port map ( D=>TXD_0X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_0XQ, 
            CLK=>clkPIN );
  FF_TX_EN_I_1:   DFF port map ( D=>TX_EN_D, 
            Q=>TX_ENQ, 
            CLK=>clkPIN );
  FF_TXD_15_XI_1:   DFFC port map ( D=>TXD_15X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_15XQ, 
            CLK=>clkPIN );
  FF_TXD_14_XI_1:   DFFC port map ( D=>TXD_14X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_14XQ, 
            CLK=>clkPIN );
  FF_TXD_13_XI_1:   DFFC port map ( D=>TXD_13X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_13XQ, 
            CLK=>clkPIN );
  FF_TXD_12_XI_1:   DFFC port map ( D=>TXD_12X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_12XQ, 
            CLK=>clkPIN );
  FF_TXD_11_XI_1:   DFFC port map ( D=>TXD_11X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_11XQ, 
            CLK=>clkPIN );
  FF_TXD_10_XI_1:   DFFC port map ( D=>TXD_10X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_10XQ, 
            CLK=>clkPIN );
  FF_TXD_9_XI_1:   DFFC port map ( D=>TXD_9X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_9XQ, 
            CLK=>clkPIN );
  FF_TXD_8_XI_1:   DFFC port map ( D=>TXD_8X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_8XQ, 
            CLK=>clkPIN );
  FF_TXD_7_XI_1:   DFFC port map ( D=>TXD_7X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_7XQ, 
            CLK=>clkPIN );
  FF_TXD_6_XI_1:   DFFC port map ( D=>TXD_6X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_6XQ, 
            CLK=>clkPIN );
  FF_TXD_5_XI_1:   DFFC port map ( D=>TXD_5X_D, 
            CE=>TXD_4X_CE, 
            Q=>TXD_5XQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data0pos_1_bus_I_1:   DFFC port map ( D=>NI_D_1XPIN, 
            CE=>ni_nires_reg_data0pos_1_bus_CE, 
            Q=>ni_nires_reg_data0pos_1_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data2pos_1_bus_I_1:   DFFC port map ( D=>NI_D_1XPIN, 
            CE=>ni_nires_reg_data2pos_1_bus_CE, 
            Q=>ni_nires_reg_data2pos_1_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data_out_10_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_10_bus_D, 
            Q=>ni_nires_reg_data_out_10_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3pos_0_bus_I_1:   DFFC port map ( D=>NI_D_0XPIN, 
            CE=>ni_nires_reg_data3pos_0_bus_CE, 
            Q=>ni_nires_reg_data3pos_0_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data1pos_0_bus_I_1:   DFFC port map ( D=>NI_D_0XPIN, 
            CE=>ni_nires_reg_data1pos_0_bus_CE, 
            Q=>ni_nires_reg_data1pos_0_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data0pos_0_bus_I_1:   DFFC port map ( D=>NI_D_0XPIN, 
            CE=>ni_nires_reg_data0pos_0_bus_CE, 
            Q=>ni_nires_reg_data0pos_0_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data2pos_0_bus_I_1:   DFFC port map ( D=>NI_D_0XPIN, 
            CE=>ni_nires_reg_data2pos_0_bus_CE, 
            Q=>ni_nires_reg_data2pos_0_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data_out_12_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_12_bus_D, 
            Q=>ni_nires_reg_data_out_12_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3pos_2_bus_I_1:   DFFC port map ( D=>NI_D_2XPIN, 
            CE=>ni_nires_reg_data3pos_2_bus_CE, 
            Q=>ni_nires_reg_data3pos_2_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data1pos_2_bus_I_1:   DFFC port map ( D=>NI_D_2XPIN, 
            CE=>ni_nires_reg_data1pos_2_bus_CE, 
            Q=>ni_nires_reg_data1pos_2_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data0pos_2_bus_I_1:   DFFC port map ( D=>NI_D_2XPIN, 
            CE=>ni_nires_reg_data0pos_2_bus_CE, 
            Q=>ni_nires_reg_data0pos_2_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data2pos_2_bus_I_1:   DFFC port map ( D=>NI_D_2XPIN, 
            CE=>ni_nires_reg_data2pos_2_bus_CE, 
            Q=>ni_nires_reg_data2pos_2_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data_out_13_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_13_bus_D, 
            Q=>ni_nires_reg_data_out_13_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3pos_3_bus_I_1:   DFFC port map ( D=>NI_D_3XPIN, 
            CE=>ni_nires_reg_data3pos_3_bus_CE, 
            Q=>ni_nires_reg_data3pos_3_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data1pos_3_bus_I_1:   DFFC port map ( D=>NI_D_3XPIN, 
            CE=>ni_nires_reg_data1pos_3_bus_CE, 
            Q=>ni_nires_reg_data1pos_3_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data0pos_3_bus_I_1:   DFFC port map ( D=>NI_D_3XPIN, 
            CE=>ni_nires_reg_data0pos_3_bus_CE, 
            Q=>ni_nires_reg_data0pos_3_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data2pos_3_bus_I_1:   DFFC port map ( D=>NI_D_3XPIN, 
            CE=>ni_nires_reg_data2pos_3_bus_CE, 
            Q=>ni_nires_reg_data2pos_3_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data_out_14_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_14_bus_D, 
            Q=>ni_nires_reg_data_out_14_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3pos_4_bus_I_1:   DFFC port map ( D=>NI_D_4XPIN, 
            CE=>ni_nires_reg_data3pos_4_bus_CE, 
            Q=>ni_nires_reg_data3pos_4_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data1pos_4_bus_I_1:   DFFC port map ( D=>NI_D_4XPIN, 
            CE=>ni_nires_reg_data1pos_4_bus_CE, 
            Q=>ni_nires_reg_data1pos_4_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data0pos_4_bus_I_1:   DFFC port map ( D=>NI_D_4XPIN, 
            CE=>ni_nires_reg_data0pos_4_bus_CE, 
            Q=>ni_nires_reg_data0pos_4_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data2pos_4_bus_I_1:   DFFC port map ( D=>NI_D_4XPIN, 
            CE=>ni_nires_reg_data2pos_4_bus_CE, 
            Q=>ni_nires_reg_data2pos_4_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data_out_15_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_15_bus_D, 
            Q=>ni_nires_reg_data_out_15_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3pos_5_bus_I_1:   DFFC port map ( D=>NI_D_5XPIN, 
            CE=>ni_nires_reg_data3pos_5_bus_CE, 
            Q=>ni_nires_reg_data3pos_5_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data1pos_5_bus_I_1:   DFFC port map ( D=>NI_D_5XPIN, 
            CE=>ni_nires_reg_data1pos_5_bus_CE, 
            Q=>ni_nires_reg_data1pos_5_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data0pos_5_bus_I_1:   DFFC port map ( D=>NI_D_5XPIN, 
            CE=>ni_nires_reg_data0pos_5_bus_CE, 
            Q=>ni_nires_reg_data0pos_5_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data2pos_5_bus_I_1:   DFFC port map ( D=>NI_D_5XPIN, 
            CE=>ni_nires_reg_data2pos_5_bus_CE, 
            Q=>ni_nires_reg_data2pos_5_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data_out_16_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_16_bus_D, 
            Q=>ni_nires_reg_data_out_16_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3pos_6_bus_I_1:   DFFC port map ( D=>NI_D_6XPIN, 
            CE=>ni_nires_reg_data3pos_6_bus_CE, 
            Q=>ni_nires_reg_data3pos_6_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data1pos_6_bus_I_1:   DFFC port map ( D=>NI_D_6XPIN, 
            CE=>ni_nires_reg_data1pos_6_bus_CE, 
            Q=>ni_nires_reg_data1pos_6_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data0pos_6_bus_I_1:   DFFC port map ( D=>NI_D_6XPIN, 
            CE=>ni_nires_reg_data0pos_6_bus_CE, 
            Q=>ni_nires_reg_data0pos_6_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data2pos_6_bus_I_1:   DFFC port map ( D=>NI_D_6XPIN, 
            CE=>ni_nires_reg_data2pos_6_bus_CE, 
            Q=>ni_nires_reg_data2pos_6_busQ, 
            CLK=>NI_STRPIN );
  FF_j2c_reg_creg1hm_2_bus_I_1:   DFFCSH port map ( Q=>j2c_reg_creg1hm_2_busQ, 
            S=>j2c_reg_creg1hm_2_bus_AP, 
            CLK=>j2c_reg_creg1hm_2_bus_C, 
            CE=>j2c_reg_creg1hm_2_bus_CE, 
            D=>j2c_reg_shreg_4_busQ );
  FF_ni_nires_reg_data_out_17_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_17_bus_D, 
            Q=>ni_nires_reg_data_out_17_busQ, 
            CLK=>clkPIN );
  FF_j2c_reg_cmdreg_0_bus_I_1:   DFFCSH port map ( Q=>j2c_reg_cmdreg_0_busQ, 
            S=>j2c_reg_cmdreg_0_bus_AP, 
            CLK=>j2c_reg_cmdreg_0_bus_C, 
            CE=>jTDIPIN, 
            D=>j2c_reg_shreg_4_busQ );
  FF_ni_nires_reg_data3pos_7_bus_I_1:   DFFC port map ( D=>NI_D_7XPIN, 
            CE=>ni_nires_reg_data3pos_7_bus_CE, 
            Q=>ni_nires_reg_data3pos_7_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data1pos_7_bus_I_1:   DFFC port map ( D=>NI_D_7XPIN, 
            CE=>ni_nires_reg_data1pos_7_bus_CE, 
            Q=>ni_nires_reg_data1pos_7_busQ, 
            CLK=>NI_STRPIN );
  FF_j2c_reg_shreg_4_bus_I_1:   DFF port map ( D=>j2c_reg_shreg_5_busQ, 
            Q=>j2c_reg_shreg_4_busQ, 
            CLK=>jTCKPIN );
  FF_ni_nires_reg_data0pos_7_bus_I_1:   DFFC port map ( D=>NI_D_7XPIN, 
            CE=>ni_nires_reg_data0pos_7_bus_CE, 
            Q=>ni_nires_reg_data0pos_7_busQ, 
            CLK=>NI_STRPIN );
  FF_j2c_reg_shreg_5_bus_I_1:   DFF port map ( D=>j2c_reg_shreg_6_busQ, 
            Q=>j2c_reg_shreg_5_busQ, 
            CLK=>jTCKPIN );
  FF_ni_nires_reg_data2pos_7_bus_I_1:   DFFC port map ( D=>NI_D_7XPIN, 
            CE=>ni_nires_reg_data2pos_7_bus_CE, 
            Q=>ni_nires_reg_data2pos_7_busQ, 
            CLK=>NI_STRPIN );
  FF_j2c_reg_shreg_6_bus_I_1:   DFF port map ( D=>j2c_reg_shreg_7_busQ, 
            Q=>j2c_reg_shreg_6_busQ, 
            CLK=>jTCKPIN );
  FF_j2c_reg_shreg_7_bus_I_1:   DFF port map ( D=>jTDIPIN, 
            Q=>j2c_reg_shreg_7_busQ, 
            CLK=>jTCKPIN );
  FF_j2c_reg_cmdreg_3_bus_I_1:   DFFRH port map ( Q=>j2c_reg_cmdreg_3_busQ, 
            R=>j2c_reg_cmdreg_3_bus_AR, 
            CLK=>j2c_reg_cmdreg_3_bus_C, 
            D=>j2c_reg_cmdreg_3_bus_D );
  FF_ni_nires_reg_data_out_18_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_18_bus_D, 
            Q=>ni_nires_reg_data_out_18_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3pos_8_bus_I_1:   DFFC port map ( D=>NI_D_8XPIN, 
            CE=>ni_nires_reg_data3pos_8_bus_CE, 
            Q=>ni_nires_reg_data3pos_8_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data1pos_8_bus_I_1:   DFFC port map ( D=>NI_D_8XPIN, 
            CE=>ni_nires_reg_data1pos_8_bus_CE, 
            Q=>ni_nires_reg_data1pos_8_busQ, 
            CLK=>NI_STRPIN );
  FF_j2c_reg_creg1hm_6_bus_I_1:   DFFCSH port map ( Q=>j2c_reg_creg1hm_6_busQ, 
            S=>j2c_reg_creg1hm_6_bus_AP, 
            CLK=>j2c_reg_creg1hm_6_bus_C, 
            CE=>j2c_reg_creg1hm_6_bus_CE, 
            D=>j2c_reg_shreg_7_busQ );
  FF_ni_nires_reg_data0pos_8_bus_I_1:   DFFC port map ( D=>NI_D_8XPIN, 
            CE=>ni_nires_reg_data0pos_8_bus_CE, 
            Q=>ni_nires_reg_data0pos_8_busQ, 
            CLK=>NI_STRPIN );
  FF_j2c_reg_creg1hm_5_bus_I_1:   DFFCRH port map ( Q=>j2c_reg_creg1hm_5_busQ, 
            R=>j2c_reg_creg1hm_5_bus_AR, 
            CLK=>j2c_reg_creg1hm_5_bus_C, 
            CE=>j2c_reg_creg1hm_5_bus_CE, 
            D=>j2c_reg_shreg_6_busQ );
  FF_ni_nires_reg_data2pos_8_bus_I_1:   DFFC port map ( D=>NI_D_8XPIN, 
            CE=>ni_nires_reg_data2pos_8_bus_CE, 
            Q=>ni_nires_reg_data2pos_8_busQ, 
            CLK=>NI_STRPIN );
  FF_j2c_reg_creg1hm_4_bus_I_1:   DFFCRH port map ( Q=>j2c_reg_creg1hm_4_busQ, 
            R=>j2c_reg_creg1hm_4_bus_AR, 
            CLK=>j2c_reg_creg1hm_4_bus_C, 
            CE=>j2c_reg_creg1hm_4_bus_CE, 
            D=>j2c_reg_shreg_5_busQ );
  FF_j2c_reg_creg1hm_3_bus_I_1:   DFFCSH port map ( Q=>j2c_reg_creg1hm_3_busQ, 
            S=>j2c_reg_creg1hm_3_bus_AP, 
            CLK=>j2c_reg_creg1hm_3_bus_C, 
            CE=>j2c_reg_creg1hm_3_bus_CE, 
            D=>j2c_reg_creg1hm_3_bus_D );
  FF_ni_nires_reg_data_out_19_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_19_bus_D, 
            Q=>ni_nires_reg_data_out_19_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3pos_9_bus_I_1:   DFFC port map ( D=>NI_D_9XPIN, 
            CE=>ni_nires_reg_data3pos_9_bus_CE, 
            Q=>ni_nires_reg_data3pos_9_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data1pos_9_bus_I_1:   DFFC port map ( D=>NI_D_9XPIN, 
            CE=>ni_nires_reg_data1pos_9_bus_CE, 
            Q=>ni_nires_reg_data1pos_9_busQ, 
            CLK=>NI_STRPIN );
  FF_j2c_reg_creg1hm_1_bus_I_1:   DFFCRH port map ( Q=>j2c_reg_creg1hm_1_busQ, 
            R=>j2c_reg_creg1hm_1_bus_AR, 
            CLK=>j2c_reg_creg1hm_1_bus_C, 
            CE=>j2c_reg_creg1hm_1_bus_CE, 
            D=>j2c_reg_creg1hm_1_bus_D );
  FF_ni_nires_reg_data0pos_9_bus_I_1:   DFFC port map ( D=>NI_D_9XPIN, 
            CE=>ni_nires_reg_data0pos_9_bus_CE, 
            Q=>ni_nires_reg_data0pos_9_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_data2pos_9_bus_I_1:   DFFC port map ( D=>NI_D_9XPIN, 
            CE=>ni_nires_reg_data2pos_9_bus_CE, 
            Q=>ni_nires_reg_data2pos_9_busQ, 
            CLK=>NI_STRPIN );
  FF_j2c_reg_creg1hm_0_bus_I_1:   DFFCRH port map ( Q=>j2c_reg_creg1hm_0_busQ, 
            R=>j2c_reg_creg1hm_0_bus_AR, 
            CLK=>j2c_reg_creg1hm_0_bus_C, 
            CE=>j2c_reg_creg1hm_0_bus_CE, 
            D=>j2c_reg_creg1hm_0_bus_D );
  FF_j2c_reg_cmdreg_2_bus_I_1:   DFFCSH port map ( Q=>j2c_reg_cmdreg_2_busQ, 
            S=>j2c_reg_cmdreg_2_bus_AP, 
            CLK=>j2c_reg_cmdreg_2_bus_C, 
            CE=>jTDIPIN, 
            D=>j2c_reg_shreg_6_busQ );
  FF_j2c_reg_cmdreg_1_bus_I_1:   DFFCSH port map ( Q=>j2c_reg_cmdreg_1_busQ, 
            S=>j2c_reg_cmdreg_1_bus_AP, 
            CLK=>j2c_reg_cmdreg_1_bus_C, 
            CE=>jTDIPIN, 
            D=>j2c_reg_shreg_5_busQ );
  FF_ID_3_5_bus_I_1:   TFFRH port map ( R=>j2c_reg_clearQ, 
            Q=>ID_3_5_busQ, 
            T=>FF_ID_3_5_bus_T1, 
            CLK=>clkPIN );
  FF_ID_3_5_bus_I_2:   AND2 port map ( I1=>ID_3_5_bus_T, 
            O=>FF_ID_3_5_bus_T1, 
            I0=>ID_3_5_bus_CE );
  FF_ni_reg_ce_prty_bit_pos_I_1:   DFF port map ( D=>ni_reg_ce_prty_bit_pos_D, 
            Q=>ni_reg_ce_prty_bit_posQ, 
            CLK=>clkPIN );
  FF_ni_reg_prty_bit_pos_r_I_1:   DFF port map ( D=>ni_reg_prty_bit_pos_r_D, 
            Q=>ni_reg_prty_bit_pos_rQ, 
            CLK=>clkPIN );
  FF_ni_pattcount_2_bus_I_1:   DFF port map ( D=>ni_pattcount_2_bus_D, 
            Q=>ni_pattcount_2_busQ, 
            CLK=>clkPIN );
  FF_ni_pattcount_1_bus_I_1:   DFF port map ( D=>ni_pattcount_1_bus_D, 
            Q=>ni_pattcount_1_busQ, 
            CLK=>clkPIN );
  FF_ni_pattcount_0_bus_I_1:   DFF port map ( D=>ni_pattcount_0_bus_D, 
            Q=>ni_pattcount_0_busQ, 
            CLK=>clkPIN );
  FF_ni_pattcount_4_bus_I_1:   DFF port map ( D=>ni_pattcount_4_bus_D, 
            Q=>ni_pattcount_4_busQ, 
            CLK=>clkPIN );
  FF_ni_pattcount_3_bus_I_1:   DFF port map ( D=>ni_pattcount_3_bus_D, 
            Q=>ni_pattcount_3_busQ, 
            CLK=>clkPIN );
  FF_ID_3_6_bus_I_1:   TFFRH port map ( R=>j2c_reg_clearQ, 
            Q=>ID_3_6_busQ, 
            T=>FF_ID_3_6_bus_T1, 
            CLK=>clkPIN );
  FF_ID_3_6_bus_I_2:   AND2 port map ( I1=>ID_3_6_bus_T, 
            O=>FF_ID_3_6_bus_T1, 
            I0=>ID_3_6_bus_CE );
  FF_ID_3_4_bus_I_1:   DFFCRH port map ( Q=>ID_3_4_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>ID_3_4_bus_CE, 
            D=>ID_3_4_bus_D );
  FF_ID_3_3_bus_I_1:   DFFCRH port map ( Q=>ID_3_3_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>ID_3_3_bus_CE, 
            D=>ID_3_3_bus_D );
  FF_ID_3_2_bus_I_1:   DFFCRH port map ( Q=>ID_3_2_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>ID_3_2_bus_CE, 
            D=>ID_3_2_bus_D );
  FF_ni_nires_reg_valid_I_1:   DFF port map ( D=>ni_nires_reg_valid_D, 
            Q=>ni_nires_reg_validQ, 
            CLK=>clkPIN );
  FF_ID_3_1_bus_I_1:   DFFCRH port map ( Q=>ID_3_1_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>ID_3_1_bus_CE, 
            D=>ID_3_1_bus_D );
  FF_ni_nires_reg_new_cnt_0_bus_I_1:   DFFRH port map ( Q=>ni_nires_reg_new_cnt_0_busQ, 
            R=>ni_nires_reg_new_cnt_0_bus_AR, 
            CLK=>clkPIN, 
            D=>ni_nires_reg_gray_cntf_0_busQ );
  FF_ID_3_0_bus_I_1:   DFFCRH port map ( Q=>ID_3_0_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>ID_3_0_bus_CE, 
            D=>ID_3_0_bus_D );
  FF_ni_nires_reg_gray_cntf_0_bus_I_1:   DFFRH port map ( Q=>ni_nires_reg_gray_cntf_0_busQ, 
            R=>ni_nires_reg_gray_cntf_0_bus_AR, 
            CLK=>ni_nires_reg_gray_cntf_0_bus_C, 
            D=>ni_nires_reg_gray_cntf_0_bus_D );
  FF_j2c_reg_clear_I_1:   DFFCRH port map ( Q=>j2c_reg_clearQ, 
            R=>j2c_reg_clear_AR, 
            CLK=>j2c_reg_clear_C, 
            CE=>j2c_reg_clear_CE, 
            D=>j2c_reg_clear_D );
  FF_ni_nires_reg_gray_cntf_1_bus_I_1:   DFFRH port map ( Q=>ni_nires_reg_gray_cntf_1_busQ, 
            R=>ni_nires_reg_gray_cntf_1_bus_AR, 
            CLK=>ni_nires_reg_gray_cntf_1_bus_C, 
            D=>ni_nires_reg_gray_cntf_0_busQ );
  FF_ni_nires_reg_clear_n_i_I_1:   DFF port map ( D=>ni_nires_reg_clear_n_i_D, 
            Q=>ni_nires_reg_clear_n_iQ, 
            CLK=>clkPIN );
  FF_j2c_reg_rstout_n_i_I_1:   DFFCSH port map ( Q=>j2c_reg_rstout_n_iQ, 
            S=>j2c_reg_clear_AR, 
            CLK=>j2c_reg_rstout_n_i_C, 
            CE=>j2c_reg_clear_CE, 
            D=>j2c_reg_rstout_n_i_D );
  FF_j2c_bitcnt_2_bus_I_1:   DFFRH port map ( Q=>j2c_bitcnt_2_busQ, 
            R=>j2c_reg_clear_AR, 
            CLK=>j2c_bitcnt_2_bus_C, 
            D=>j2c_bitcnt_2_bus_D );
  FF_j2c_bitcnt_1_bus_I_1:   DFFRH port map ( Q=>j2c_bitcnt_1_busQ, 
            R=>j2c_reg_clear_AR, 
            CLK=>j2c_bitcnt_1_bus_C, 
            D=>j2c_bitcnt_1_bus_D );
  FF_j2c_bitcnt_0_bus_I_1:   DFFRH port map ( Q=>j2c_bitcnt_0_busQ, 
            R=>j2c_reg_clear_AR, 
            CLK=>j2c_bitcnt_0_bus_C, 
            D=>j2c_bitcnt_0_bus_D );
  FF_ID_2_5_bus_I_1:   TFFRH port map ( R=>j2c_reg_clearQ, 
            Q=>ID_2_5_busQ, 
            T=>FF_ID_2_5_bus_T1, 
            CLK=>clkPIN );
  FF_ID_2_5_bus_I_2:   AND2 port map ( I1=>ID_2_5_bus_T, 
            O=>FF_ID_2_5_bus_T1, 
            I0=>ID_2_5_bus_CE );
  FF_ni_reg_ce_prty_bit_neg_I_1:   DFF port map ( D=>ni_reg_ce_prty_bit_neg_D, 
            Q=>ni_reg_ce_prty_bit_negQ, 
            CLK=>clkPIN );
  FF_ni_reg_prty_bit_neg_r_I_1:   DFF port map ( D=>ni_reg_prty_bit_neg_r_D, 
            Q=>ni_reg_prty_bit_neg_rQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_old_cnt_0_bus_I_1:   DFFCRH port map ( Q=>ni_nires_reg_old_cnt_0_busQ, 
            R=>ni_nires_reg_old_cnt_0_bus_AR, 
            CLK=>clkPIN, 
            CE=>ni_nires_reg_old_cnt_0_bus_CE, 
            D=>ni_nires_reg_old_cnt_0_bus_D );
  FF_ni_nires_reg_old_cnt_1_bus_I_1:   DFFCRH port map ( Q=>ni_nires_reg_old_cnt_1_busQ, 
            R=>ni_nires_reg_old_cnt_1_bus_AR, 
            CLK=>clkPIN, 
            CE=>ni_nires_reg_old_cnt_0_bus_CE, 
            D=>ni_nires_reg_old_cnt_0_busQ );
  FF_ni_nires_reg_new_cnt_1_bus_I_1:   DFFRH port map ( Q=>ni_nires_reg_new_cnt_1_busQ, 
            R=>ni_nires_reg_new_cnt_1_bus_AR, 
            CLK=>clkPIN, 
            D=>ni_nires_reg_gray_cntf_1_busQ );
  FF_ni_nires_reg_data_out_1_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_1_bus_D, 
            Q=>ni_nires_reg_data_out_1_busQ, 
            CLK=>clkPIN );
  FF_ID_2_6_bus_I_1:   TFFRH port map ( R=>j2c_reg_clearQ, 
            Q=>ID_2_6_busQ, 
            T=>FF_ID_2_6_bus_T1, 
            CLK=>clkPIN );
  FF_ID_2_6_bus_I_2:   AND2 port map ( I1=>ID_2_6_bus_T, 
            O=>FF_ID_2_6_bus_T1, 
            I0=>ID_2_6_bus_CE );
  FF_ni_nires_reg_data3neg_1_bus_I_1:   DFFC port map ( D=>NI_D_1XPIN, 
            CE=>ni_nires_reg_data3neg_1_bus_CE, 
            Q=>ni_nires_reg_data3neg_1_busQ, 
            CLK=>ni_nires_reg_data3neg_1_bus_C );
  FF_ID_2_4_bus_I_1:   DFFCRH port map ( Q=>ID_2_4_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>ID_2_4_bus_CE, 
            D=>ID_2_4_bus_D );
  FF_ni_nires_reg_data1neg_1_bus_I_1:   DFFC port map ( D=>NI_D_1XPIN, 
            CE=>ni_nires_reg_data1neg_1_bus_CE, 
            Q=>ni_nires_reg_data1neg_1_busQ, 
            CLK=>ni_nires_reg_data1neg_1_bus_C );
  FF_ID_2_3_bus_I_1:   DFFCRH port map ( Q=>ID_2_3_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>ID_2_3_bus_CE, 
            D=>ID_2_3_bus_D );
  FF_ID_2_2_bus_I_1:   DFFCRH port map ( Q=>ID_2_2_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>ID_2_2_bus_CE, 
            D=>ID_2_2_bus_D );
  FF_ni_nires_reg_data0neg_1_bus_I_1:   DFFC port map ( D=>NI_D_1XPIN, 
            CE=>ni_nires_reg_data0neg_1_bus_CE, 
            Q=>ni_nires_reg_data0neg_1_busQ, 
            CLK=>ni_nires_reg_data0neg_1_bus_C );
  FF_ID_2_1_bus_I_1:   DFFCRH port map ( Q=>ID_2_1_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>ID_2_1_bus_CE, 
            D=>ID_2_1_bus_D );
  FF_ID_2_0_bus_I_1:   DFFCRH port map ( Q=>ID_2_0_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>ID_2_0_bus_CE, 
            D=>ID_2_0_bus_D );
  FF_ni_nires_reg_data2neg_1_bus_I_1:   DFFC port map ( D=>NI_D_1XPIN, 
            CE=>ni_nires_reg_data2neg_1_bus_CE, 
            Q=>ni_nires_reg_data2neg_1_busQ, 
            CLK=>ni_nires_reg_data2neg_1_bus_C );
  FF_ni_nires_reg_data_out_0_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_0_bus_D, 
            Q=>ni_nires_reg_data_out_0_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3neg_0_bus_I_1:   DFFC port map ( D=>NI_D_0XPIN, 
            CE=>ni_nires_reg_data3neg_0_bus_CE, 
            Q=>ni_nires_reg_data3neg_0_busQ, 
            CLK=>ni_nires_reg_data3neg_0_bus_C );
  FF_ni_nires_reg_data1neg_0_bus_I_1:   DFFC port map ( D=>NI_D_0XPIN, 
            CE=>ni_nires_reg_data1neg_0_bus_CE, 
            Q=>ni_nires_reg_data1neg_0_busQ, 
            CLK=>ni_nires_reg_data1neg_0_bus_C );
  FF_ni_nires_reg_data0neg_0_bus_I_1:   DFFC port map ( D=>NI_D_0XPIN, 
            CE=>ni_nires_reg_data0neg_0_bus_CE, 
            Q=>ni_nires_reg_data0neg_0_busQ, 
            CLK=>ni_nires_reg_data0neg_0_bus_C );
  FF_ni_nires_reg_data2neg_0_bus_I_1:   DFFC port map ( D=>NI_D_0XPIN, 
            CE=>ni_nires_reg_data2neg_0_bus_CE, 
            Q=>ni_nires_reg_data2neg_0_busQ, 
            CLK=>ni_nires_reg_data2neg_0_bus_C );
  FF_j2c_reg_creg0hm_4_bus_I_1:   DFFCRH port map ( Q=>j2c_reg_creg0hm_4_busQ, 
            R=>j2c_reg_creg0hm_4_bus_AR, 
            CLK=>j2c_reg_creg0hm_4_bus_C, 
            CE=>j2c_reg_creg0hm_4_bus_CE, 
            D=>j2c_reg_shreg_1_busQ );
  FF_j2c_reg_shreg_1_bus_I_1:   DFF port map ( D=>j2c_reg_shreg_2_busQ, 
            Q=>j2c_reg_shreg_1_busQ, 
            CLK=>jTCKPIN );
  FF_j2c_reg_shreg_2_bus_I_1:   DFF port map ( D=>j2c_reg_shreg_3_busQ, 
            Q=>j2c_reg_shreg_2_busQ, 
            CLK=>jTCKPIN );
  FF_j2c_reg_shreg_3_bus_I_1:   DFF port map ( D=>j2c_reg_shreg_4_busQ, 
            Q=>j2c_reg_shreg_3_busQ, 
            CLK=>jTCKPIN );
  FF_j2c_reg_creg0hm_6_bus_I_1:   DFFCSH port map ( Q=>j2c_reg_creg0hm_6_busQ, 
            S=>j2c_reg_creg0hm_6_bus_AP, 
            CLK=>j2c_reg_creg0hm_6_bus_C, 
            CE=>j2c_reg_creg0hm_6_bus_CE, 
            D=>j2c_reg_shreg_3_busQ );
  FF_j2c_reg_creg0hm_5_bus_I_1:   DFFCRH port map ( Q=>j2c_reg_creg0hm_5_busQ, 
            R=>j2c_reg_creg0hm_5_bus_AR, 
            CLK=>j2c_reg_creg0hm_5_bus_C, 
            CE=>j2c_reg_creg0hm_5_bus_CE, 
            D=>j2c_reg_shreg_2_busQ );
  FF_j2c_reg_creg0hm_2_bus_I_1:   DFFCRH port map ( Q=>j2c_reg_creg0hm_2_busQ, 
            R=>j2c_reg_creg0hm_2_bus_AR, 
            CLK=>j2c_reg_creg0hm_2_bus_C, 
            CE=>j2c_reg_creg0hm_2_bus_CE, 
            D=>j2c_reg_shreg_0_busQ );
  FF_ID_0_6_bus_I_1:   TFFRH port map ( R=>j2c_reg_clearQ, 
            Q=>ID_0_6_busQ, 
            T=>FF_ID_0_6_bus_T1, 
            CLK=>clkPIN );
  FF_ID_0_6_bus_I_2:   AND2 port map ( I1=>ID_0_6_bus_T, 
            O=>FF_ID_0_6_bus_T1, 
            I0=>TX_ENQ );
  FF_j2c_reg_shreg_0_bus_I_1:   DFF port map ( D=>j2c_reg_shreg_1_busQ, 
            Q=>j2c_reg_shreg_0_busQ, 
            CLK=>jTCKPIN );
  FF_ID_0_5_bus_I_1:   TFFRH port map ( R=>j2c_reg_clearQ, 
            Q=>ID_0_5_busQ, 
            T=>FF_ID_0_5_bus_T1, 
            CLK=>clkPIN );
  FF_ID_0_5_bus_I_2:   AND2 port map ( I1=>ID_0_5_bus_T, 
            O=>FF_ID_0_5_bus_T1, 
            I0=>TX_ENQ );
  FF_j2c_reg_creg0hm_1_bus_I_1:   DFFCSH port map ( Q=>j2c_reg_creg0hm_1_busQ, 
            S=>j2c_reg_creg0hm_1_bus_AP, 
            CLK=>j2c_reg_creg0hm_1_bus_C, 
            CE=>j2c_reg_creg0hm_1_bus_CE, 
            D=>j2c_reg_creg0hm_1_bus_D );
  FF_ID_0_4_bus_I_1:   DFFCRH port map ( Q=>ID_0_4_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>TX_ENQ, 
            D=>ID_0_4_bus_D );
  FF_ID_0_3_bus_I_1:   DFFCRH port map ( Q=>ID_0_3_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>TX_ENQ, 
            D=>ID_0_3_bus_D );
  FF_ID_0_2_bus_I_1:   DFFCRH port map ( Q=>ID_0_2_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>TX_ENQ, 
            D=>ID_0_2_bus_D );
  FF_ID_0_1_bus_I_1:   DFFCRH port map ( Q=>ID_0_1_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>TX_ENQ, 
            D=>ID_0_1_bus_D );
  FF_ID_0_0_bus_I_1:   DFFCRH port map ( Q=>ID_0_0_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>TX_ENQ, 
            D=>ID_0_0_bus_D );
  FF_j2c_reg_creg0hm_3_bus_I_1:   DFFCSH port map ( Q=>j2c_reg_creg0hm_3_busQ, 
            S=>j2c_reg_creg0hm_3_bus_AP, 
            CLK=>j2c_reg_creg0hm_3_bus_C, 
            CE=>j2c_reg_creg0hm_3_bus_CE, 
            D=>j2c_reg_creg0hm_3_bus_D );
  FF_j2c_reg_creg0hm_0_bus_I_1:   DFFCSH port map ( Q=>j2c_reg_creg0hm_0_busQ, 
            S=>j2c_reg_creg0hm_0_bus_AP, 
            CLK=>j2c_reg_creg0hm_0_bus_C, 
            CE=>j2c_reg_creg0hm_0_bus_CE, 
            D=>j2c_reg_creg0hm_0_bus_D );
  FF_ID_0_7_bus_I_1:   TFFRH port map ( R=>j2c_reg_clearQ, 
            Q=>ID_0_7_busQ, 
            T=>FF_ID_0_7_bus_T1, 
            CLK=>clkPIN );
  FF_ID_0_7_bus_I_2:   AND2 port map ( I1=>ID_0_7_bus_T, 
            O=>FF_ID_0_7_bus_T1, 
            I0=>TX_ENQ );
  FF_ID_1_4_bus_I_1:   TFFRH port map ( R=>j2c_reg_clearQ, 
            Q=>ID_1_4_busQ, 
            T=>FF_ID_1_4_bus_T1, 
            CLK=>clkPIN );
  FF_ID_1_4_bus_I_2:   AND2 port map ( I1=>ID_1_4_bus_T, 
            O=>FF_ID_1_4_bus_T1, 
            I0=>TX_ENQ );
  FF_ID_1_3_bus_I_1:   DFFCRH port map ( Q=>ID_1_3_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>TX_ENQ, 
            D=>ID_1_3_bus_D );
  FF_ID_1_2_bus_I_1:   DFFCRH port map ( Q=>ID_1_2_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>TX_ENQ, 
            D=>ID_1_2_bus_D );
  FF_ni_nires_reg_data_out_2_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_2_bus_D, 
            Q=>ni_nires_reg_data_out_2_busQ, 
            CLK=>clkPIN );
  FF_ID_1_1_bus_I_1:   DFFCRH port map ( Q=>ID_1_1_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>TX_ENQ, 
            D=>ID_1_1_bus_D );
  FF_ni_nires_reg_data3neg_2_bus_I_1:   DFFC port map ( D=>NI_D_2XPIN, 
            CE=>ni_nires_reg_data3neg_2_bus_CE, 
            Q=>ni_nires_reg_data3neg_2_busQ, 
            CLK=>ni_nires_reg_data3neg_2_bus_C );
  FF_ID_1_0_bus_I_1:   DFFCRH port map ( Q=>ID_1_0_busQ, 
            R=>j2c_reg_clearQ, 
            CLK=>clkPIN, 
            CE=>TX_ENQ, 
            D=>ID_1_0_bus_D );
  FF_ni_nires_reg_data1neg_2_bus_I_1:   DFFC port map ( D=>NI_D_2XPIN, 
            CE=>ni_nires_reg_data1neg_2_bus_CE, 
            Q=>ni_nires_reg_data1neg_2_busQ, 
            CLK=>ni_nires_reg_data1neg_2_bus_C );
  FF_ni_nires_reg_data0neg_2_bus_I_1:   DFFC port map ( D=>NI_D_2XPIN, 
            CE=>ni_nires_reg_data0neg_2_bus_CE, 
            Q=>ni_nires_reg_data0neg_2_busQ, 
            CLK=>ni_nires_reg_data0neg_2_bus_C );
  FF_ni_nires_reg_data2neg_2_bus_I_1:   DFFC port map ( D=>NI_D_2XPIN, 
            CE=>ni_nires_reg_data2neg_2_bus_CE, 
            Q=>ni_nires_reg_data2neg_2_busQ, 
            CLK=>ni_nires_reg_data2neg_2_bus_C );
  FF_ni_nires_reg_data_out_3_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_3_bus_D, 
            Q=>ni_nires_reg_data_out_3_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3neg_3_bus_I_1:   DFFC port map ( D=>NI_D_3XPIN, 
            CE=>ni_nires_reg_data3neg_3_bus_CE, 
            Q=>ni_nires_reg_data3neg_3_busQ, 
            CLK=>ni_nires_reg_data3neg_3_bus_C );
  FF_ni_nires_reg_data1neg_3_bus_I_1:   DFFC port map ( D=>NI_D_3XPIN, 
            CE=>ni_nires_reg_data1neg_3_bus_CE, 
            Q=>ni_nires_reg_data1neg_3_busQ, 
            CLK=>ni_nires_reg_data1neg_3_bus_C );
  FF_ni_nires_reg_data0neg_3_bus_I_1:   DFFC port map ( D=>NI_D_3XPIN, 
            CE=>ni_nires_reg_data0neg_3_bus_CE, 
            Q=>ni_nires_reg_data0neg_3_busQ, 
            CLK=>ni_nires_reg_data0neg_3_bus_C );
  FF_ni_nires_reg_data2neg_3_bus_I_1:   DFFC port map ( D=>NI_D_3XPIN, 
            CE=>ni_nires_reg_data2neg_3_bus_CE, 
            Q=>ni_nires_reg_data2neg_3_busQ, 
            CLK=>ni_nires_reg_data2neg_3_bus_C );
  FF_ID_1_5_bus_I_1:   TFFRH port map ( R=>j2c_reg_clearQ, 
            Q=>ID_1_5_busQ, 
            T=>FF_ID_1_5_bus_T1, 
            CLK=>clkPIN );
  FF_ID_1_5_bus_I_2:   AND2 port map ( I1=>ID_1_5_bus_T, 
            O=>FF_ID_1_5_bus_T1, 
            I0=>TX_ENQ );
  FF_ID_1_6_bus_I_1:   TFFRH port map ( R=>j2c_reg_clearQ, 
            Q=>ID_1_6_busQ, 
            T=>FF_ID_1_6_bus_T1, 
            CLK=>clkPIN );
  FF_ID_1_6_bus_I_2:   AND2 port map ( I1=>ID_1_6_bus_T, 
            O=>FF_ID_1_6_bus_T1, 
            I0=>TX_ENQ );
  FF_ni_nires_reg_data_out_4_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_4_bus_D, 
            Q=>ni_nires_reg_data_out_4_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3neg_4_bus_I_1:   DFFC port map ( D=>NI_D_4XPIN, 
            CE=>ni_nires_reg_data3neg_4_bus_CE, 
            Q=>ni_nires_reg_data3neg_4_busQ, 
            CLK=>ni_nires_reg_data3neg_4_bus_C );
  FF_ni_nires_reg_data1neg_4_bus_I_1:   DFFC port map ( D=>NI_D_4XPIN, 
            CE=>ni_nires_reg_data1neg_4_bus_CE, 
            Q=>ni_nires_reg_data1neg_4_busQ, 
            CLK=>ni_nires_reg_data1neg_4_bus_C );
  FF_ni_nires_reg_data0neg_4_bus_I_1:   DFFC port map ( D=>NI_D_4XPIN, 
            CE=>ni_nires_reg_data0neg_4_bus_CE, 
            Q=>ni_nires_reg_data0neg_4_busQ, 
            CLK=>ni_nires_reg_data0neg_4_bus_C );
  FF_ni_nires_reg_data2neg_4_bus_I_1:   DFFC port map ( D=>NI_D_4XPIN, 
            CE=>ni_nires_reg_data2neg_4_bus_CE, 
            Q=>ni_nires_reg_data2neg_4_busQ, 
            CLK=>ni_nires_reg_data2neg_4_bus_C );
  FF_ni_nires_reg_data_out_5_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_5_bus_D, 
            Q=>ni_nires_reg_data_out_5_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3neg_5_bus_I_1:   DFFC port map ( D=>NI_D_5XPIN, 
            CE=>ni_nires_reg_data3neg_5_bus_CE, 
            Q=>ni_nires_reg_data3neg_5_busQ, 
            CLK=>ni_nires_reg_data3neg_5_bus_C );
  FF_ni_nires_reg_data1neg_5_bus_I_1:   DFFC port map ( D=>NI_D_5XPIN, 
            CE=>ni_nires_reg_data1neg_5_bus_CE, 
            Q=>ni_nires_reg_data1neg_5_busQ, 
            CLK=>ni_nires_reg_data1neg_5_bus_C );
  FF_ni_nires_reg_data0neg_5_bus_I_1:   DFFC port map ( D=>NI_D_5XPIN, 
            CE=>ni_nires_reg_data0neg_5_bus_CE, 
            Q=>ni_nires_reg_data0neg_5_busQ, 
            CLK=>ni_nires_reg_data0neg_5_bus_C );
  FF_ni_nires_reg_data2neg_5_bus_I_1:   DFFC port map ( D=>NI_D_5XPIN, 
            CE=>ni_nires_reg_data2neg_5_bus_CE, 
            Q=>ni_nires_reg_data2neg_5_busQ, 
            CLK=>ni_nires_reg_data2neg_5_bus_C );
  FF_ni_nires_reg_data_out_6_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_6_bus_D, 
            Q=>ni_nires_reg_data_out_6_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3neg_6_bus_I_1:   DFFC port map ( D=>NI_D_6XPIN, 
            CE=>ni_nires_reg_data3neg_6_bus_CE, 
            Q=>ni_nires_reg_data3neg_6_busQ, 
            CLK=>ni_nires_reg_data3neg_6_bus_C );
  FF_ni_nires_reg_data1neg_6_bus_I_1:   DFFC port map ( D=>NI_D_6XPIN, 
            CE=>ni_nires_reg_data1neg_6_bus_CE, 
            Q=>ni_nires_reg_data1neg_6_busQ, 
            CLK=>ni_nires_reg_data1neg_6_bus_C );
  FF_ni_nires_reg_data0neg_6_bus_I_1:   DFFC port map ( D=>NI_D_6XPIN, 
            CE=>ni_nires_reg_data0neg_6_bus_CE, 
            Q=>ni_nires_reg_data0neg_6_busQ, 
            CLK=>ni_nires_reg_data0neg_6_bus_C );
  FF_ni_nires_reg_data2neg_6_bus_I_1:   DFFC port map ( D=>NI_D_6XPIN, 
            CE=>ni_nires_reg_data2neg_6_bus_CE, 
            Q=>ni_nires_reg_data2neg_6_busQ, 
            CLK=>ni_nires_reg_data2neg_6_bus_C );
  FF_ni_nires_reg_data_out_7_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_7_bus_D, 
            Q=>ni_nires_reg_data_out_7_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3neg_7_bus_I_1:   DFFC port map ( D=>NI_D_7XPIN, 
            CE=>ni_nires_reg_data3neg_7_bus_CE, 
            Q=>ni_nires_reg_data3neg_7_busQ, 
            CLK=>ni_nires_reg_data3neg_7_bus_C );
  FF_ni_nires_reg_data1neg_7_bus_I_1:   DFFC port map ( D=>NI_D_7XPIN, 
            CE=>ni_nires_reg_data1neg_7_bus_CE, 
            Q=>ni_nires_reg_data1neg_7_busQ, 
            CLK=>ni_nires_reg_data1neg_7_bus_C );
  FF_ni_nires_reg_data0neg_7_bus_I_1:   DFFC port map ( D=>NI_D_7XPIN, 
            CE=>ni_nires_reg_data0neg_7_bus_CE, 
            Q=>ni_nires_reg_data0neg_7_busQ, 
            CLK=>ni_nires_reg_data0neg_7_bus_C );
  FF_ni_nires_reg_data2neg_7_bus_I_1:   DFFC port map ( D=>NI_D_7XPIN, 
            CE=>ni_nires_reg_data2neg_7_bus_CE, 
            Q=>ni_nires_reg_data2neg_7_busQ, 
            CLK=>ni_nires_reg_data2neg_7_bus_C );
  FF_ni_nires_reg_data_out_8_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_8_bus_D, 
            Q=>ni_nires_reg_data_out_8_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3neg_8_bus_I_1:   DFFC port map ( D=>NI_D_8XPIN, 
            CE=>ni_nires_reg_data3neg_8_bus_CE, 
            Q=>ni_nires_reg_data3neg_8_busQ, 
            CLK=>ni_nires_reg_data3neg_8_bus_C );
  FF_ni_nires_reg_data1neg_8_bus_I_1:   DFFC port map ( D=>NI_D_8XPIN, 
            CE=>ni_nires_reg_data1neg_8_bus_CE, 
            Q=>ni_nires_reg_data1neg_8_busQ, 
            CLK=>ni_nires_reg_data1neg_8_bus_C );
  FF_ni_nires_reg_data0neg_8_bus_I_1:   DFFC port map ( D=>NI_D_8XPIN, 
            CE=>ni_nires_reg_data0neg_8_bus_CE, 
            Q=>ni_nires_reg_data0neg_8_busQ, 
            CLK=>ni_nires_reg_data0neg_8_bus_C );
  FF_ni_nires_reg_data2neg_8_bus_I_1:   DFFC port map ( D=>NI_D_8XPIN, 
            CE=>ni_nires_reg_data2neg_8_bus_CE, 
            Q=>ni_nires_reg_data2neg_8_busQ, 
            CLK=>ni_nires_reg_data2neg_8_bus_C );
  FF_ni_nires_reg_data_out_9_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_9_bus_D, 
            Q=>ni_nires_reg_data_out_9_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3neg_9_bus_I_1:   DFFC port map ( D=>NI_D_9XPIN, 
            CE=>ni_nires_reg_data3neg_9_bus_CE, 
            Q=>ni_nires_reg_data3neg_9_busQ, 
            CLK=>ni_nires_reg_data3neg_9_bus_C );
  FF_ni_nires_reg_data1neg_9_bus_I_1:   DFFC port map ( D=>NI_D_9XPIN, 
            CE=>ni_nires_reg_data1neg_9_bus_CE, 
            Q=>ni_nires_reg_data1neg_9_busQ, 
            CLK=>ni_nires_reg_data1neg_9_bus_C );
  FF_ni_nires_reg_data0neg_9_bus_I_1:   DFFC port map ( D=>NI_D_9XPIN, 
            CE=>ni_nires_reg_data0neg_9_bus_CE, 
            Q=>ni_nires_reg_data0neg_9_busQ, 
            CLK=>ni_nires_reg_data0neg_9_bus_C );
  FF_ni_nires_reg_data2neg_9_bus_I_1:   DFFC port map ( D=>NI_D_9XPIN, 
            CE=>ni_nires_reg_data2neg_9_bus_CE, 
            Q=>ni_nires_reg_data2neg_9_busQ, 
            CLK=>ni_nires_reg_data2neg_9_bus_C );
  FF_ni_nires_reg_data_out_11_bus_I_1:   DFF port map ( D=>ni_nires_reg_data_out_11_bus_D, 
            Q=>ni_nires_reg_data_out_11_busQ, 
            CLK=>clkPIN );
  FF_ni_nires_reg_data3pos_1_bus_I_1:   DFFC port map ( D=>NI_D_1XPIN, 
            CE=>ni_nires_reg_data3pos_1_bus_CE, 
            Q=>ni_nires_reg_data3pos_1_busQ, 
            CLK=>NI_STRPIN );
  FF_ni_nires_reg_gray_cnt_1_bus_I_1:   DFFRH port map ( Q=>ni_nires_reg_gray_cnt_1_busQ, 
            R=>ni_nires_reg_gray_cnt_1_bus_AR, 
            CLK=>NI_STRPIN, 
            D=>ni_nires_reg_gray_cnt_0_busQ );
  FF_ni_nires_reg_gray_cnt_0_bus_I_1:   DFFRH port map ( Q=>ni_nires_reg_gray_cnt_0_busQ, 
            R=>ni_nires_reg_gray_cnt_0_bus_AR, 
            CLK=>NI_STRPIN, 
            D=>ni_nires_reg_gray_cnt_0_bus_D );
  FF_ni_nires_reg_data1pos_1_bus_I_1:   DFFC port map ( D=>NI_D_1XPIN, 
            CE=>ni_nires_reg_data1pos_1_bus_CE, 
            Q=>ni_nires_reg_data1pos_1_busQ, 
            CLK=>NI_STRPIN );
  GATE_PRBSEN_I_3:   AND4 port map ( O=>PRBSENCOM, 
            I3=>ix1084, 
            I2=>ix1266, 
            I1=>GATE_PRBSEN_B, 
            I0=>GATE_PRBSEN_A );
  GATE_PRBSEN_I_2:   INV port map ( I0=>ix1164, 
            O=>GATE_PRBSEN_B );
  GATE_PRBSEN_I_1:   INV port map ( I0=>ix1160, 
            O=>GATE_PRBSEN_A );
  GATE_T_0_I_1:   NAN2 port map ( O=>T_0, 
            I0=>reset_nPIN, 
            I1=>GATE_T_0_A );
  GATE_T_0_I_2:   INV port map ( O=>GATE_T_0_A, 
            I0=>T_446 );
  GATE_T_1_I_1:   NAN2 port map ( O=>T_1, 
            I0=>reset_nPIN, 
            I1=>GATE_T_1_A );
  GATE_T_1_I_2:   INV port map ( O=>GATE_T_1_A, 
            I0=>T_445 );
  GATE_T_2_I_1:   NAN2 port map ( O=>T_2, 
            I0=>reset_nPIN, 
            I1=>GATE_T_2_A );
  GATE_T_2_I_2:   INV port map ( O=>GATE_T_2_A, 
            I0=>T_444 );
  GATE_T_3_I_1:   NOR4 port map ( I0=>ix1160, 
            I1=>ix1164, 
            O=>T_3, 
            I2=>ix1266, 
            I3=>GATE_T_3_DN );
  GATE_T_3_I_2:   INV port map ( I0=>ix1084, 
            O=>GATE_T_3_DN );
  GATE_SCL_OE_I_1:   AND2 port map ( O=>SCL_OE, 
            I1=>DIS_JTGPIN, 
            I0=>GATE_SCL_OE_A );
  GATE_SCL_OE_I_2:   INV port map ( O=>GATE_SCL_OE_A, 
            I0=>jTCKPIN );
  GATE_SDA_OE_I_1:   AND2 port map ( O=>SDA_OE, 
            I1=>DIS_JTGPIN, 
            I0=>GATE_SDA_OE_A );
  GATE_SDA_OE_I_2:   INV port map ( O=>GATE_SDA_OE_A, 
            I0=>jTMSPIN );
  GATE_T_4_I_1:   OR4 port map ( I0=>T_691, 
            I1=>T_690, 
            O=>T_4, 
            I2=>T_689, 
            I3=>T_688 );
  GATE_TXD_4X_D_I_1:   OR3 port map ( O=>TXD_4X_D, 
            I2=>T_685, 
            I1=>T_358, 
            I0=>T_684 );
  GATE_TXD_3X_D_X1_I_1:   OR3 port map ( O=>TXD_3X_D_X1, 
            I2=>T_486, 
            I1=>T_487, 
            I0=>T_485 );
  GATE_TXD_3X_D_X2_I_1:   AND4 port map ( O=>TXD_3X_D_X2, 
            I3=>nx1271, 
            I2=>TXD_0XQ, 
            I1=>TXD_1XQ, 
            I0=>TXD_2XQ );
  GATE_TXD_2X_D_I_1:   OR4 port map ( I0=>T_349, 
            I1=>T_665, 
            O=>TXD_2X_D, 
            I2=>T_664, 
            I3=>T_663 );
  GATE_TXD_1X_D_I_1:   OR4 port map ( I0=>T_658, 
            I1=>T_657, 
            O=>TXD_1X_D, 
            I2=>T_656, 
            I3=>T_655 );
  GATE_TXD_0X_D_I_1:   OR3 port map ( O=>TXD_0X_D, 
            I2=>T_645, 
            I1=>T_646, 
            I0=>T_644 );
  GATE_T_5_I_1:   OR2 port map ( O=>T_5, 
            I1=>T_319, 
            I0=>T_318 );
  GATE_TXD_15X_D_X1_I_1:   OR3 port map ( O=>TXD_15X_D_X1, 
            I2=>T_484, 
            I1=>T_30, 
            I0=>T_483 );
  GATE_TXD_15X_D_X2_I_1:   AND4 port map ( O=>TXD_15X_D_X2, 
            I3=>nx1271, 
            I2=>TXD_12XQ, 
            I1=>TXD_13XQ, 
            I0=>TXD_14XQ );
  GATE_TXD_14X_D_I_1:   OR4 port map ( I0=>T_312, 
            I1=>T_632, 
            O=>TXD_14X_D, 
            I2=>T_631, 
            I3=>T_630 );
  GATE_TXD_13X_D_I_1:   OR3 port map ( O=>TXD_13X_D, 
            I2=>T_629, 
            I1=>T_299, 
            I0=>T_628 );
  GATE_TXD_12X_D_I_1:   OR3 port map ( O=>TXD_12X_D, 
            I2=>T_625, 
            I1=>T_289, 
            I0=>T_624 );
  GATE_TXD_11X_D_X1_I_1:   OR3 port map ( O=>TXD_11X_D_X1, 
            I2=>T_478, 
            I1=>T_479, 
            I0=>T_477 );
  GATE_TXD_11X_D_X2_I_1:   NOR4 port map ( I0=>TXD_10XQ, 
            I1=>TXD_9XQ, 
            O=>TXD_11X_D_X2, 
            I2=>TXD_8XQ, 
            I3=>GATE_TXD_11X_D_X2_DN );
  GATE_TXD_11X_D_X2_I_2:   INV port map ( I0=>nx1271, 
            O=>GATE_TXD_11X_D_X2_DN );
  GATE_TXD_10X_D_I_1:   OR4 port map ( I0=>T_284, 
            I1=>T_605, 
            O=>TXD_10X_D, 
            I2=>T_604, 
            I3=>T_603 );
  GATE_TXD_9X_D_I_1:   OR4 port map ( I0=>T_598, 
            I1=>T_597, 
            O=>TXD_9X_D, 
            I2=>T_596, 
            I3=>T_595 );
  GATE_TXD_8X_D_I_1:   OR3 port map ( O=>TXD_8X_D, 
            I2=>T_585, 
            I1=>T_586, 
            I0=>T_584 );
  GATE_TXD_7X_D_X1_I_1:   OR3 port map ( O=>TXD_7X_D_X1, 
            I2=>T_476, 
            I1=>T_19, 
            I0=>T_475 );
  GATE_TXD_7X_D_X2_I_1:   NOR4 port map ( I0=>TXD_6XQ, 
            I1=>TXD_5XQ, 
            O=>TXD_7X_D_X2, 
            I2=>TXD_4XQ, 
            I3=>GATE_TXD_7X_D_X2_DN );
  GATE_TXD_7X_D_X2_I_2:   INV port map ( I0=>nx1271, 
            O=>GATE_TXD_7X_D_X2_DN );
  GATE_TXD_6X_D_I_1:   OR4 port map ( I0=>T_251, 
            I1=>T_575, 
            O=>TXD_6X_D, 
            I2=>T_574, 
            I3=>T_573 );
  GATE_TXD_5X_D_I_1:   OR3 port map ( O=>TXD_5X_D, 
            I2=>T_572, 
            I1=>T_244, 
            I0=>T_571 );
  GATE_ni_nires_reg_data0pos_1_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0pos_1_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_nx2236_I_1:   OR3 port map ( O=>nx2236, 
            I2=>T_687, 
            I1=>T_367, 
            I0=>T_686 );
  GATE_ni_nires_reg_data2pos_1_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2pos_1_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data_out_10_bus_D_I_1:   OR4 port map ( I0=>T_236, 
            I1=>T_237, 
            O=>ni_nires_reg_data_out_10_bus_D, 
            I2=>T_238, 
            I3=>T_239 );
  GATE_ni_nires_reg_data3pos_0_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3pos_0_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_1_busQ, 
            I0=>GATE_ni_nires_reg_data3pos_0_bus_CE_A );
  GATE_ni_nires_reg_data3pos_0_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3pos_0_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_0_busQ );
  GATE_ni_nires_reg_data1pos_0_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1pos_0_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>GATE_ni_nires_reg_data1pos_0_bus_CE_A );
  GATE_ni_nires_reg_data1pos_0_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1pos_0_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_nx1195_I_1:   OR4 port map ( I0=>T_695, 
            I1=>T_694, 
            O=>nx1195, 
            I2=>T_693, 
            I3=>T_692 );
  GATE_ni_nires_reg_data0pos_0_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0pos_0_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data2pos_0_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2pos_0_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data_out_12_bus_D_I_1:   OR4 port map ( I0=>T_232, 
            I1=>T_233, 
            O=>ni_nires_reg_data_out_12_bus_D, 
            I2=>T_234, 
            I3=>T_235 );
  GATE_ni_nires_reg_data3pos_2_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3pos_2_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_1_busQ, 
            I0=>GATE_ni_nires_reg_data3pos_2_bus_CE_A );
  GATE_ni_nires_reg_data3pos_2_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3pos_2_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_0_busQ );
  GATE_nx2272_X1_I_1:   OR3 port map ( O=>nx2272_X1, 
            I2=>T_253, 
            I1=>T_252, 
            I0=>T_254 );
  GATE_nx2272_X2_I_1:   AND2 port map ( O=>nx2272_X2, 
            I1=>ix1160, 
            I0=>GATE_nx2272_X2_A );
  GATE_nx2272_X2_I_2:   INV port map ( O=>GATE_nx2272_X2_A, 
            I0=>ni_nires_reg_data_out_7_busQ );
  GATE_ni_nires_reg_data1pos_2_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1pos_2_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>GATE_ni_nires_reg_data1pos_2_bus_CE_A );
  GATE_ni_nires_reg_data1pos_2_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1pos_2_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data0pos_2_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0pos_2_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ix1266_I_1:   OR4 port map ( I0=>T_459, 
            I1=>T_460, 
            O=>ix1266, 
            I2=>T_461, 
            I3=>T_462 );
  GATE_ni_nires_reg_data2pos_2_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2pos_2_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_nx1271_I_3:   AND4 port map ( O=>nx1271, 
            I3=>ix1164, 
            I2=>ix1266, 
            I1=>GATE_nx1271_B, 
            I0=>GATE_nx1271_A );
  GATE_nx1271_I_2:   INV port map ( I0=>ix1160, 
            O=>GATE_nx1271_B );
  GATE_nx1271_I_1:   INV port map ( I0=>ix1084, 
            O=>GATE_nx1271_A );
  GATE_ni_nires_reg_data_out_13_bus_D_I_1:   OR4 port map ( I0=>T_228, 
            I1=>T_229, 
            O=>ni_nires_reg_data_out_13_bus_D, 
            I2=>T_230, 
            I3=>T_231 );
  GATE_ni_nires_reg_data3pos_3_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3pos_3_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_1_busQ, 
            I0=>GATE_ni_nires_reg_data3pos_3_bus_CE_A );
  GATE_ni_nires_reg_data3pos_3_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3pos_3_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_0_busQ );
  GATE_ni_nires_reg_data1pos_3_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1pos_3_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>GATE_ni_nires_reg_data1pos_3_bus_CE_A );
  GATE_ni_nires_reg_data1pos_3_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1pos_3_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_nx2294_I_1:   OR4 port map ( I0=>T_359, 
            I1=>T_360, 
            O=>nx2294, 
            I2=>T_361, 
            I3=>T_362 );
  GATE_ni_nires_reg_data0pos_3_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0pos_3_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_nx1361_I_1:   AND4 port map ( O=>nx1361, 
            I3=>T_499, 
            I2=>T_500, 
            I1=>T_501, 
            I0=>T_502 );
  GATE_ni_nires_reg_data2pos_3_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2pos_3_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data_out_14_bus_D_I_1:   OR4 port map ( I0=>T_224, 
            I1=>T_225, 
            O=>ni_nires_reg_data_out_14_bus_D, 
            I2=>T_226, 
            I3=>T_227 );
  GATE_ni_nires_reg_data3pos_4_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3pos_4_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_1_busQ, 
            I0=>GATE_ni_nires_reg_data3pos_4_bus_CE_A );
  GATE_ni_nires_reg_data3pos_4_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3pos_4_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_0_busQ );
  GATE_ni_nires_reg_data1pos_4_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1pos_4_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>GATE_ni_nires_reg_data1pos_4_bus_CE_A );
  GATE_ni_nires_reg_data1pos_4_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1pos_4_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data0pos_4_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0pos_4_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data2pos_4_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2pos_4_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data_out_15_bus_D_I_1:   OR4 port map ( I0=>T_220, 
            I1=>T_221, 
            O=>ni_nires_reg_data_out_15_bus_D, 
            I2=>T_222, 
            I3=>T_223 );
  GATE_ni_nires_reg_data3pos_5_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3pos_5_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_1_busQ, 
            I0=>GATE_ni_nires_reg_data3pos_5_bus_CE_A );
  GATE_ni_nires_reg_data3pos_5_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3pos_5_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_0_busQ );
  GATE_ni_nires_reg_data1pos_5_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1pos_5_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>GATE_ni_nires_reg_data1pos_5_bus_CE_A );
  GATE_ni_nires_reg_data1pos_5_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1pos_5_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data0pos_5_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0pos_5_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data2pos_5_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2pos_5_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data_out_16_bus_D_I_1:   OR4 port map ( I0=>T_216, 
            I1=>T_217, 
            O=>ni_nires_reg_data_out_16_bus_D, 
            I2=>T_218, 
            I3=>T_219 );
  GATE_ni_nires_reg_data3pos_6_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3pos_6_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_1_busQ, 
            I0=>GATE_ni_nires_reg_data3pos_6_bus_CE_A );
  GATE_ni_nires_reg_data3pos_6_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3pos_6_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_0_busQ );
  GATE_ni_nires_reg_data1pos_6_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1pos_6_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>GATE_ni_nires_reg_data1pos_6_bus_CE_A );
  GATE_ni_nires_reg_data1pos_6_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1pos_6_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data0pos_6_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0pos_6_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data2pos_6_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2pos_6_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_jTDO_OE_I_1:   OR2 port map ( O=>jTDO_OE, 
            I1=>T_368, 
            I0=>DIS_JTGPIN );
  GATE_j2c_reg_creg1hm_2_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg1hm_2_bus_C );
  GATE_j2c_reg_creg1hm_2_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg1hm_2_bus_CE_A );
  GATE_j2c_reg_creg1hm_2_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg1hm_2_bus_CE_B );
  GATE_j2c_reg_creg1hm_2_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg1hm_2_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg1hm_2_bus_CE_A, 
            I1=>GATE_j2c_reg_creg1hm_2_bus_CE_B );
  GATE_j2c_reg_creg1hm_2_bus_AP_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg1hm_2_bus_AP );
  GATE_ni_nires_reg_data_out_17_bus_D_I_1:   OR4 port map ( I0=>T_212, 
            I1=>T_213, 
            O=>ni_nires_reg_data_out_17_bus_D, 
            I2=>T_214, 
            I3=>T_215 );
  GATE_j2c_reg_cmdreg_0_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_cmdreg_0_bus_C );
  GATE_j2c_reg_cmdreg_0_bus_AP_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_cmdreg_0_bus_AP );
  GATE_ni_nires_reg_data3pos_7_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3pos_7_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_1_busQ, 
            I0=>GATE_ni_nires_reg_data3pos_7_bus_CE_A );
  GATE_ni_nires_reg_data3pos_7_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3pos_7_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_0_busQ );
  GATE_j2c_reg_clear_AR_I_1:   NOR2 port map ( O=>j2c_reg_clear_AR, 
            I1=>jTMSPIN, 
            I0=>DIS_JTGPIN );
  GATE_ni_nires_reg_data1pos_7_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1pos_7_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>GATE_ni_nires_reg_data1pos_7_bus_CE_A );
  GATE_ni_nires_reg_data1pos_7_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1pos_7_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data0pos_7_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0pos_7_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ni_nires_reg_data2pos_7_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2pos_7_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_j2c_reg_cmdreg_3_bus_D_I_1:   AND2 port map ( O=>j2c_reg_cmdreg_3_bus_D, 
            I1=>j2c_reg_shreg_7_busQ, 
            I0=>jTDIPIN );
  GATE_j2c_reg_cmdreg_3_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_cmdreg_3_bus_C );
  GATE_j2c_reg_cmdreg_3_bus_AR_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_cmdreg_3_bus_AR );
  GATE_ni_nires_reg_data_out_18_bus_D_I_1:   OR4 port map ( I0=>T_208, 
            I1=>T_209, 
            O=>ni_nires_reg_data_out_18_bus_D, 
            I2=>T_210, 
            I3=>T_211 );
  GATE_ni_nires_reg_data3pos_8_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3pos_8_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_1_busQ, 
            I0=>GATE_ni_nires_reg_data3pos_8_bus_CE_A );
  GATE_ni_nires_reg_data3pos_8_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3pos_8_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_0_busQ );
  GATE_ni_nires_reg_data1pos_8_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1pos_8_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>GATE_ni_nires_reg_data1pos_8_bus_CE_A );
  GATE_ni_nires_reg_data1pos_8_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1pos_8_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_j2c_reg_creg1hm_6_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg1hm_6_bus_C );
  GATE_j2c_reg_creg1hm_6_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg1hm_6_bus_CE_A );
  GATE_j2c_reg_creg1hm_6_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg1hm_6_bus_CE_B );
  GATE_j2c_reg_creg1hm_6_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg1hm_6_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg1hm_6_bus_CE_A, 
            I1=>GATE_j2c_reg_creg1hm_6_bus_CE_B );
  GATE_j2c_reg_creg1hm_6_bus_AP_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg1hm_6_bus_AP );
  GATE_ni_nires_reg_data0pos_8_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0pos_8_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_j2c_reg_creg1hm_5_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg1hm_5_bus_C );
  GATE_j2c_reg_creg1hm_5_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg1hm_5_bus_CE_A );
  GATE_j2c_reg_creg1hm_5_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg1hm_5_bus_CE_B );
  GATE_j2c_reg_creg1hm_5_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg1hm_5_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg1hm_5_bus_CE_A, 
            I1=>GATE_j2c_reg_creg1hm_5_bus_CE_B );
  GATE_j2c_reg_creg1hm_5_bus_AR_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg1hm_5_bus_AR );
  GATE_ni_nires_reg_data2pos_8_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2pos_8_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_j2c_reg_creg1hm_4_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg1hm_4_bus_C );
  GATE_j2c_reg_creg1hm_4_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg1hm_4_bus_CE_A );
  GATE_j2c_reg_creg1hm_4_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg1hm_4_bus_CE_B );
  GATE_j2c_reg_creg1hm_4_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg1hm_4_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg1hm_4_bus_CE_A, 
            I1=>GATE_j2c_reg_creg1hm_4_bus_CE_B );
  GATE_j2c_reg_creg1hm_4_bus_AR_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg1hm_4_bus_AR );
  GATE_j2c_reg_creg1hm_3_bus_D_I_1:   OR4 port map ( I0=>T_204, 
            I1=>T_205, 
            O=>j2c_reg_creg1hm_3_bus_D, 
            I2=>T_206, 
            I3=>T_207 );
  GATE_j2c_reg_creg1hm_3_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg1hm_3_bus_C );
  GATE_j2c_reg_creg1hm_3_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg1hm_3_bus_CE_A );
  GATE_j2c_reg_creg1hm_3_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg1hm_3_bus_CE_B );
  GATE_j2c_reg_creg1hm_3_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg1hm_3_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg1hm_3_bus_CE_A, 
            I1=>GATE_j2c_reg_creg1hm_3_bus_CE_B );
  GATE_j2c_reg_creg1hm_3_bus_AP_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg1hm_3_bus_AP );
  GATE_ni_nires_reg_data_out_19_bus_D_I_1:   OR4 port map ( I0=>T_200, 
            I1=>T_201, 
            O=>ni_nires_reg_data_out_19_bus_D, 
            I2=>T_202, 
            I3=>T_203 );
  GATE_ni_nires_reg_data3pos_9_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3pos_9_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_1_busQ, 
            I0=>GATE_ni_nires_reg_data3pos_9_bus_CE_A );
  GATE_ni_nires_reg_data3pos_9_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3pos_9_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_0_busQ );
  GATE_ix47_X1_I_1:   OR4 port map ( I0=>T_471, 
            I1=>T_472, 
            O=>ix47_X1, 
            I2=>T_473, 
            I3=>T_474 );
  GATE_ni_nires_reg_data1pos_9_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1pos_9_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>GATE_ni_nires_reg_data1pos_9_bus_CE_A );
  GATE_ni_nires_reg_data1pos_9_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1pos_9_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_nx1519_I_1:   AND3 port map ( O=>nx1519, 
            I2=>ix1160, 
            I1=>ix1084, 
            I0=>ix1164 );
  GATE_j2c_reg_creg1hm_1_bus_D_I_1:   OR4 port map ( I0=>T_196, 
            I1=>T_197, 
            O=>j2c_reg_creg1hm_1_bus_D, 
            I2=>T_198, 
            I3=>T_199 );
  GATE_j2c_reg_creg1hm_1_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg1hm_1_bus_C );
  GATE_j2c_reg_creg1hm_1_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg1hm_1_bus_CE_A );
  GATE_j2c_reg_creg1hm_1_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg1hm_1_bus_CE_B );
  GATE_j2c_reg_creg1hm_1_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg1hm_1_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg1hm_1_bus_CE_A, 
            I1=>GATE_j2c_reg_creg1hm_1_bus_CE_B );
  GATE_j2c_reg_creg1hm_1_bus_AR_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg1hm_1_bus_AR );
  GATE_ni_nires_reg_data0pos_9_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0pos_9_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ix1524_I_1:   OR4 port map ( I0=>T_412, 
            I1=>T_413, 
            O=>ix1524, 
            I2=>T_414, 
            I3=>T_415 );
  GATE_ni_nires_reg_data2pos_9_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2pos_9_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ix1578_I_1:   OR4 port map ( I0=>T_408, 
            I1=>T_409, 
            O=>ix1578, 
            I2=>T_410, 
            I3=>T_411 );
  GATE_ix59_X1_I_1:   OR4 port map ( I0=>T_467, 
            I1=>T_468, 
            O=>ix59_X1, 
            I2=>T_469, 
            I3=>T_470 );
  GATE_j2c_reg_creg1hm_0_bus_D_I_1:   OR4 port map ( I0=>T_192, 
            I1=>T_193, 
            O=>j2c_reg_creg1hm_0_bus_D, 
            I2=>T_194, 
            I3=>T_195 );
  GATE_j2c_reg_creg1hm_0_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg1hm_0_bus_C );
  GATE_j2c_reg_creg1hm_0_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg1hm_0_bus_CE_A );
  GATE_j2c_reg_creg1hm_0_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg1hm_0_bus_CE_B );
  GATE_j2c_reg_creg1hm_0_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg1hm_0_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg1hm_0_bus_CE_A, 
            I1=>GATE_j2c_reg_creg1hm_0_bus_CE_B );
  GATE_j2c_reg_creg1hm_0_bus_AR_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg1hm_0_bus_AR );
  GATE_j2c_reg_cmdreg_2_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_cmdreg_2_bus_C );
  GATE_j2c_reg_cmdreg_2_bus_AP_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_cmdreg_2_bus_AP );
  GATE_j2c_reg_cmdreg_1_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_cmdreg_1_bus_C );
  GATE_j2c_reg_cmdreg_1_bus_AP_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_cmdreg_1_bus_AP );
  GATE_nx1595_I_1:   AND2 port map ( O=>nx1595, 
            I1=>ix1610, 
            I0=>ix1598 );
  GATE_ix1598_I_1:   OR4 port map ( I0=>T_404, 
            I1=>T_405, 
            O=>ix1598, 
            I2=>T_406, 
            I3=>T_407 );
  GATE_ix71_X1_I_1:   OR4 port map ( I0=>T_463, 
            I1=>T_464, 
            O=>ix71_X1, 
            I2=>T_465, 
            I3=>T_466 );
  GATE_ix1610_I_1:   OR4 port map ( I0=>T_400, 
            I1=>T_401, 
            O=>ix1610, 
            I2=>T_402, 
            I3=>T_403 );
  GATE_ID_3_5_bus_T_I_1:   AND3 port map ( O=>ID_3_5_bus_T, 
            I2=>T_570, 
            I1=>ID_3_0_busQ, 
            I0=>T_569 );
  GATE_ni_reg_ce_prty_bit_pos_D_I_1:   OR4 port map ( I0=>T_179, 
            I1=>T_180, 
            O=>ni_reg_ce_prty_bit_pos_D, 
            I2=>T_181, 
            I3=>T_182 );
  GATE_ni_reg_prty_bit_pos_r_D_I_1:   OR4 port map ( I0=>T_172, 
            I1=>T_546, 
            O=>ni_reg_prty_bit_pos_r_D, 
            I2=>T_545, 
            I3=>T_544 );
  GATE_ni_pattcount_2_bus_D_I_1:   OR3 port map ( O=>ni_pattcount_2_bus_D, 
            I2=>T_158, 
            I1=>T_157, 
            I0=>T_159 );
  GATE_ni_pattcount_1_bus_D_I_1:   XOR2 port map ( O=>ni_pattcount_1_bus_D, 
            I1=>ni_pattcount_0_busQ, 
            I0=>ni_pattcount_1_busQ );
  GATE_ni_pattcount_0_bus_D_I_1:   INV port map ( I0=>ni_pattcount_0_busQ, 
            O=>ni_pattcount_0_bus_D );
  GATE_ix1641_X1_I_1:   OR4 port map ( I0=>T_187, 
            I1=>T_188, 
            O=>ix1641_X1, 
            I2=>T_189, 
            I3=>T_190 );
  GATE_ix1647_X1_I_1:   OR4 port map ( I0=>T_183, 
            I1=>T_184, 
            O=>ix1647_X1, 
            I2=>T_185, 
            I3=>T_186 );
  GATE_nx1647_I_1:   AND2 port map ( O=>nx1647, 
            I1=>ix1578, 
            I0=>ix1524 );
  GATE_ni_pattcount_4_bus_D_X1_I_1:   AND4 port map ( O=>ni_pattcount_4_bus_D_X1, 
            I3=>ni_pattcount_3_busQ, 
            I2=>ni_pattcount_0_busQ, 
            I1=>ni_pattcount_1_busQ, 
            I0=>ni_pattcount_2_busQ );
  GATE_ni_pattcount_3_bus_D_I_1:   OR4 port map ( I0=>T_153, 
            I1=>T_154, 
            O=>ni_pattcount_3_bus_D, 
            I2=>T_155, 
            I3=>T_156 );
  GATE_ID_3_6_bus_T_I_1:   AND3 port map ( O=>ID_3_6_bus_T, 
            I2=>T_542, 
            I1=>T_543, 
            I0=>T_541 );
  GATE_ID_3_4_bus_D_X2_I_1:   AND4 port map ( O=>ID_3_4_bus_D_X2, 
            I3=>ID_3_0_busQ, 
            I2=>ID_3_1_busQ, 
            I1=>ID_3_2_busQ, 
            I0=>ID_3_3_busQ );
  GATE_ID_3_3_bus_D_I_1:   OR4 port map ( I0=>T_149, 
            I1=>T_150, 
            O=>ID_3_3_bus_D, 
            I2=>T_151, 
            I3=>T_152 );
  GATE_ID_3_2_bus_D_I_1:   OR3 port map ( O=>ID_3_2_bus_D, 
            I2=>T_147, 
            I1=>T_146, 
            I0=>T_148 );
  GATE_ni_nires_reg_valid_D_I_1:   OR4 port map ( I0=>T_142, 
            I1=>T_143, 
            O=>ni_nires_reg_valid_D, 
            I2=>T_144, 
            I3=>T_145 );
  GATE_ID_3_1_bus_D_I_1:   XOR2 port map ( O=>ID_3_1_bus_D, 
            I1=>ID_3_0_busQ, 
            I0=>ID_3_1_busQ );
  GATE_ni_nires_reg_new_cnt_0_bus_AR_I_1:   INV port map ( I0=>ni_nires_reg_clear_n_iQ, 
            O=>ni_nires_reg_new_cnt_0_bus_AR );
  GATE_ID_3_0_bus_D_I_1:   INV port map ( I0=>ID_3_0_busQ, 
            O=>ID_3_0_bus_D );
  GATE_ni_nires_reg_gray_cntf_0_bus_D_I_1:   INV port map ( I0=>ni_nires_reg_gray_cntf_1_busQ, 
            O=>ni_nires_reg_gray_cntf_0_bus_D );
  GATE_ni_nires_reg_gray_cntf_0_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_gray_cntf_0_bus_C );
  GATE_ni_nires_reg_gray_cntf_0_bus_AR_I_1:   INV port map ( I0=>ni_nires_reg_clear_n_iQ, 
            O=>ni_nires_reg_gray_cntf_0_bus_AR );
  GATE_T_6_I_1:   AND3 port map ( O=>T_6, 
            I2=>j2c_bitcnt_1_busQ, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_j2c_reg_clear_C_I_1:   INV port map ( I0=>jTCKPIN, 
            O=>j2c_reg_clear_C );
  GATE_ni_nires_reg_gray_cntf_1_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_gray_cntf_1_bus_C );
  GATE_ni_nires_reg_gray_cntf_1_bus_AR_I_1:   INV port map ( I0=>ni_nires_reg_clear_n_iQ, 
            O=>ni_nires_reg_gray_cntf_1_bus_AR );
  GATE_ni_nires_reg_clear_n_i_D_I_1:   AND2 port map ( O=>ni_nires_reg_clear_n_i_D, 
            I1=>j2c_reg_rstout_n_iQ, 
            I0=>reset_nPIN );
  GATE_j2c_reg_rstout_n_i_D_I_1:   AND3 port map ( O=>j2c_reg_rstout_n_i_D, 
            I2=>j2c_bitcnt_1_busQ, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_j2c_reg_rstout_n_i_C_I_1:   INV port map ( I0=>jTCKPIN, 
            O=>j2c_reg_rstout_n_i_C );
  GATE_j2c_bitcnt_2_bus_D_I_1:   OR3 port map ( O=>j2c_bitcnt_2_bus_D, 
            I2=>T_138, 
            I1=>T_137, 
            I0=>T_139 );
  GATE_j2c_bitcnt_2_bus_C_I_1:   INV port map ( I0=>jTCKPIN, 
            O=>j2c_bitcnt_2_bus_C );
  GATE_nx1717_I_1:   OR2 port map ( O=>nx1717, 
            I1=>T_178, 
            I0=>ix1160 );
  GATE_j2c_bitcnt_1_bus_D_I_1:   XOR2 port map ( O=>j2c_bitcnt_1_bus_D, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_j2c_bitcnt_1_bus_C_I_1:   INV port map ( I0=>jTCKPIN, 
            O=>j2c_bitcnt_1_bus_C );
  GATE_j2c_bitcnt_0_bus_D_I_1:   INV port map ( I0=>j2c_bitcnt_0_busQ, 
            O=>j2c_bitcnt_0_bus_D );
  GATE_j2c_bitcnt_0_bus_C_I_1:   INV port map ( I0=>jTCKPIN, 
            O=>j2c_bitcnt_0_bus_C );
  GATE_nx1725_I_1:   OR3 port map ( O=>nx1725, 
            I2=>T_518, 
            I1=>T_135, 
            I0=>T_517 );
  GATE_ID_2_5_bus_T_I_1:   AND3 port map ( O=>ID_2_5_bus_T, 
            I2=>T_540, 
            I1=>ID_2_0_busQ, 
            I0=>T_539 );
  GATE_ni_reg_ce_prty_bit_neg_D_X1_I_1:   OR4 port map ( I0=>T_7, 
            I1=>T_8, 
            O=>ni_reg_ce_prty_bit_neg_D_X1, 
            I2=>T_9, 
            I3=>T_10 );
  GATE_ni_reg_ce_prty_bit_neg_D_X2_I_1:   AND2 port map ( O=>ni_reg_ce_prty_bit_neg_D_X2, 
            I1=>TX_ENQ, 
            I0=>GATE_ni_reg_ce_prty_bit_neg_D_X2_A );
  GATE_ni_reg_ce_prty_bit_neg_D_X2_I_2:   INV port map ( O=>GATE_ni_reg_ce_prty_bit_neg_D_X2_A, 
            I0=>TXD_8XQ );
  GATE_ni_reg_prty_bit_neg_r_D_I_1:   OR4 port map ( I0=>T_130, 
            I1=>T_516, 
            O=>ni_reg_prty_bit_neg_r_D, 
            I2=>T_515, 
            I3=>T_514 );
  GATE_ni_nires_reg_old_cnt_0_bus_D_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>ni_nires_reg_old_cnt_0_bus_D );
  GATE_ni_nires_reg_old_cnt_0_bus_AR_I_1:   INV port map ( I0=>ni_nires_reg_clear_n_iQ, 
            O=>ni_nires_reg_old_cnt_0_bus_AR );
  GATE_ni_nires_reg_old_cnt_0_bus_CE_I_1:   OR4 port map ( I0=>T_114, 
            I1=>T_115, 
            O=>ni_nires_reg_old_cnt_0_bus_CE, 
            I2=>T_116, 
            I3=>T_117 );
  GATE_nx1759_I_1:   OR3 port map ( O=>nx1759, 
            I2=>T_627, 
            I1=>T_294, 
            I0=>T_626 );
  GATE_ni_nires_reg_old_cnt_1_bus_AR_I_1:   INV port map ( I0=>ni_nires_reg_clear_n_iQ, 
            O=>ni_nires_reg_old_cnt_1_bus_AR );
  GATE_ix1771_X1_I_1:   OR4 port map ( I0=>T_11, 
            I1=>T_12, 
            O=>ix1771_X1, 
            I2=>T_13, 
            I3=>T_14 );
  GATE_ix1773_I_1:   XOR2 port map ( O=>ix1773, 
            I1=>TXD_11XQ, 
            I0=>TXD_12XQ );
  GATE_ix1775_I_1:   XOR2 port map ( O=>ix1775, 
            I1=>TXD_9XQ, 
            I0=>TXD_10XQ );
  GATE_ni_nires_reg_new_cnt_1_bus_AR_I_1:   INV port map ( I0=>ni_nires_reg_clear_n_iQ, 
            O=>ni_nires_reg_new_cnt_1_bus_AR );
  GATE_TXD_4X_CE_I_1:   OR2 port map ( O=>TXD_4X_CE, 
            I1=>T_353, 
            I0=>T_352 );
  GATE_ni_nires_reg_data_out_1_bus_D_I_1:   OR4 port map ( I0=>T_110, 
            I1=>T_111, 
            O=>ni_nires_reg_data_out_1_bus_D, 
            I2=>T_112, 
            I3=>T_113 );
  GATE_ID_2_6_bus_T_I_1:   AND3 port map ( O=>ID_2_6_bus_T, 
            I2=>T_512, 
            I1=>T_513, 
            I0=>T_511 );
  GATE_ni_nires_reg_data3neg_1_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data3neg_1_bus_C );
  GATE_ni_nires_reg_data3neg_1_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3neg_1_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>GATE_ni_nires_reg_data3neg_1_bus_CE_A );
  GATE_ni_nires_reg_data3neg_1_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3neg_1_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ID_2_4_bus_D_X2_I_1:   AND4 port map ( O=>ID_2_4_bus_D_X2, 
            I3=>ID_2_0_busQ, 
            I2=>ID_2_1_busQ, 
            I1=>ID_2_2_busQ, 
            I0=>ID_2_3_busQ );
  GATE_ni_nires_reg_data1neg_1_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data1neg_1_bus_C );
  GATE_ni_nires_reg_data1neg_1_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1neg_1_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_0_busQ, 
            I0=>GATE_ni_nires_reg_data1neg_1_bus_CE_A );
  GATE_ni_nires_reg_data1neg_1_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1neg_1_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_1_busQ );
  GATE_ID_2_3_bus_D_I_1:   OR4 port map ( I0=>T_106, 
            I1=>T_107, 
            O=>ID_2_3_bus_D, 
            I2=>T_108, 
            I3=>T_109 );
  GATE_ID_2_2_bus_D_I_1:   OR3 port map ( O=>ID_2_2_bus_D, 
            I2=>T_104, 
            I1=>T_103, 
            I0=>T_105 );
  GATE_ni_nires_reg_data0neg_1_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data0neg_1_bus_C );
  GATE_ni_nires_reg_data0neg_1_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0neg_1_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ID_2_1_bus_D_I_1:   XOR2 port map ( O=>ID_2_1_bus_D, 
            I1=>ID_2_0_busQ, 
            I0=>ID_2_1_busQ );
  GATE_ID_2_0_bus_D_I_1:   INV port map ( I0=>ID_2_0_busQ, 
            O=>ID_2_0_bus_D );
  GATE_ni_nires_reg_data2neg_1_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data2neg_1_bus_C );
  GATE_ni_nires_reg_data2neg_1_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2neg_1_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_nx1815_X1_I_1:   OR3 port map ( O=>nx1815_X1, 
            I2=>T_316, 
            I1=>T_315, 
            I0=>T_317 );
  GATE_nx1815_X2_I_1:   AND2 port map ( O=>nx1815_X2, 
            I1=>ix1160, 
            I0=>GATE_nx1815_X2_A );
  GATE_nx1815_X2_I_2:   INV port map ( O=>GATE_nx1815_X2_A, 
            I0=>ni_nires_reg_data_out_17_busQ );
  GATE_ni_nires_reg_data_out_0_bus_D_I_1:   OR4 port map ( I0=>T_99, 
            I1=>T_100, 
            O=>ni_nires_reg_data_out_0_bus_D, 
            I2=>T_101, 
            I3=>T_102 );
  GATE_ni_nires_reg_data3neg_0_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data3neg_0_bus_C );
  GATE_ni_nires_reg_data3neg_0_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3neg_0_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>GATE_ni_nires_reg_data3neg_0_bus_CE_A );
  GATE_ni_nires_reg_data3neg_0_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3neg_0_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data1neg_0_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data1neg_0_bus_C );
  GATE_ni_nires_reg_data1neg_0_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1neg_0_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_0_busQ, 
            I0=>GATE_ni_nires_reg_data1neg_0_bus_CE_A );
  GATE_ni_nires_reg_data1neg_0_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1neg_0_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_1_busQ );
  GATE_ni_nires_reg_data0neg_0_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data0neg_0_bus_C );
  GATE_ni_nires_reg_data0neg_0_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0neg_0_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data2neg_0_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data2neg_0_bus_C );
  GATE_ni_nires_reg_data2neg_0_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2neg_0_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_j2c_reg_creg0hm_4_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg0hm_4_bus_C );
  GATE_j2c_reg_creg0hm_4_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg0hm_4_bus_CE_A );
  GATE_j2c_reg_creg0hm_4_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg0hm_4_bus_CE_B );
  GATE_j2c_reg_creg0hm_4_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg0hm_4_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg0hm_4_bus_CE_A, 
            I1=>GATE_j2c_reg_creg0hm_4_bus_CE_B );
  GATE_j2c_reg_creg0hm_4_bus_AR_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg0hm_4_bus_AR );
  GATE_nx1851_I_1:   OR4 port map ( I0=>T_302, 
            I1=>T_303, 
            O=>nx1851, 
            I2=>T_304, 
            I3=>T_305 );
  GATE_j2c_reg_creg0hm_6_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg0hm_6_bus_C );
  GATE_j2c_reg_creg0hm_6_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg0hm_6_bus_CE_A );
  GATE_j2c_reg_creg0hm_6_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg0hm_6_bus_CE_B );
  GATE_j2c_reg_creg0hm_6_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg0hm_6_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg0hm_6_bus_CE_A, 
            I1=>GATE_j2c_reg_creg0hm_6_bus_CE_B );
  GATE_j2c_reg_creg0hm_6_bus_AP_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg0hm_6_bus_AP );
  GATE_j2c_reg_creg0hm_5_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg0hm_5_bus_C );
  GATE_j2c_reg_creg0hm_5_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg0hm_5_bus_CE_A );
  GATE_j2c_reg_creg0hm_5_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg0hm_5_bus_CE_B );
  GATE_j2c_reg_creg0hm_5_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg0hm_5_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg0hm_5_bus_CE_A, 
            I1=>GATE_j2c_reg_creg0hm_5_bus_CE_B );
  GATE_j2c_reg_creg0hm_5_bus_AR_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg0hm_5_bus_AR );
  GATE_nx1912_I_1:   OR4 port map ( I0=>T_731, 
            I1=>T_730, 
            O=>nx1912, 
            I2=>T_729, 
            I3=>T_728 );
  GATE_j2c_reg_creg0hm_2_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg0hm_2_bus_C );
  GATE_j2c_reg_creg0hm_2_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg0hm_2_bus_CE_A );
  GATE_j2c_reg_creg0hm_2_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg0hm_2_bus_CE_B );
  GATE_j2c_reg_creg0hm_2_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg0hm_2_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg0hm_2_bus_CE_A, 
            I1=>GATE_j2c_reg_creg0hm_2_bus_CE_B );
  GATE_j2c_reg_creg0hm_2_bus_AR_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg0hm_2_bus_AR );
  GATE_ID_0_6_bus_T_I_1:   AND3 port map ( O=>ID_0_6_bus_T, 
            I2=>T_509, 
            I1=>T_510, 
            I0=>T_508 );
  GATE_ID_0_5_bus_T_I_1:   AND3 port map ( O=>ID_0_5_bus_T, 
            I2=>T_507, 
            I1=>ID_0_0_busQ, 
            I0=>T_506 );
  GATE_j2c_reg_creg0hm_1_bus_D_I_1:   OR4 port map ( I0=>T_95, 
            I1=>T_96, 
            O=>j2c_reg_creg0hm_1_bus_D, 
            I2=>T_97, 
            I3=>T_98 );
  GATE_j2c_reg_creg0hm_1_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg0hm_1_bus_C );
  GATE_j2c_reg_creg0hm_1_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg0hm_1_bus_CE_A );
  GATE_j2c_reg_creg0hm_1_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg0hm_1_bus_CE_B );
  GATE_j2c_reg_creg0hm_1_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg0hm_1_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg0hm_1_bus_CE_A, 
            I1=>GATE_j2c_reg_creg0hm_1_bus_CE_B );
  GATE_j2c_reg_creg0hm_1_bus_AP_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg0hm_1_bus_AP );
  GATE_ID_0_4_bus_D_X2_I_1:   AND4 port map ( O=>ID_0_4_bus_D_X2, 
            I3=>ID_0_0_busQ, 
            I2=>ID_0_1_busQ, 
            I1=>ID_0_2_busQ, 
            I0=>ID_0_3_busQ );
  GATE_ID_0_3_bus_D_I_1:   OR4 port map ( I0=>T_91, 
            I1=>T_92, 
            O=>ID_0_3_bus_D, 
            I2=>T_93, 
            I3=>T_94 );
  GATE_ID_0_2_bus_D_I_1:   OR3 port map ( O=>ID_0_2_bus_D, 
            I2=>T_89, 
            I1=>T_88, 
            I0=>T_90 );
  GATE_ID_0_1_bus_D_I_1:   XOR2 port map ( O=>ID_0_1_bus_D, 
            I1=>ID_0_0_busQ, 
            I0=>ID_0_1_busQ );
  GATE_ID_0_0_bus_D_I_1:   INV port map ( I0=>ID_0_0_busQ, 
            O=>ID_0_0_bus_D );
  GATE_ix373_X1_I_1:   OR4 port map ( I0=>T_424, 
            I1=>T_425, 
            O=>ix373_X1, 
            I2=>T_426, 
            I3=>T_427 );
  GATE_j2c_reg_creg0hm_3_bus_D_I_1:   OR4 port map ( I0=>T_84, 
            I1=>T_85, 
            O=>j2c_reg_creg0hm_3_bus_D, 
            I2=>T_86, 
            I3=>T_87 );
  GATE_j2c_reg_creg0hm_3_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg0hm_3_bus_C );
  GATE_j2c_reg_creg0hm_3_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg0hm_3_bus_CE_A );
  GATE_j2c_reg_creg0hm_3_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg0hm_3_bus_CE_B );
  GATE_j2c_reg_creg0hm_3_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg0hm_3_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg0hm_3_bus_CE_A, 
            I1=>GATE_j2c_reg_creg0hm_3_bus_CE_B );
  GATE_j2c_reg_creg0hm_3_bus_AP_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg0hm_3_bus_AP );
  GATE_nx1909_I_1:   OR2 port map ( O=>nx1909, 
            I1=>T_351, 
            I0=>T_350 );
  GATE_ix385_X1_I_1:   OR4 port map ( I0=>T_420, 
            I1=>T_421, 
            O=>ix385_X1, 
            I2=>T_422, 
            I3=>T_423 );
  GATE_j2c_reg_creg0hm_0_bus_D_I_1:   OR4 port map ( I0=>T_80, 
            I1=>T_81, 
            O=>j2c_reg_creg0hm_0_bus_D, 
            I2=>T_82, 
            I3=>T_83 );
  GATE_j2c_reg_creg0hm_0_bus_C_I_1:   INV port map ( I0=>j2c_reg_clear_AR, 
            O=>j2c_reg_creg0hm_0_bus_C );
  GATE_j2c_reg_creg0hm_0_bus_CE_I_1:   INV port map ( I0=>j2c_reg_cmdreg_0_busQ, 
            O=>GATE_j2c_reg_creg0hm_0_bus_CE_A );
  GATE_j2c_reg_creg0hm_0_bus_CE_I_2:   INV port map ( I0=>jTDIPIN, 
            O=>GATE_j2c_reg_creg0hm_0_bus_CE_B );
  GATE_j2c_reg_creg0hm_0_bus_CE_I_3:   AND3 port map ( O=>j2c_reg_creg0hm_0_bus_CE, 
            I0=>j2c_reg_cmdreg_3_busQ, 
            I2=>GATE_j2c_reg_creg0hm_0_bus_CE_A, 
            I1=>GATE_j2c_reg_creg0hm_0_bus_CE_B );
  GATE_j2c_reg_creg0hm_0_bus_AP_I_1:   INV port map ( I0=>reset_nPIN, 
            O=>j2c_reg_creg0hm_0_bus_AP );
  GATE_ix397_X1_I_1:   OR4 port map ( I0=>T_416, 
            I1=>T_417, 
            O=>ix397_X1, 
            I2=>T_418, 
            I3=>T_419 );
  GATE_ID_0_7_bus_T_I_1:   AND4 port map ( O=>ID_0_7_bus_T, 
            I3=>T_503, 
            I2=>T_504, 
            I1=>T_505, 
            I0=>ID_0_0_busQ );
  GATE_ID_1_4_bus_T_I_1:   AND3 port map ( O=>ID_1_4_bus_T, 
            I2=>T_498, 
            I1=>ID_1_0_busQ, 
            I0=>T_497 );
  GATE_ID_1_3_bus_D_X2_I_1:   AND4 port map ( O=>ID_1_3_bus_D_X2, 
            I3=>nx1361, 
            I2=>ID_1_0_busQ, 
            I1=>ID_1_1_busQ, 
            I0=>ID_1_2_busQ );
  GATE_ID_1_2_bus_D_I_1:   OR4 port map ( I0=>T_76, 
            I1=>T_77, 
            O=>ID_1_2_bus_D, 
            I2=>T_78, 
            I3=>T_79 );
  GATE_nx1949_I_1:   OR2 port map ( O=>nx1949, 
            I1=>T_301, 
            I0=>T_300 );
  GATE_ni_nires_reg_data_out_2_bus_D_I_1:   OR4 port map ( I0=>T_72, 
            I1=>T_73, 
            O=>ni_nires_reg_data_out_2_bus_D, 
            I2=>T_74, 
            I3=>T_75 );
  GATE_ID_1_1_bus_D_I_1:   OR3 port map ( O=>ID_1_1_bus_D, 
            I2=>T_70, 
            I1=>T_69, 
            I0=>T_71 );
  GATE_ni_nires_reg_data3neg_2_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data3neg_2_bus_C );
  GATE_ni_nires_reg_data3neg_2_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3neg_2_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>GATE_ni_nires_reg_data3neg_2_bus_CE_A );
  GATE_ni_nires_reg_data3neg_2_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3neg_2_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ID_1_0_bus_D_I_1:   XOR2 port map ( O=>ID_1_0_bus_D, 
            I1=>ID_1_0_busQ, 
            I0=>nx1361 );
  GATE_ni_nires_reg_data1neg_2_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data1neg_2_bus_C );
  GATE_ni_nires_reg_data1neg_2_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1neg_2_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_0_busQ, 
            I0=>GATE_ni_nires_reg_data1neg_2_bus_CE_A );
  GATE_ni_nires_reg_data1neg_2_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1neg_2_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_1_busQ );
  GATE_ni_nires_reg_data0neg_2_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data0neg_2_bus_C );
  GATE_ni_nires_reg_data0neg_2_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0neg_2_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data2neg_2_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data2neg_2_bus_C );
  GATE_ni_nires_reg_data2neg_2_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2neg_2_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_nx1967_I_1:   OR3 port map ( O=>nx1967, 
            I2=>T_313, 
            I1=>nx1271, 
            I0=>T_314 );
  GATE_ni_nires_reg_data_out_3_bus_D_I_1:   OR4 port map ( I0=>T_65, 
            I1=>T_66, 
            O=>ni_nires_reg_data_out_3_bus_D, 
            I2=>T_67, 
            I3=>T_68 );
  GATE_ni_nires_reg_data3neg_3_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data3neg_3_bus_C );
  GATE_ni_nires_reg_data3neg_3_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3neg_3_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>GATE_ni_nires_reg_data3neg_3_bus_CE_A );
  GATE_ni_nires_reg_data3neg_3_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3neg_3_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data1neg_3_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data1neg_3_bus_C );
  GATE_ni_nires_reg_data1neg_3_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1neg_3_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_0_busQ, 
            I0=>GATE_ni_nires_reg_data1neg_3_bus_CE_A );
  GATE_ni_nires_reg_data1neg_3_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1neg_3_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_1_busQ );
  GATE_ni_nires_reg_data0neg_3_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data0neg_3_bus_C );
  GATE_ni_nires_reg_data0neg_3_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0neg_3_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data2neg_3_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data2neg_3_bus_C );
  GATE_ni_nires_reg_data2neg_3_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2neg_3_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ID_1_5_bus_T_I_1:   AND3 port map ( O=>ID_1_5_bus_T, 
            I2=>T_495, 
            I1=>T_496, 
            I0=>T_494 );
  GATE_ID_1_6_bus_T_I_1:   AND4 port map ( O=>ID_1_6_bus_T, 
            I3=>T_491, 
            I2=>T_492, 
            I1=>T_493, 
            I0=>ID_1_5_busQ );
  GATE_ni_nires_reg_data_out_4_bus_D_I_1:   OR4 port map ( I0=>T_61, 
            I1=>T_62, 
            O=>ni_nires_reg_data_out_4_bus_D, 
            I2=>T_63, 
            I3=>T_64 );
  GATE_ni_nires_reg_data3neg_4_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data3neg_4_bus_C );
  GATE_ni_nires_reg_data3neg_4_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3neg_4_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>GATE_ni_nires_reg_data3neg_4_bus_CE_A );
  GATE_ni_nires_reg_data3neg_4_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3neg_4_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data1neg_4_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data1neg_4_bus_C );
  GATE_ni_nires_reg_data1neg_4_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1neg_4_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_0_busQ, 
            I0=>GATE_ni_nires_reg_data1neg_4_bus_CE_A );
  GATE_ni_nires_reg_data1neg_4_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1neg_4_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_1_busQ );
  GATE_ni_nires_reg_data0neg_4_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data0neg_4_bus_C );
  GATE_ni_nires_reg_data0neg_4_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0neg_4_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data2neg_4_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data2neg_4_bus_C );
  GATE_ni_nires_reg_data2neg_4_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2neg_4_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data_out_5_bus_D_I_1:   OR4 port map ( I0=>T_57, 
            I1=>T_58, 
            O=>ni_nires_reg_data_out_5_bus_D, 
            I2=>T_59, 
            I3=>T_60 );
  GATE_ni_nires_reg_data3neg_5_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data3neg_5_bus_C );
  GATE_ni_nires_reg_data3neg_5_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3neg_5_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>GATE_ni_nires_reg_data3neg_5_bus_CE_A );
  GATE_ni_nires_reg_data3neg_5_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3neg_5_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data1neg_5_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data1neg_5_bus_C );
  GATE_ni_nires_reg_data1neg_5_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1neg_5_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_0_busQ, 
            I0=>GATE_ni_nires_reg_data1neg_5_bus_CE_A );
  GATE_ni_nires_reg_data1neg_5_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1neg_5_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_1_busQ );
  GATE_ni_nires_reg_data0neg_5_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data0neg_5_bus_C );
  GATE_ni_nires_reg_data0neg_5_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0neg_5_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data2neg_5_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data2neg_5_bus_C );
  GATE_ni_nires_reg_data2neg_5_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2neg_5_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data_out_6_bus_D_I_1:   OR4 port map ( I0=>T_53, 
            I1=>T_54, 
            O=>ni_nires_reg_data_out_6_bus_D, 
            I2=>T_55, 
            I3=>T_56 );
  GATE_ni_nires_reg_data3neg_6_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data3neg_6_bus_C );
  GATE_ni_nires_reg_data3neg_6_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3neg_6_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>GATE_ni_nires_reg_data3neg_6_bus_CE_A );
  GATE_ni_nires_reg_data3neg_6_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3neg_6_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data1neg_6_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data1neg_6_bus_C );
  GATE_ni_nires_reg_data1neg_6_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1neg_6_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_0_busQ, 
            I0=>GATE_ni_nires_reg_data1neg_6_bus_CE_A );
  GATE_ni_nires_reg_data1neg_6_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1neg_6_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_1_busQ );
  GATE_ni_nires_reg_data0neg_6_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data0neg_6_bus_C );
  GATE_ni_nires_reg_data0neg_6_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0neg_6_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data2neg_6_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data2neg_6_bus_C );
  GATE_ni_nires_reg_data2neg_6_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2neg_6_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data_out_7_bus_D_I_1:   OR4 port map ( I0=>T_49, 
            I1=>T_50, 
            O=>ni_nires_reg_data_out_7_bus_D, 
            I2=>T_51, 
            I3=>T_52 );
  GATE_ni_nires_reg_data3neg_7_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data3neg_7_bus_C );
  GATE_ni_nires_reg_data3neg_7_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3neg_7_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>GATE_ni_nires_reg_data3neg_7_bus_CE_A );
  GATE_ni_nires_reg_data3neg_7_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3neg_7_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data1neg_7_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data1neg_7_bus_C );
  GATE_ni_nires_reg_data1neg_7_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1neg_7_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_0_busQ, 
            I0=>GATE_ni_nires_reg_data1neg_7_bus_CE_A );
  GATE_ni_nires_reg_data1neg_7_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1neg_7_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_1_busQ );
  GATE_ni_nires_reg_data0neg_7_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data0neg_7_bus_C );
  GATE_ni_nires_reg_data0neg_7_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0neg_7_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data2neg_7_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data2neg_7_bus_C );
  GATE_ni_nires_reg_data2neg_7_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2neg_7_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data_out_8_bus_D_I_1:   OR4 port map ( I0=>T_45, 
            I1=>T_46, 
            O=>ni_nires_reg_data_out_8_bus_D, 
            I2=>T_47, 
            I3=>T_48 );
  GATE_ni_nires_reg_data3neg_8_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data3neg_8_bus_C );
  GATE_ni_nires_reg_data3neg_8_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3neg_8_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>GATE_ni_nires_reg_data3neg_8_bus_CE_A );
  GATE_ni_nires_reg_data3neg_8_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3neg_8_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data1neg_8_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data1neg_8_bus_C );
  GATE_ni_nires_reg_data1neg_8_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1neg_8_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_0_busQ, 
            I0=>GATE_ni_nires_reg_data1neg_8_bus_CE_A );
  GATE_ni_nires_reg_data1neg_8_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1neg_8_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_1_busQ );
  GATE_ni_nires_reg_data0neg_8_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data0neg_8_bus_C );
  GATE_ni_nires_reg_data0neg_8_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0neg_8_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data2neg_8_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data2neg_8_bus_C );
  GATE_ni_nires_reg_data2neg_8_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2neg_8_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data_out_9_bus_D_I_1:   OR4 port map ( I0=>T_41, 
            I1=>T_42, 
            O=>ni_nires_reg_data_out_9_bus_D, 
            I2=>T_43, 
            I3=>T_44 );
  GATE_ni_nires_reg_data3neg_9_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data3neg_9_bus_C );
  GATE_ni_nires_reg_data3neg_9_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3neg_9_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>GATE_ni_nires_reg_data3neg_9_bus_CE_A );
  GATE_ni_nires_reg_data3neg_9_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3neg_9_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data1neg_9_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data1neg_9_bus_C );
  GATE_ni_nires_reg_data1neg_9_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1neg_9_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_0_busQ, 
            I0=>GATE_ni_nires_reg_data1neg_9_bus_CE_A );
  GATE_ni_nires_reg_data1neg_9_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1neg_9_bus_CE_A, 
            I0=>ni_nires_reg_gray_cntf_1_busQ );
  GATE_ni_nires_reg_data0neg_9_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data0neg_9_bus_C );
  GATE_ni_nires_reg_data0neg_9_bus_CE_I_1:   NOR2 port map ( O=>ni_nires_reg_data0neg_9_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ni_nires_reg_data2neg_9_bus_C_I_1:   INV port map ( I0=>NI_STRPIN, 
            O=>ni_nires_reg_data2neg_9_bus_C );
  GATE_ni_nires_reg_data2neg_9_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data2neg_9_bus_CE, 
            I1=>ni_nires_reg_gray_cntf_1_busQ, 
            I0=>ni_nires_reg_gray_cntf_0_busQ );
  GATE_ix1084_I_1:   OR4 port map ( I0=>T_455, 
            I1=>T_456, 
            O=>ix1084, 
            I2=>T_457, 
            I3=>T_458 );
  GATE_nx2210_I_1:   OR3 port map ( O=>nx2210, 
            I2=>T_548, 
            I1=>T_177, 
            I0=>T_547 );
  GATE_ni_nires_reg_data_out_11_bus_D_I_1:   OR4 port map ( I0=>T_37, 
            I1=>T_38, 
            O=>ni_nires_reg_data_out_11_bus_D, 
            I2=>T_39, 
            I3=>T_40 );
  GATE_ni_nires_reg_data3pos_1_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data3pos_1_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_1_busQ, 
            I0=>GATE_ni_nires_reg_data3pos_1_bus_CE_A );
  GATE_ni_nires_reg_data3pos_1_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data3pos_1_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_0_busQ );
  GATE_ni_nires_reg_gray_cnt_1_bus_AR_I_1:   INV port map ( I0=>ni_nires_reg_clear_n_iQ, 
            O=>ni_nires_reg_gray_cnt_1_bus_AR );
  GATE_ni_nires_reg_gray_cnt_0_bus_D_I_1:   INV port map ( I0=>ni_nires_reg_gray_cnt_1_busQ, 
            O=>ni_nires_reg_gray_cnt_0_bus_D );
  GATE_ni_nires_reg_gray_cnt_0_bus_AR_I_1:   INV port map ( I0=>ni_nires_reg_clear_n_iQ, 
            O=>ni_nires_reg_gray_cnt_0_bus_AR );
  GATE_ix1160_I_1:   OR4 port map ( I0=>T_451, 
            I1=>T_452, 
            O=>ix1160, 
            I2=>T_453, 
            I3=>T_454 );
  GATE_ni_nires_reg_data1pos_1_bus_CE_I_1:   AND2 port map ( O=>ni_nires_reg_data1pos_1_bus_CE, 
            I1=>ni_nires_reg_gray_cnt_0_busQ, 
            I0=>GATE_ni_nires_reg_data1pos_1_bus_CE_A );
  GATE_ni_nires_reg_data1pos_1_bus_CE_I_2:   INV port map ( O=>GATE_ni_nires_reg_data1pos_1_bus_CE_A, 
            I0=>ni_nires_reg_gray_cnt_1_busQ );
  GATE_ix1164_I_1:   OR4 port map ( I0=>T_447, 
            I1=>T_448, 
            O=>ix1164, 
            I2=>T_449, 
            I3=>T_450 );
  GATE_ID_3_5_X0_I_1:   NAN2 port map ( O=>ID_3_5_X0, 
            I0=>ni_reg_ce_prty_bit_posQ, 
            I1=>GATE_ID_3_5_X0_A );
  GATE_ID_3_5_X0_I_2:   INV port map ( O=>GATE_ID_3_5_X0_A, 
            I0=>T_191 );
  GATE_j2c_reg_clear_CE_I_1:   OR2 port map ( O=>j2c_reg_clear_CE, 
            I1=>T_141, 
            I0=>T_140 );
  GATE_ID_2_5_X0_I_1:   NAN2 port map ( O=>ID_2_5_X0, 
            I0=>ni_reg_ce_prty_bit_negQ, 
            I1=>GATE_ID_2_5_X0_A );
  GATE_ID_2_5_X0_I_2:   INV port map ( O=>GATE_ID_2_5_X0_A, 
            I0=>T_136 );
  GATE_TXD_3X_D_I_1:   XOR2 port map ( O=>TXD_3X_D, 
            I1=>TXD_3X_D_X2, 
            I0=>TXD_3X_D_X1 );
  GATE_TXD_15X_D_I_1:   XOR2 port map ( O=>TXD_15X_D, 
            I1=>TXD_15X_D_X2, 
            I0=>TXD_15X_D_X1 );
  GATE_TXD_11X_D_I_1:   XOR2 port map ( O=>TXD_11X_D, 
            I1=>TXD_11X_D_X2, 
            I0=>TXD_11X_D_X1 );
  GATE_TXD_7X_D_I_1:   XOR2 port map ( O=>TXD_7X_D, 
            I1=>TXD_7X_D_X2, 
            I0=>TXD_7X_D_X1 );
  GATE_nx2272_I_1:   XOR2 port map ( O=>nx2272, 
            I1=>nx2272_X2, 
            I0=>nx2272_X1 );
  GATE_ix47_I_1:   XOR2 port map ( O=>GATE_ix47_Y, 
            I1=>ix47_X1, 
            I0=>j2c_reg_creg1hm_6_busQ );
  GATE_ix47_I_2:   INV port map ( O=>ix47, 
            I0=>GATE_ix47_Y );
  GATE_ix59_I_1:   XOR2 port map ( O=>GATE_ix59_Y, 
            I1=>ix59_X1, 
            I0=>j2c_reg_creg1hm_2_busQ );
  GATE_ix59_I_2:   INV port map ( O=>ix59, 
            I0=>GATE_ix59_Y );
  GATE_ix71_I_1:   XOR2 port map ( O=>GATE_ix71_Y, 
            I1=>ix71_X1, 
            I0=>j2c_reg_creg1hm_2_busQ );
  GATE_ix71_I_2:   INV port map ( O=>ix71, 
            I0=>GATE_ix71_Y );
  GATE_ix1641_I_1:   XOR2 port map ( O=>GATE_ix1641_Y, 
            I1=>ix1641_X1, 
            I0=>TXD_7XQ );
  GATE_ix1641_I_2:   INV port map ( O=>ix1641, 
            I0=>GATE_ix1641_Y );
  GATE_ix1647_I_1:   XOR2 port map ( O=>GATE_ix1647_Y, 
            I1=>ix1647_X1, 
            I0=>TXD_4XQ );
  GATE_ix1647_I_2:   INV port map ( O=>ix1647, 
            I0=>GATE_ix1647_Y );
  GATE_ni_pattcount_4_bus_D_I_1:   XOR2 port map ( O=>ni_pattcount_4_bus_D, 
            I1=>ni_pattcount_4_bus_D_X1, 
            I0=>ni_pattcount_4_busQ );
  GATE_ID_3_4_bus_D_I_1:   XOR2 port map ( O=>ID_3_4_bus_D, 
            I1=>ID_3_4_bus_D_X2, 
            I0=>ID_3_4_busQ );
  GATE_ni_reg_ce_prty_bit_neg_D_I_1:   XOR2 port map ( O=>ni_reg_ce_prty_bit_neg_D, 
            I1=>ni_reg_ce_prty_bit_neg_D_X2, 
            I0=>ni_reg_ce_prty_bit_neg_D_X1 );
  GATE_ix1771_I_1:   XOR2 port map ( O=>GATE_ix1771_Y, 
            I1=>ix1771_X1, 
            I0=>TXD_15XQ );
  GATE_ix1771_I_2:   INV port map ( O=>ix1771, 
            I0=>GATE_ix1771_Y );
  GATE_ID_2_4_bus_D_I_1:   XOR2 port map ( O=>ID_2_4_bus_D, 
            I1=>ID_2_4_bus_D_X2, 
            I0=>ID_2_4_busQ );
  GATE_nx1815_I_1:   XOR2 port map ( O=>nx1815, 
            I1=>nx1815_X2, 
            I0=>nx1815_X1 );
  GATE_ID_0_4_bus_D_I_1:   XOR2 port map ( O=>ID_0_4_bus_D, 
            I1=>ID_0_4_bus_D_X2, 
            I0=>ID_0_4_busQ );
  GATE_ix373_I_1:   XOR2 port map ( O=>GATE_ix373_Y, 
            I1=>ix373_X1, 
            I0=>j2c_reg_creg0hm_6_busQ );
  GATE_ix373_I_2:   INV port map ( O=>ix373, 
            I0=>GATE_ix373_Y );
  GATE_ix385_I_1:   XOR2 port map ( O=>GATE_ix385_Y, 
            I1=>ix385_X1, 
            I0=>j2c_reg_creg0hm_4_busQ );
  GATE_ix385_I_2:   INV port map ( O=>ix385, 
            I0=>GATE_ix385_Y );
  GATE_ix397_I_1:   XOR2 port map ( O=>GATE_ix397_Y, 
            I1=>ix397_X1, 
            I0=>j2c_reg_creg0hm_4_busQ );
  GATE_ix397_I_2:   INV port map ( O=>ix397, 
            I0=>GATE_ix397_Y );
  GATE_ID_1_3_bus_D_I_1:   XOR2 port map ( O=>ID_1_3_bus_D, 
            I1=>ID_1_3_bus_D_X2, 
            I0=>ID_1_3_busQ );
  GATE_ENABLE_I_1:   INV port map ( I0=>T_0, 
            O=>ENABLECOM );
  GATE_EN_I_1:   INV port map ( I0=>T_1, 
            O=>ENCOM );
  GATE_SD2ANL_I_1:   INV port map ( I0=>T_2, 
            O=>SD2ANLCOM );
  GATE_WP_EEP_I_1:   INV port map ( I0=>T_3, 
            O=>WP_EEPCOM );
  GATE_jTDO_I_1:   INV port map ( I0=>T_4, 
            O=>jTDOCOM );
  GATE_TX_EN_D_I_1:   INV port map ( I0=>T_5, 
            O=>TX_EN_D );
  GATE_ID_3_5_bus_CE_I_1:   INV port map ( I0=>ID_3_5_X0, 
            O=>ID_3_5_bus_CE );
  GATE_ID_3_6_bus_CE_I_1:   INV port map ( I0=>ID_3_5_X0, 
            O=>ID_3_6_bus_CE );
  GATE_ID_3_4_bus_CE_I_1:   INV port map ( I0=>ID_3_5_X0, 
            O=>ID_3_4_bus_CE );
  GATE_ID_3_3_bus_CE_I_1:   INV port map ( I0=>ID_3_5_X0, 
            O=>ID_3_3_bus_CE );
  GATE_ID_3_2_bus_CE_I_1:   INV port map ( I0=>ID_3_5_X0, 
            O=>ID_3_2_bus_CE );
  GATE_ID_3_1_bus_CE_I_1:   INV port map ( I0=>ID_3_5_X0, 
            O=>ID_3_1_bus_CE );
  GATE_ID_3_0_bus_CE_I_1:   INV port map ( I0=>ID_3_5_X0, 
            O=>ID_3_0_bus_CE );
  GATE_j2c_reg_clear_D_I_1:   INV port map ( I0=>T_6, 
            O=>j2c_reg_clear_D );
  GATE_ID_2_5_bus_CE_I_1:   INV port map ( I0=>ID_2_5_X0, 
            O=>ID_2_5_bus_CE );
  GATE_ID_2_6_bus_CE_I_1:   INV port map ( I0=>ID_2_5_X0, 
            O=>ID_2_6_bus_CE );
  GATE_ID_2_4_bus_CE_I_1:   INV port map ( I0=>ID_2_5_X0, 
            O=>ID_2_4_bus_CE );
  GATE_ID_2_3_bus_CE_I_1:   INV port map ( I0=>ID_2_5_X0, 
            O=>ID_2_3_bus_CE );
  GATE_ID_2_2_bus_CE_I_1:   INV port map ( I0=>ID_2_5_X0, 
            O=>ID_2_2_bus_CE );
  GATE_ID_2_1_bus_CE_I_1:   INV port map ( I0=>ID_2_5_X0, 
            O=>ID_2_1_bus_CE );
  GATE_ID_2_0_bus_CE_I_1:   INV port map ( I0=>ID_2_5_X0, 
            O=>ID_2_0_bus_CE );
  GATE_T_7_I_1:   NOR4 port map ( I0=>ix1775, 
            I1=>ix1771, 
            O=>T_7, 
            I2=>ix1773, 
            I3=>GATE_T_7_DN );
  GATE_T_7_I_2:   INV port map ( I0=>TX_ENQ, 
            O=>GATE_T_7_DN );
  GATE_T_8_I_1:   AND4 port map ( O=>T_8, 
            I3=>ix1773, 
            I2=>TX_ENQ, 
            I1=>ix1771, 
            I0=>GATE_T_8_A );
  GATE_T_8_I_2:   INV port map ( I0=>ix1775, 
            O=>GATE_T_8_A );
  GATE_T_9_I_1:   AND4 port map ( O=>T_9, 
            I3=>ix1771, 
            I2=>ix1775, 
            I1=>TX_ENQ, 
            I0=>GATE_T_9_A );
  GATE_T_9_I_2:   INV port map ( I0=>ix1773, 
            O=>GATE_T_9_A );
  GATE_T_10_I_1:   AND4 port map ( O=>T_10, 
            I3=>ix1773, 
            I2=>TX_ENQ, 
            I1=>ix1775, 
            I0=>GATE_T_10_A );
  GATE_T_10_I_2:   INV port map ( I0=>ix1771, 
            O=>GATE_T_10_A );
  GATE_T_11_I_1:   NOR3 port map ( O=>T_11, 
            I2=>TXD_13XQ, 
            I1=>TXD_14XQ, 
            I0=>ni_reg_prty_bit_neg_rQ );
  GATE_T_12_I_1:   INV port map ( I0=>ni_reg_prty_bit_neg_rQ, 
            O=>GATE_T_12_A );
  GATE_T_12_I_2:   AND3 port map ( O=>T_12, 
            I2=>TXD_13XQ, 
            I1=>TXD_14XQ, 
            I0=>GATE_T_12_A );
  GATE_T_13_I_1:   INV port map ( I0=>TXD_13XQ, 
            O=>GATE_T_13_A );
  GATE_T_13_I_2:   AND3 port map ( O=>T_13, 
            I2=>TXD_14XQ, 
            I1=>ni_reg_prty_bit_neg_rQ, 
            I0=>GATE_T_13_A );
  GATE_T_14_I_1:   INV port map ( I0=>TXD_14XQ, 
            O=>GATE_T_14_A );
  GATE_T_14_I_2:   AND3 port map ( O=>T_14, 
            I2=>TXD_13XQ, 
            I1=>ni_reg_prty_bit_neg_rQ, 
            I0=>GATE_T_14_A );
  GATE_T_15_I_1:   NOR4 port map ( I0=>ix1610, 
            I1=>ix1160, 
            O=>T_15, 
            I2=>nx1271, 
            I3=>GATE_T_15_DN );
  GATE_T_15_I_2:   INV port map ( I0=>ni_nires_reg_data_out_7_busQ, 
            O=>GATE_T_15_DN );
  GATE_T_16_I_3:   AND4 port map ( O=>T_16, 
            I3=>ix1160, 
            I2=>ni_nires_reg_data_out_8_busQ, 
            I1=>GATE_T_16_B, 
            I0=>GATE_T_16_A );
  GATE_T_16_I_2:   INV port map ( I0=>ix1610, 
            O=>GATE_T_16_B );
  GATE_T_16_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_16_A );
  GATE_T_17_I_1:   AND4 port map ( O=>T_17, 
            I3=>nx1717, 
            I2=>ix1610, 
            I1=>ni_nires_reg_data_out_9_busQ, 
            I0=>GATE_T_17_A );
  GATE_T_17_I_2:   INV port map ( I0=>nx1271, 
            O=>GATE_T_17_A );
  GATE_T_18_I_3:   AND4 port map ( O=>T_18, 
            I3=>ix1610, 
            I2=>ni_nires_reg_data_out_8_busQ, 
            I1=>GATE_T_18_B, 
            I0=>GATE_T_18_A );
  GATE_T_18_I_2:   INV port map ( I0=>nx1717, 
            O=>GATE_T_18_B );
  GATE_T_18_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_18_A );
  GATE_T_19_I_1:   AND2 port map ( O=>T_19, 
            I1=>nx1271, 
            I0=>TXD_7XQ );
  GATE_T_20_I_1:   AND3 port map ( O=>T_20, 
            I2=>T_481, 
            I1=>T_482, 
            I0=>T_480 );
  GATE_T_21_I_1:   NOR4 port map ( I0=>nx1595, 
            I1=>ix1160, 
            O=>T_21, 
            I2=>nx1271, 
            I3=>GATE_T_21_DN );
  GATE_T_21_I_2:   INV port map ( I0=>ni_nires_reg_data_out_13_busQ, 
            O=>GATE_T_21_DN );
  GATE_T_22_I_1:   NOR4 port map ( I0=>nx1595, 
            I1=>ix1084, 
            O=>T_22, 
            I2=>nx1271, 
            I3=>GATE_T_22_DN );
  GATE_T_22_I_2:   INV port map ( I0=>ni_nires_reg_data_out_13_busQ, 
            O=>GATE_T_22_DN );
  GATE_T_23_I_3:   AND4 port map ( O=>T_23, 
            I3=>ni_nires_reg_data_out_14_busQ, 
            I2=>ni_nires_reg_data_out_13_busQ, 
            I1=>GATE_T_23_B, 
            I0=>GATE_T_23_A );
  GATE_T_23_I_2:   INV port map ( I0=>nx1595, 
            O=>GATE_T_23_B );
  GATE_T_23_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_23_A );
  GATE_T_24_I_1:   INV port map ( I0=>nx1759, 
            O=>GATE_T_24_A );
  GATE_T_24_I_2:   INV port map ( I0=>nx1271, 
            O=>GATE_T_24_B );
  GATE_T_24_I_3:   AND3 port map ( O=>T_24, 
            I0=>nx1595, 
            I2=>GATE_T_24_A, 
            I1=>GATE_T_24_B );
  GATE_T_25_I_1:   AND2 port map ( O=>T_25, 
            I1=>nx1271, 
            I0=>TXD_11XQ );
  GATE_T_26_I_1:   NOR4 port map ( I0=>ix1610, 
            I1=>ix1160, 
            O=>T_26, 
            I2=>nx1271, 
            I3=>GATE_T_26_DN );
  GATE_T_26_I_2:   INV port map ( I0=>ni_nires_reg_data_out_17_busQ, 
            O=>GATE_T_26_DN );
  GATE_T_27_I_3:   AND4 port map ( O=>T_27, 
            I3=>ix1160, 
            I2=>ni_nires_reg_data_out_18_busQ, 
            I1=>GATE_T_27_B, 
            I0=>GATE_T_27_A );
  GATE_T_27_I_2:   INV port map ( I0=>ix1610, 
            O=>GATE_T_27_B );
  GATE_T_27_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_27_A );
  GATE_T_28_I_3:   AND4 port map ( O=>T_28, 
            I3=>ix1610, 
            I2=>ni_nires_reg_data_out_18_busQ, 
            I1=>GATE_T_28_B, 
            I0=>GATE_T_28_A );
  GATE_T_28_I_2:   INV port map ( I0=>nx1717, 
            O=>GATE_T_28_B );
  GATE_T_28_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_28_A );
  GATE_T_29_I_1:   AND4 port map ( O=>T_29, 
            I3=>nx1717, 
            I2=>ix1610, 
            I1=>ni_nires_reg_data_out_19_busQ, 
            I0=>GATE_T_29_A );
  GATE_T_29_I_2:   INV port map ( I0=>nx1271, 
            O=>GATE_T_29_A );
  GATE_T_30_I_1:   AND2 port map ( O=>T_30, 
            I1=>nx1271, 
            I0=>TXD_15XQ );
  GATE_T_31_I_1:   AND3 port map ( O=>T_31, 
            I2=>T_489, 
            I1=>T_490, 
            I0=>T_488 );
  GATE_T_32_I_1:   NOR4 port map ( I0=>nx1595, 
            I1=>ix1160, 
            O=>T_32, 
            I2=>nx1271, 
            I3=>GATE_T_32_DN );
  GATE_T_32_I_2:   INV port map ( I0=>ni_nires_reg_data_out_3_busQ, 
            O=>GATE_T_32_DN );
  GATE_T_33_I_1:   NOR4 port map ( I0=>nx1595, 
            I1=>ix1084, 
            O=>T_33, 
            I2=>nx1271, 
            I3=>GATE_T_33_DN );
  GATE_T_33_I_2:   INV port map ( I0=>ni_nires_reg_data_out_3_busQ, 
            O=>GATE_T_33_DN );
  GATE_T_34_I_3:   AND4 port map ( O=>T_34, 
            I3=>ni_nires_reg_data_out_4_busQ, 
            I2=>ni_nires_reg_data_out_3_busQ, 
            I1=>GATE_T_34_B, 
            I0=>GATE_T_34_A );
  GATE_T_34_I_2:   INV port map ( I0=>nx1595, 
            O=>GATE_T_34_B );
  GATE_T_34_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_34_A );
  GATE_T_35_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_35_A );
  GATE_T_35_I_2:   INV port map ( I0=>nx2236, 
            O=>GATE_T_35_B );
  GATE_T_35_I_3:   AND3 port map ( O=>T_35, 
            I0=>nx1595, 
            I2=>GATE_T_35_A, 
            I1=>GATE_T_35_B );
  GATE_T_36_I_1:   AND2 port map ( O=>T_36, 
            I1=>nx1271, 
            I0=>TXD_3XQ );
  GATE_T_37_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_37_A );
  GATE_T_37_I_2:   AND3 port map ( O=>T_37, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1pos_1_busQ, 
            I0=>GATE_T_37_A );
  GATE_T_38_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_38_A );
  GATE_T_38_I_2:   AND3 port map ( O=>T_38, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_data3pos_1_busQ, 
            I0=>GATE_T_38_A );
  GATE_T_39_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_39_A );
  GATE_T_39_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_39_B );
  GATE_T_39_I_3:   AND3 port map ( O=>T_39, 
            I0=>ni_nires_reg_data0pos_1_busQ, 
            I2=>GATE_T_39_A, 
            I1=>GATE_T_39_B );
  GATE_T_40_I_1:   AND3 port map ( O=>T_40, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data2pos_1_busQ, 
            I0=>ni_nires_reg_old_cnt_1_busQ );
  GATE_T_41_I_1:   AND3 port map ( O=>T_41, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_old_cnt_0_busQ, 
            I0=>ni_nires_reg_data2neg_9_busQ );
  GATE_T_42_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_42_A );
  GATE_T_42_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_42_B );
  GATE_T_42_I_3:   AND3 port map ( O=>T_42, 
            I0=>ni_nires_reg_data0neg_9_busQ, 
            I2=>GATE_T_42_A, 
            I1=>GATE_T_42_B );
  GATE_T_43_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_43_A );
  GATE_T_43_I_2:   AND3 port map ( O=>T_43, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1neg_9_busQ, 
            I0=>GATE_T_43_A );
  GATE_T_44_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_44_A );
  GATE_T_44_I_2:   AND3 port map ( O=>T_44, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_data3neg_9_busQ, 
            I0=>GATE_T_44_A );
  GATE_T_45_I_1:   AND3 port map ( O=>T_45, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_old_cnt_0_busQ, 
            I0=>ni_nires_reg_data2neg_8_busQ );
  GATE_T_46_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_46_A );
  GATE_T_46_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_46_B );
  GATE_T_46_I_3:   AND3 port map ( O=>T_46, 
            I0=>ni_nires_reg_data0neg_8_busQ, 
            I2=>GATE_T_46_A, 
            I1=>GATE_T_46_B );
  GATE_T_47_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_47_A );
  GATE_T_47_I_2:   AND3 port map ( O=>T_47, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1neg_8_busQ, 
            I0=>GATE_T_47_A );
  GATE_T_48_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_48_A );
  GATE_T_48_I_2:   AND3 port map ( O=>T_48, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_data3neg_8_busQ, 
            I0=>GATE_T_48_A );
  GATE_T_49_I_1:   AND3 port map ( O=>T_49, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_old_cnt_0_busQ, 
            I0=>ni_nires_reg_data2neg_7_busQ );
  GATE_T_50_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_50_A );
  GATE_T_50_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_50_B );
  GATE_T_50_I_3:   AND3 port map ( O=>T_50, 
            I0=>ni_nires_reg_data0neg_7_busQ, 
            I2=>GATE_T_50_A, 
            I1=>GATE_T_50_B );
  GATE_T_51_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_51_A );
  GATE_T_51_I_2:   AND3 port map ( O=>T_51, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1neg_7_busQ, 
            I0=>GATE_T_51_A );
  GATE_T_52_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_52_A );
  GATE_T_52_I_2:   AND3 port map ( O=>T_52, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_data3neg_7_busQ, 
            I0=>GATE_T_52_A );
  GATE_T_53_I_1:   AND3 port map ( O=>T_53, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_old_cnt_0_busQ, 
            I0=>ni_nires_reg_data2neg_6_busQ );
  GATE_T_54_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_54_A );
  GATE_T_54_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_54_B );
  GATE_T_54_I_3:   AND3 port map ( O=>T_54, 
            I0=>ni_nires_reg_data0neg_6_busQ, 
            I2=>GATE_T_54_A, 
            I1=>GATE_T_54_B );
  GATE_T_55_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_55_A );
  GATE_T_55_I_2:   AND3 port map ( O=>T_55, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1neg_6_busQ, 
            I0=>GATE_T_55_A );
  GATE_T_56_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_56_A );
  GATE_T_56_I_2:   AND3 port map ( O=>T_56, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_data3neg_6_busQ, 
            I0=>GATE_T_56_A );
  GATE_T_57_I_1:   AND3 port map ( O=>T_57, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_old_cnt_0_busQ, 
            I0=>ni_nires_reg_data2neg_5_busQ );
  GATE_T_58_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_58_A );
  GATE_T_58_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_58_B );
  GATE_T_58_I_3:   AND3 port map ( O=>T_58, 
            I0=>ni_nires_reg_data0neg_5_busQ, 
            I2=>GATE_T_58_A, 
            I1=>GATE_T_58_B );
  GATE_T_59_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_59_A );
  GATE_T_59_I_2:   AND3 port map ( O=>T_59, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1neg_5_busQ, 
            I0=>GATE_T_59_A );
  GATE_T_60_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_60_A );
  GATE_T_60_I_2:   AND3 port map ( O=>T_60, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_data3neg_5_busQ, 
            I0=>GATE_T_60_A );
  GATE_T_61_I_1:   AND3 port map ( O=>T_61, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_old_cnt_0_busQ, 
            I0=>ni_nires_reg_data2neg_4_busQ );
  GATE_T_62_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_62_A );
  GATE_T_62_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_62_B );
  GATE_T_62_I_3:   AND3 port map ( O=>T_62, 
            I0=>ni_nires_reg_data0neg_4_busQ, 
            I2=>GATE_T_62_A, 
            I1=>GATE_T_62_B );
  GATE_T_63_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_63_A );
  GATE_T_63_I_2:   AND3 port map ( O=>T_63, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1neg_4_busQ, 
            I0=>GATE_T_63_A );
  GATE_T_64_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_64_A );
  GATE_T_64_I_2:   AND3 port map ( O=>T_64, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_data3neg_4_busQ, 
            I0=>GATE_T_64_A );
  GATE_T_65_I_1:   AND3 port map ( O=>T_65, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_old_cnt_0_busQ, 
            I0=>ni_nires_reg_data2neg_3_busQ );
  GATE_T_66_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_66_A );
  GATE_T_66_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_66_B );
  GATE_T_66_I_3:   AND3 port map ( O=>T_66, 
            I0=>ni_nires_reg_data0neg_3_busQ, 
            I2=>GATE_T_66_A, 
            I1=>GATE_T_66_B );
  GATE_T_67_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_67_A );
  GATE_T_67_I_2:   AND3 port map ( O=>T_67, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1neg_3_busQ, 
            I0=>GATE_T_67_A );
  GATE_T_68_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_68_A );
  GATE_T_68_I_2:   AND3 port map ( O=>T_68, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_data3neg_3_busQ, 
            I0=>GATE_T_68_A );
  GATE_T_69_I_1:   INV port map ( I0=>ID_1_1_busQ, 
            O=>GATE_T_69_A );
  GATE_T_69_I_2:   AND3 port map ( O=>T_69, 
            I2=>ID_1_0_busQ, 
            I1=>nx1361, 
            I0=>GATE_T_69_A );
  GATE_T_70_I_1:   AND2 port map ( O=>T_70, 
            I1=>ID_1_1_busQ, 
            I0=>GATE_T_70_A );
  GATE_T_70_I_2:   INV port map ( O=>GATE_T_70_A, 
            I0=>ID_1_0_busQ );
  GATE_T_71_I_1:   AND2 port map ( O=>T_71, 
            I1=>ID_1_1_busQ, 
            I0=>GATE_T_71_A );
  GATE_T_71_I_2:   INV port map ( O=>GATE_T_71_A, 
            I0=>nx1361 );
  GATE_T_72_I_1:   AND3 port map ( O=>T_72, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_old_cnt_0_busQ, 
            I0=>ni_nires_reg_data2neg_2_busQ );
  GATE_T_73_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_73_A );
  GATE_T_73_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_73_B );
  GATE_T_73_I_3:   AND3 port map ( O=>T_73, 
            I0=>ni_nires_reg_data0neg_2_busQ, 
            I2=>GATE_T_73_A, 
            I1=>GATE_T_73_B );
  GATE_T_74_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_74_A );
  GATE_T_74_I_2:   AND3 port map ( O=>T_74, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1neg_2_busQ, 
            I0=>GATE_T_74_A );
  GATE_T_75_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_75_A );
  GATE_T_75_I_2:   AND3 port map ( O=>T_75, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_data3neg_2_busQ, 
            I0=>GATE_T_75_A );
  GATE_T_76_I_1:   AND4 port map ( O=>T_76, 
            I3=>nx1361, 
            I2=>ID_1_0_busQ, 
            I1=>ID_1_1_busQ, 
            I0=>GATE_T_76_A );
  GATE_T_76_I_2:   INV port map ( I0=>ID_1_2_busQ, 
            O=>GATE_T_76_A );
  GATE_T_77_I_1:   AND2 port map ( O=>T_77, 
            I1=>ID_1_2_busQ, 
            I0=>GATE_T_77_A );
  GATE_T_77_I_2:   INV port map ( O=>GATE_T_77_A, 
            I0=>ID_1_0_busQ );
  GATE_T_78_I_1:   AND2 port map ( O=>T_78, 
            I1=>ID_1_2_busQ, 
            I0=>GATE_T_78_A );
  GATE_T_78_I_2:   INV port map ( O=>GATE_T_78_A, 
            I0=>ID_1_1_busQ );
  GATE_T_79_I_1:   AND2 port map ( O=>T_79, 
            I1=>ID_1_2_busQ, 
            I0=>GATE_T_79_A );
  GATE_T_79_I_2:   INV port map ( O=>GATE_T_79_A, 
            I0=>nx1361 );
  GATE_T_80_I_1:   INV port map ( I0=>j2c_reg_shreg_0_busQ, 
            O=>GATE_T_80_A );
  GATE_T_80_I_2:   INV port map ( I0=>j2c_reg_shreg_3_busQ, 
            O=>GATE_T_80_B );
  GATE_T_80_I_3:   AND3 port map ( O=>T_80, 
            I0=>j2c_reg_shreg_1_busQ, 
            I2=>GATE_T_80_A, 
            I1=>GATE_T_80_B );
  GATE_T_81_I_1:   INV port map ( I0=>j2c_reg_shreg_0_busQ, 
            O=>GATE_T_81_A );
  GATE_T_81_I_2:   INV port map ( I0=>j2c_reg_shreg_1_busQ, 
            O=>GATE_T_81_B );
  GATE_T_81_I_3:   AND3 port map ( O=>T_81, 
            I0=>j2c_reg_shreg_3_busQ, 
            I2=>GATE_T_81_A, 
            I1=>GATE_T_81_B );
  GATE_T_82_I_1:   INV port map ( I0=>j2c_reg_shreg_3_busQ, 
            O=>GATE_T_82_A );
  GATE_T_82_I_2:   INV port map ( I0=>j2c_reg_shreg_1_busQ, 
            O=>GATE_T_82_B );
  GATE_T_82_I_3:   AND3 port map ( O=>T_82, 
            I0=>j2c_reg_shreg_0_busQ, 
            I2=>GATE_T_82_A, 
            I1=>GATE_T_82_B );
  GATE_T_83_I_1:   AND3 port map ( O=>T_83, 
            I2=>j2c_reg_shreg_3_busQ, 
            I1=>j2c_reg_shreg_1_busQ, 
            I0=>j2c_reg_shreg_0_busQ );
  GATE_T_84_I_1:   INV port map ( I0=>j2c_reg_shreg_3_busQ, 
            O=>GATE_T_84_A );
  GATE_T_84_I_2:   INV port map ( I0=>j2c_reg_shreg_2_busQ, 
            O=>GATE_T_84_B );
  GATE_T_84_I_3:   AND3 port map ( O=>T_84, 
            I0=>j2c_reg_shreg_1_busQ, 
            I2=>GATE_T_84_A, 
            I1=>GATE_T_84_B );
  GATE_T_85_I_1:   INV port map ( I0=>j2c_reg_shreg_3_busQ, 
            O=>GATE_T_85_A );
  GATE_T_85_I_2:   INV port map ( I0=>j2c_reg_shreg_1_busQ, 
            O=>GATE_T_85_B );
  GATE_T_85_I_3:   AND3 port map ( O=>T_85, 
            I0=>j2c_reg_shreg_2_busQ, 
            I2=>GATE_T_85_A, 
            I1=>GATE_T_85_B );
  GATE_T_86_I_1:   INV port map ( I0=>j2c_reg_shreg_2_busQ, 
            O=>GATE_T_86_A );
  GATE_T_86_I_2:   INV port map ( I0=>j2c_reg_shreg_1_busQ, 
            O=>GATE_T_86_B );
  GATE_T_86_I_3:   AND3 port map ( O=>T_86, 
            I0=>j2c_reg_shreg_3_busQ, 
            I2=>GATE_T_86_A, 
            I1=>GATE_T_86_B );
  GATE_T_87_I_1:   AND3 port map ( O=>T_87, 
            I2=>j2c_reg_shreg_2_busQ, 
            I1=>j2c_reg_shreg_1_busQ, 
            I0=>j2c_reg_shreg_3_busQ );
  GATE_T_88_I_1:   INV port map ( I0=>ID_0_2_busQ, 
            O=>GATE_T_88_A );
  GATE_T_88_I_2:   AND3 port map ( O=>T_88, 
            I2=>ID_0_1_busQ, 
            I1=>ID_0_0_busQ, 
            I0=>GATE_T_88_A );
  GATE_T_89_I_1:   AND2 port map ( O=>T_89, 
            I1=>ID_0_2_busQ, 
            I0=>GATE_T_89_A );
  GATE_T_89_I_2:   INV port map ( O=>GATE_T_89_A, 
            I0=>ID_0_0_busQ );
  GATE_T_90_I_1:   AND2 port map ( O=>T_90, 
            I1=>ID_0_2_busQ, 
            I0=>GATE_T_90_A );
  GATE_T_90_I_2:   INV port map ( O=>GATE_T_90_A, 
            I0=>ID_0_1_busQ );
  GATE_T_91_I_1:   AND4 port map ( O=>T_91, 
            I3=>ID_0_0_busQ, 
            I2=>ID_0_1_busQ, 
            I1=>ID_0_2_busQ, 
            I0=>GATE_T_91_A );
  GATE_T_91_I_2:   INV port map ( I0=>ID_0_3_busQ, 
            O=>GATE_T_91_A );
  GATE_T_92_I_1:   AND2 port map ( O=>T_92, 
            I1=>ID_0_3_busQ, 
            I0=>GATE_T_92_A );
  GATE_T_92_I_2:   INV port map ( O=>GATE_T_92_A, 
            I0=>ID_0_0_busQ );
  GATE_T_93_I_1:   AND2 port map ( O=>T_93, 
            I1=>ID_0_3_busQ, 
            I0=>GATE_T_93_A );
  GATE_T_93_I_2:   INV port map ( O=>GATE_T_93_A, 
            I0=>ID_0_1_busQ );
  GATE_T_94_I_1:   AND2 port map ( O=>T_94, 
            I1=>ID_0_3_busQ, 
            I0=>GATE_T_94_A );
  GATE_T_94_I_2:   INV port map ( O=>GATE_T_94_A, 
            I0=>ID_0_2_busQ );
  GATE_T_95_I_1:   INV port map ( I0=>j2c_reg_shreg_0_busQ, 
            O=>GATE_T_95_A );
  GATE_T_95_I_2:   INV port map ( I0=>j2c_reg_shreg_3_busQ, 
            O=>GATE_T_95_B );
  GATE_T_95_I_3:   AND3 port map ( O=>T_95, 
            I0=>j2c_reg_shreg_2_busQ, 
            I2=>GATE_T_95_A, 
            I1=>GATE_T_95_B );
  GATE_T_96_I_1:   INV port map ( I0=>j2c_reg_shreg_0_busQ, 
            O=>GATE_T_96_A );
  GATE_T_96_I_2:   INV port map ( I0=>j2c_reg_shreg_2_busQ, 
            O=>GATE_T_96_B );
  GATE_T_96_I_3:   AND3 port map ( O=>T_96, 
            I0=>j2c_reg_shreg_3_busQ, 
            I2=>GATE_T_96_A, 
            I1=>GATE_T_96_B );
  GATE_T_97_I_1:   INV port map ( I0=>j2c_reg_shreg_3_busQ, 
            O=>GATE_T_97_A );
  GATE_T_97_I_2:   INV port map ( I0=>j2c_reg_shreg_2_busQ, 
            O=>GATE_T_97_B );
  GATE_T_97_I_3:   AND3 port map ( O=>T_97, 
            I0=>j2c_reg_shreg_0_busQ, 
            I2=>GATE_T_97_A, 
            I1=>GATE_T_97_B );
  GATE_T_98_I_1:   AND3 port map ( O=>T_98, 
            I2=>j2c_reg_shreg_3_busQ, 
            I1=>j2c_reg_shreg_2_busQ, 
            I0=>j2c_reg_shreg_0_busQ );
  GATE_T_99_I_1:   AND3 port map ( O=>T_99, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_old_cnt_0_busQ, 
            I0=>ni_nires_reg_data2neg_0_busQ );
  GATE_T_100_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_100_A );
  GATE_T_100_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_100_B );
  GATE_T_100_I_3:   AND3 port map ( O=>T_100, 
            I0=>ni_nires_reg_data0neg_0_busQ, 
            I2=>GATE_T_100_A, 
            I1=>GATE_T_100_B );
  GATE_T_101_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_101_A );
  GATE_T_101_I_2:   AND3 port map ( O=>T_101, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1neg_0_busQ, 
            I0=>GATE_T_101_A );
  GATE_T_102_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_102_A );
  GATE_T_102_I_2:   AND3 port map ( O=>T_102, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_data3neg_0_busQ, 
            I0=>GATE_T_102_A );
  GATE_T_103_I_1:   INV port map ( I0=>ID_2_2_busQ, 
            O=>GATE_T_103_A );
  GATE_T_103_I_2:   AND3 port map ( O=>T_103, 
            I2=>ID_2_1_busQ, 
            I1=>ID_2_0_busQ, 
            I0=>GATE_T_103_A );
  GATE_T_104_I_1:   AND2 port map ( O=>T_104, 
            I1=>ID_2_2_busQ, 
            I0=>GATE_T_104_A );
  GATE_T_104_I_2:   INV port map ( O=>GATE_T_104_A, 
            I0=>ID_2_0_busQ );
  GATE_T_105_I_1:   AND2 port map ( O=>T_105, 
            I1=>ID_2_2_busQ, 
            I0=>GATE_T_105_A );
  GATE_T_105_I_2:   INV port map ( O=>GATE_T_105_A, 
            I0=>ID_2_1_busQ );
  GATE_T_106_I_1:   AND4 port map ( O=>T_106, 
            I3=>ID_2_0_busQ, 
            I2=>ID_2_1_busQ, 
            I1=>ID_2_2_busQ, 
            I0=>GATE_T_106_A );
  GATE_T_106_I_2:   INV port map ( I0=>ID_2_3_busQ, 
            O=>GATE_T_106_A );
  GATE_T_107_I_1:   AND2 port map ( O=>T_107, 
            I1=>ID_2_3_busQ, 
            I0=>GATE_T_107_A );
  GATE_T_107_I_2:   INV port map ( O=>GATE_T_107_A, 
            I0=>ID_2_0_busQ );
  GATE_T_108_I_1:   AND2 port map ( O=>T_108, 
            I1=>ID_2_3_busQ, 
            I0=>GATE_T_108_A );
  GATE_T_108_I_2:   INV port map ( O=>GATE_T_108_A, 
            I0=>ID_2_1_busQ );
  GATE_T_109_I_1:   AND2 port map ( O=>T_109, 
            I1=>ID_2_3_busQ, 
            I0=>GATE_T_109_A );
  GATE_T_109_I_2:   INV port map ( O=>GATE_T_109_A, 
            I0=>ID_2_2_busQ );
  GATE_T_110_I_1:   AND3 port map ( O=>T_110, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_old_cnt_0_busQ, 
            I0=>ni_nires_reg_data2neg_1_busQ );
  GATE_T_111_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_111_A );
  GATE_T_111_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_111_B );
  GATE_T_111_I_3:   AND3 port map ( O=>T_111, 
            I0=>ni_nires_reg_data0neg_1_busQ, 
            I2=>GATE_T_111_A, 
            I1=>GATE_T_111_B );
  GATE_T_112_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_112_A );
  GATE_T_112_I_2:   AND3 port map ( O=>T_112, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1neg_1_busQ, 
            I0=>GATE_T_112_A );
  GATE_T_113_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_113_A );
  GATE_T_113_I_2:   AND3 port map ( O=>T_113, 
            I2=>ni_nires_reg_old_cnt_1_busQ, 
            I1=>ni_nires_reg_data3neg_1_busQ, 
            I0=>GATE_T_113_A );
  GATE_T_114_I_1:   AND2 port map ( O=>T_114, 
            I1=>ni_nires_reg_old_cnt_1_busQ, 
            I0=>GATE_T_114_A );
  GATE_T_114_I_2:   INV port map ( O=>GATE_T_114_A, 
            I0=>ni_nires_reg_new_cnt_1_busQ );
  GATE_T_115_I_1:   AND2 port map ( O=>T_115, 
            I1=>ni_nires_reg_new_cnt_1_busQ, 
            I0=>GATE_T_115_A );
  GATE_T_115_I_2:   INV port map ( O=>GATE_T_115_A, 
            I0=>ni_nires_reg_old_cnt_1_busQ );
  GATE_T_116_I_1:   AND2 port map ( O=>T_116, 
            I1=>ni_nires_reg_new_cnt_0_busQ, 
            I0=>GATE_T_116_A );
  GATE_T_116_I_2:   INV port map ( O=>GATE_T_116_A, 
            I0=>ni_nires_reg_old_cnt_0_busQ );
  GATE_T_117_I_1:   AND2 port map ( O=>T_117, 
            I1=>ni_nires_reg_old_cnt_0_busQ, 
            I0=>GATE_T_117_A );
  GATE_T_117_I_2:   INV port map ( O=>GATE_T_117_A, 
            I0=>ni_nires_reg_new_cnt_0_busQ );
  GATE_T_118_I_1:   AND3 port map ( O=>T_118, 
            I2=>T_534, 
            I1=>T_535, 
            I0=>T_533 );
  GATE_T_119_I_1:   INV port map ( I0=>ix1160, 
            O=>GATE_T_119_A );
  GATE_T_119_I_2:   AND3 port map ( O=>T_119, 
            I2=>T_532, 
            I1=>T_531, 
            I0=>GATE_T_119_A );
  GATE_T_120_I_1:   AND3 port map ( O=>T_120, 
            I2=>T_530, 
            I1=>nx1647, 
            I0=>T_529 );
  GATE_T_121_I_1:   AND3 port map ( O=>T_121, 
            I2=>T_528, 
            I1=>nx1595, 
            I0=>T_527 );
  GATE_T_122_I_1:   INV port map ( I0=>ix1084, 
            O=>GATE_T_122_A );
  GATE_T_122_I_2:   AND3 port map ( O=>T_122, 
            I2=>T_526, 
            I1=>T_525, 
            I0=>GATE_T_122_A );
  GATE_T_123_I_1:   INV port map ( I0=>nx1909, 
            O=>GATE_T_123_A );
  GATE_T_123_I_2:   AND3 port map ( O=>T_123, 
            I2=>T_524, 
            I1=>T_523, 
            I0=>GATE_T_123_A );
  GATE_T_124_I_1:   AND3 port map ( O=>T_124, 
            I2=>T_522, 
            I1=>nx1909, 
            I0=>T_521 );
  GATE_T_125_I_1:   AND3 port map ( O=>T_125, 
            I2=>T_520, 
            I1=>nx1595, 
            I0=>T_519 );
  GATE_T_126_I_1:   AND4 port map ( O=>T_126, 
            I3=>nx1647, 
            I2=>nx1595, 
            I1=>ni_nires_reg_data_out_10_busQ, 
            I0=>GATE_T_126_A );
  GATE_T_126_I_2:   INV port map ( I0=>nx1519, 
            O=>GATE_T_126_A );
  GATE_T_127_I_1:   AND4 port map ( O=>T_127, 
            I3=>nx1647, 
            I2=>nx1595, 
            I1=>ni_nires_reg_data_out_10_busQ, 
            I0=>GATE_T_127_A );
  GATE_T_127_I_2:   INV port map ( I0=>ix1266, 
            O=>GATE_T_127_A );
  GATE_T_128_I_1:   INV port map ( I0=>ix1598, 
            O=>GATE_T_128_A );
  GATE_T_128_I_2:   AND3 port map ( O=>T_128, 
            I2=>ix1610, 
            I1=>nx1725, 
            I0=>GATE_T_128_A );
  GATE_T_129_I_1:   INV port map ( I0=>nx1717, 
            O=>GATE_T_129_A );
  GATE_T_129_I_2:   INV port map ( I0=>ix1610, 
            O=>GATE_T_129_B );
  GATE_T_129_I_3:   AND3 port map ( O=>T_129, 
            I0=>ni_nires_reg_data_out_18_busQ, 
            I2=>GATE_T_129_A, 
            I1=>GATE_T_129_B );
  GATE_T_130_I_1:   INV port map ( I0=>ix1610, 
            O=>GATE_T_130_A );
  GATE_T_130_I_2:   AND3 port map ( O=>T_130, 
            I2=>ni_nires_reg_data_out_19_busQ, 
            I1=>nx1717, 
            I0=>GATE_T_130_A );
  GATE_T_131_I_1:   NOR4 port map ( I0=>ix1578, 
            I1=>ix1160, 
            O=>T_131, 
            I2=>ix1524, 
            I3=>GATE_T_131_DN );
  GATE_T_131_I_2:   INV port map ( I0=>ni_nires_reg_data_out_17_busQ, 
            O=>GATE_T_131_DN );
  GATE_T_132_I_3:   AND4 port map ( O=>T_132, 
            I3=>ix1160, 
            I2=>ni_nires_reg_data_out_18_busQ, 
            I1=>GATE_T_132_B, 
            I0=>GATE_T_132_A );
  GATE_T_132_I_2:   INV port map ( I0=>ix1578, 
            O=>GATE_T_132_B );
  GATE_T_132_I_1:   INV port map ( I0=>ix1524, 
            O=>GATE_T_132_A );
  GATE_T_133_I_1:   INV port map ( I0=>nx1851, 
            O=>GATE_T_133_A );
  GATE_T_133_I_2:   INV port map ( I0=>ix1524, 
            O=>GATE_T_133_B );
  GATE_T_133_I_3:   AND3 port map ( O=>T_133, 
            I0=>ix1578, 
            I2=>GATE_T_133_A, 
            I1=>GATE_T_133_B );
  GATE_T_134_I_1:   INV port map ( I0=>nx1815, 
            O=>GATE_T_134_A );
  GATE_T_134_I_2:   INV port map ( I0=>ix1578, 
            O=>GATE_T_134_B );
  GATE_T_134_I_3:   AND3 port map ( O=>T_134, 
            I0=>ix1524, 
            I2=>GATE_T_134_A, 
            I1=>GATE_T_134_B );
  GATE_T_135_I_1:   AND2 port map ( O=>T_135, 
            I1=>nx1647, 
            I0=>GATE_T_135_A );
  GATE_T_135_I_2:   INV port map ( O=>GATE_T_135_A, 
            I0=>nx1759 );
  GATE_T_136_I_1:   AND4 port map ( O=>T_136, 
            I3=>T_536, 
            I2=>T_537, 
            I1=>T_538, 
            I0=>ID_2_0_busQ );
  GATE_T_137_I_1:   INV port map ( I0=>j2c_bitcnt_2_busQ, 
            O=>GATE_T_137_A );
  GATE_T_137_I_2:   AND3 port map ( O=>T_137, 
            I2=>j2c_bitcnt_1_busQ, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>GATE_T_137_A );
  GATE_T_138_I_1:   AND2 port map ( O=>T_138, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_138_A );
  GATE_T_138_I_2:   INV port map ( O=>GATE_T_138_A, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_139_I_1:   AND2 port map ( O=>T_139, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_139_A );
  GATE_T_139_I_2:   INV port map ( O=>GATE_T_139_A, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_140_I_3:   AND4 port map ( O=>T_140, 
            I3=>j2c_bitcnt_0_busQ, 
            I2=>j2c_reg_cmdreg_3_busQ, 
            I1=>GATE_T_140_B, 
            I0=>GATE_T_140_A );
  GATE_T_140_I_2:   INV port map ( I0=>j2c_bitcnt_1_busQ, 
            O=>GATE_T_140_B );
  GATE_T_140_I_1:   INV port map ( I0=>j2c_bitcnt_2_busQ, 
            O=>GATE_T_140_A );
  GATE_T_141_I_1:   AND3 port map ( O=>T_141, 
            I2=>j2c_bitcnt_1_busQ, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_142_I_1:   AND2 port map ( O=>T_142, 
            I1=>ni_nires_reg_old_cnt_1_busQ, 
            I0=>GATE_T_142_A );
  GATE_T_142_I_2:   INV port map ( O=>GATE_T_142_A, 
            I0=>ni_nires_reg_new_cnt_1_busQ );
  GATE_T_143_I_1:   AND2 port map ( O=>T_143, 
            I1=>ni_nires_reg_new_cnt_1_busQ, 
            I0=>GATE_T_143_A );
  GATE_T_143_I_2:   INV port map ( O=>GATE_T_143_A, 
            I0=>ni_nires_reg_old_cnt_1_busQ );
  GATE_T_144_I_1:   AND2 port map ( O=>T_144, 
            I1=>ni_nires_reg_new_cnt_0_busQ, 
            I0=>GATE_T_144_A );
  GATE_T_144_I_2:   INV port map ( O=>GATE_T_144_A, 
            I0=>ni_nires_reg_old_cnt_0_busQ );
  GATE_T_145_I_1:   AND2 port map ( O=>T_145, 
            I1=>ni_nires_reg_old_cnt_0_busQ, 
            I0=>GATE_T_145_A );
  GATE_T_145_I_2:   INV port map ( O=>GATE_T_145_A, 
            I0=>ni_nires_reg_new_cnt_0_busQ );
  GATE_T_146_I_1:   INV port map ( I0=>ID_3_2_busQ, 
            O=>GATE_T_146_A );
  GATE_T_146_I_2:   AND3 port map ( O=>T_146, 
            I2=>ID_3_1_busQ, 
            I1=>ID_3_0_busQ, 
            I0=>GATE_T_146_A );
  GATE_T_147_I_1:   AND2 port map ( O=>T_147, 
            I1=>ID_3_2_busQ, 
            I0=>GATE_T_147_A );
  GATE_T_147_I_2:   INV port map ( O=>GATE_T_147_A, 
            I0=>ID_3_0_busQ );
  GATE_T_148_I_1:   AND2 port map ( O=>T_148, 
            I1=>ID_3_2_busQ, 
            I0=>GATE_T_148_A );
  GATE_T_148_I_2:   INV port map ( O=>GATE_T_148_A, 
            I0=>ID_3_1_busQ );
  GATE_T_149_I_1:   AND4 port map ( O=>T_149, 
            I3=>ID_3_0_busQ, 
            I2=>ID_3_1_busQ, 
            I1=>ID_3_2_busQ, 
            I0=>GATE_T_149_A );
  GATE_T_149_I_2:   INV port map ( I0=>ID_3_3_busQ, 
            O=>GATE_T_149_A );
  GATE_T_150_I_1:   AND2 port map ( O=>T_150, 
            I1=>ID_3_3_busQ, 
            I0=>GATE_T_150_A );
  GATE_T_150_I_2:   INV port map ( O=>GATE_T_150_A, 
            I0=>ID_3_0_busQ );
  GATE_T_151_I_1:   AND2 port map ( O=>T_151, 
            I1=>ID_3_3_busQ, 
            I0=>GATE_T_151_A );
  GATE_T_151_I_2:   INV port map ( O=>GATE_T_151_A, 
            I0=>ID_3_1_busQ );
  GATE_T_152_I_1:   AND2 port map ( O=>T_152, 
            I1=>ID_3_3_busQ, 
            I0=>GATE_T_152_A );
  GATE_T_152_I_2:   INV port map ( O=>GATE_T_152_A, 
            I0=>ID_3_2_busQ );
  GATE_T_153_I_1:   AND4 port map ( O=>T_153, 
            I3=>ni_pattcount_1_busQ, 
            I2=>ni_pattcount_2_busQ, 
            I1=>ni_pattcount_0_busQ, 
            I0=>GATE_T_153_A );
  GATE_T_153_I_2:   INV port map ( I0=>ni_pattcount_3_busQ, 
            O=>GATE_T_153_A );
  GATE_T_154_I_1:   AND2 port map ( O=>T_154, 
            I1=>ni_pattcount_3_busQ, 
            I0=>GATE_T_154_A );
  GATE_T_154_I_2:   INV port map ( O=>GATE_T_154_A, 
            I0=>ni_pattcount_0_busQ );
  GATE_T_155_I_1:   AND2 port map ( O=>T_155, 
            I1=>ni_pattcount_3_busQ, 
            I0=>GATE_T_155_A );
  GATE_T_155_I_2:   INV port map ( O=>GATE_T_155_A, 
            I0=>ni_pattcount_1_busQ );
  GATE_T_156_I_1:   AND2 port map ( O=>T_156, 
            I1=>ni_pattcount_3_busQ, 
            I0=>GATE_T_156_A );
  GATE_T_156_I_2:   INV port map ( O=>GATE_T_156_A, 
            I0=>ni_pattcount_2_busQ );
  GATE_T_157_I_1:   INV port map ( I0=>ni_pattcount_2_busQ, 
            O=>GATE_T_157_A );
  GATE_T_157_I_2:   AND3 port map ( O=>T_157, 
            I2=>ni_pattcount_1_busQ, 
            I1=>ni_pattcount_0_busQ, 
            I0=>GATE_T_157_A );
  GATE_T_158_I_1:   AND2 port map ( O=>T_158, 
            I1=>ni_pattcount_2_busQ, 
            I0=>GATE_T_158_A );
  GATE_T_158_I_2:   INV port map ( O=>GATE_T_158_A, 
            I0=>ni_pattcount_0_busQ );
  GATE_T_159_I_1:   AND2 port map ( O=>T_159, 
            I1=>ni_pattcount_2_busQ, 
            I0=>GATE_T_159_A );
  GATE_T_159_I_2:   INV port map ( O=>GATE_T_159_A, 
            I0=>ni_pattcount_1_busQ );
  GATE_T_160_I_1:   AND3 port map ( O=>T_160, 
            I2=>T_564, 
            I1=>T_565, 
            I0=>T_563 );
  GATE_T_161_I_1:   INV port map ( I0=>ix1160, 
            O=>GATE_T_161_A );
  GATE_T_161_I_2:   AND3 port map ( O=>T_161, 
            I2=>T_562, 
            I1=>T_561, 
            I0=>GATE_T_161_A );
  GATE_T_162_I_1:   INV port map ( I0=>ix1084, 
            O=>GATE_T_162_A );
  GATE_T_162_I_2:   AND3 port map ( O=>T_162, 
            I2=>T_560, 
            I1=>T_559, 
            I0=>GATE_T_162_A );
  GATE_T_163_I_1:   AND3 port map ( O=>T_163, 
            I2=>T_558, 
            I1=>nx1909, 
            I0=>T_557 );
  GATE_T_164_I_1:   INV port map ( I0=>nx1909, 
            O=>GATE_T_164_A );
  GATE_T_164_I_2:   AND3 port map ( O=>T_164, 
            I2=>T_556, 
            I1=>T_555, 
            I0=>GATE_T_164_A );
  GATE_T_165_I_1:   AND3 port map ( O=>T_165, 
            I2=>T_554, 
            I1=>nx1595, 
            I0=>T_553 );
  GATE_T_166_I_1:   AND3 port map ( O=>T_166, 
            I2=>T_552, 
            I1=>nx1647, 
            I0=>T_551 );
  GATE_T_167_I_1:   AND3 port map ( O=>T_167, 
            I2=>T_550, 
            I1=>nx1595, 
            I0=>T_549 );
  GATE_T_168_I_1:   AND4 port map ( O=>T_168, 
            I3=>nx1647, 
            I2=>nx1595, 
            I1=>ni_nires_reg_data_out_0_busQ, 
            I0=>GATE_T_168_A );
  GATE_T_168_I_2:   INV port map ( I0=>nx1519, 
            O=>GATE_T_168_A );
  GATE_T_169_I_1:   AND4 port map ( O=>T_169, 
            I3=>nx1647, 
            I2=>nx1595, 
            I1=>ni_nires_reg_data_out_0_busQ, 
            I0=>GATE_T_169_A );
  GATE_T_169_I_2:   INV port map ( I0=>ix1266, 
            O=>GATE_T_169_A );
  GATE_T_170_I_1:   INV port map ( I0=>ix1598, 
            O=>GATE_T_170_A );
  GATE_T_170_I_2:   AND3 port map ( O=>T_170, 
            I2=>ix1610, 
            I1=>nx2210, 
            I0=>GATE_T_170_A );
  GATE_T_171_I_1:   INV port map ( I0=>ix1610, 
            O=>GATE_T_171_A );
  GATE_T_171_I_2:   AND3 port map ( O=>T_171, 
            I2=>ni_nires_reg_data_out_9_busQ, 
            I1=>nx1717, 
            I0=>GATE_T_171_A );
  GATE_T_172_I_1:   INV port map ( I0=>nx1717, 
            O=>GATE_T_172_A );
  GATE_T_172_I_2:   INV port map ( I0=>ix1610, 
            O=>GATE_T_172_B );
  GATE_T_172_I_3:   AND3 port map ( O=>T_172, 
            I0=>ni_nires_reg_data_out_8_busQ, 
            I2=>GATE_T_172_A, 
            I1=>GATE_T_172_B );
  GATE_T_173_I_1:   NOR4 port map ( I0=>ix1578, 
            I1=>ix1160, 
            O=>T_173, 
            I2=>ix1524, 
            I3=>GATE_T_173_DN );
  GATE_T_173_I_2:   INV port map ( I0=>ni_nires_reg_data_out_7_busQ, 
            O=>GATE_T_173_DN );
  GATE_T_174_I_3:   AND4 port map ( O=>T_174, 
            I3=>ix1160, 
            I2=>ni_nires_reg_data_out_8_busQ, 
            I1=>GATE_T_174_B, 
            I0=>GATE_T_174_A );
  GATE_T_174_I_2:   INV port map ( I0=>ix1578, 
            O=>GATE_T_174_B );
  GATE_T_174_I_1:   INV port map ( I0=>ix1524, 
            O=>GATE_T_174_A );
  GATE_T_175_I_1:   INV port map ( I0=>nx2272, 
            O=>GATE_T_175_A );
  GATE_T_175_I_2:   INV port map ( I0=>ix1578, 
            O=>GATE_T_175_B );
  GATE_T_175_I_3:   AND3 port map ( O=>T_175, 
            I0=>ix1524, 
            I2=>GATE_T_175_A, 
            I1=>GATE_T_175_B );
  GATE_T_176_I_1:   INV port map ( I0=>ix1524, 
            O=>GATE_T_176_A );
  GATE_T_176_I_2:   INV port map ( I0=>nx2294, 
            O=>GATE_T_176_B );
  GATE_T_176_I_3:   AND3 port map ( O=>T_176, 
            I0=>ix1578, 
            I2=>GATE_T_176_A, 
            I1=>GATE_T_176_B );
  GATE_T_177_I_1:   AND2 port map ( O=>T_177, 
            I1=>nx1647, 
            I0=>GATE_T_177_A );
  GATE_T_177_I_2:   INV port map ( O=>GATE_T_177_A, 
            I0=>nx2236 );
  GATE_T_178_I_1:   AND3 port map ( O=>T_178, 
            I2=>ix1084, 
            I1=>ix1266, 
            I0=>ix1164 );
  GATE_T_179_I_3:   AND4 port map ( O=>T_179, 
            I3=>TXD_0XQ, 
            I2=>TX_ENQ, 
            I1=>GATE_T_179_B, 
            I0=>GATE_T_179_A );
  GATE_T_179_I_2:   INV port map ( I0=>ix1647, 
            O=>GATE_T_179_B );
  GATE_T_179_I_1:   INV port map ( I0=>ix1641, 
            O=>GATE_T_179_A );
  GATE_T_180_I_3:   AND4 port map ( O=>T_180, 
            I3=>ix1641, 
            I2=>TX_ENQ, 
            I1=>GATE_T_180_B, 
            I0=>GATE_T_180_A );
  GATE_T_180_I_2:   INV port map ( I0=>ix1647, 
            O=>GATE_T_180_B );
  GATE_T_180_I_1:   INV port map ( I0=>TXD_0XQ, 
            O=>GATE_T_180_A );
  GATE_T_181_I_3:   AND4 port map ( O=>T_181, 
            I3=>ix1647, 
            I2=>TX_ENQ, 
            I1=>GATE_T_181_B, 
            I0=>GATE_T_181_A );
  GATE_T_181_I_2:   INV port map ( I0=>ix1641, 
            O=>GATE_T_181_B );
  GATE_T_181_I_1:   INV port map ( I0=>TXD_0XQ, 
            O=>GATE_T_181_A );
  GATE_T_182_I_1:   AND4 port map ( O=>T_182, 
            I3=>ix1647, 
            I2=>ix1641, 
            I1=>TXD_0XQ, 
            I0=>TX_ENQ );
  GATE_T_183_I_1:   NOR3 port map ( O=>T_183, 
            I2=>TXD_2XQ, 
            I1=>TXD_3XQ, 
            I0=>TXD_1XQ );
  GATE_T_184_I_1:   INV port map ( I0=>TXD_1XQ, 
            O=>GATE_T_184_A );
  GATE_T_184_I_2:   AND3 port map ( O=>T_184, 
            I2=>TXD_2XQ, 
            I1=>TXD_3XQ, 
            I0=>GATE_T_184_A );
  GATE_T_185_I_1:   INV port map ( I0=>TXD_2XQ, 
            O=>GATE_T_185_A );
  GATE_T_185_I_2:   AND3 port map ( O=>T_185, 
            I2=>TXD_3XQ, 
            I1=>TXD_1XQ, 
            I0=>GATE_T_185_A );
  GATE_T_186_I_1:   INV port map ( I0=>TXD_3XQ, 
            O=>GATE_T_186_A );
  GATE_T_186_I_2:   AND3 port map ( O=>T_186, 
            I2=>TXD_2XQ, 
            I1=>TXD_1XQ, 
            I0=>GATE_T_186_A );
  GATE_T_187_I_1:   NOR3 port map ( O=>T_187, 
            I2=>TXD_5XQ, 
            I1=>TXD_6XQ, 
            I0=>ni_reg_prty_bit_pos_rQ );
  GATE_T_188_I_1:   INV port map ( I0=>ni_reg_prty_bit_pos_rQ, 
            O=>GATE_T_188_A );
  GATE_T_188_I_2:   AND3 port map ( O=>T_188, 
            I2=>TXD_5XQ, 
            I1=>TXD_6XQ, 
            I0=>GATE_T_188_A );
  GATE_T_189_I_1:   INV port map ( I0=>TXD_5XQ, 
            O=>GATE_T_189_A );
  GATE_T_189_I_2:   AND3 port map ( O=>T_189, 
            I2=>TXD_6XQ, 
            I1=>ni_reg_prty_bit_pos_rQ, 
            I0=>GATE_T_189_A );
  GATE_T_190_I_1:   INV port map ( I0=>TXD_6XQ, 
            O=>GATE_T_190_A );
  GATE_T_190_I_2:   AND3 port map ( O=>T_190, 
            I2=>TXD_5XQ, 
            I1=>ni_reg_prty_bit_pos_rQ, 
            I0=>GATE_T_190_A );
  GATE_T_191_I_1:   AND4 port map ( O=>T_191, 
            I3=>T_566, 
            I2=>T_567, 
            I1=>T_568, 
            I0=>ID_3_0_busQ );
  GATE_T_192_I_1:   INV port map ( I0=>j2c_reg_shreg_7_busQ, 
            O=>GATE_T_192_A );
  GATE_T_192_I_2:   INV port map ( I0=>j2c_reg_shreg_5_busQ, 
            O=>GATE_T_192_B );
  GATE_T_192_I_3:   AND3 port map ( O=>T_192, 
            I0=>j2c_reg_shreg_4_busQ, 
            I2=>GATE_T_192_A, 
            I1=>GATE_T_192_B );
  GATE_T_193_I_1:   INV port map ( I0=>j2c_reg_shreg_7_busQ, 
            O=>GATE_T_193_A );
  GATE_T_193_I_2:   INV port map ( I0=>j2c_reg_shreg_4_busQ, 
            O=>GATE_T_193_B );
  GATE_T_193_I_3:   AND3 port map ( O=>T_193, 
            I0=>j2c_reg_shreg_5_busQ, 
            I2=>GATE_T_193_A, 
            I1=>GATE_T_193_B );
  GATE_T_194_I_1:   INV port map ( I0=>j2c_reg_shreg_5_busQ, 
            O=>GATE_T_194_A );
  GATE_T_194_I_2:   INV port map ( I0=>j2c_reg_shreg_4_busQ, 
            O=>GATE_T_194_B );
  GATE_T_194_I_3:   AND3 port map ( O=>T_194, 
            I0=>j2c_reg_shreg_7_busQ, 
            I2=>GATE_T_194_A, 
            I1=>GATE_T_194_B );
  GATE_T_195_I_1:   AND3 port map ( O=>T_195, 
            I2=>j2c_reg_shreg_5_busQ, 
            I1=>j2c_reg_shreg_4_busQ, 
            I0=>j2c_reg_shreg_7_busQ );
  GATE_T_196_I_1:   INV port map ( I0=>j2c_reg_shreg_7_busQ, 
            O=>GATE_T_196_A );
  GATE_T_196_I_2:   INV port map ( I0=>j2c_reg_shreg_6_busQ, 
            O=>GATE_T_196_B );
  GATE_T_196_I_3:   AND3 port map ( O=>T_196, 
            I0=>j2c_reg_shreg_4_busQ, 
            I2=>GATE_T_196_A, 
            I1=>GATE_T_196_B );
  GATE_T_197_I_1:   INV port map ( I0=>j2c_reg_shreg_7_busQ, 
            O=>GATE_T_197_A );
  GATE_T_197_I_2:   INV port map ( I0=>j2c_reg_shreg_4_busQ, 
            O=>GATE_T_197_B );
  GATE_T_197_I_3:   AND3 port map ( O=>T_197, 
            I0=>j2c_reg_shreg_6_busQ, 
            I2=>GATE_T_197_A, 
            I1=>GATE_T_197_B );
  GATE_T_198_I_1:   INV port map ( I0=>j2c_reg_shreg_6_busQ, 
            O=>GATE_T_198_A );
  GATE_T_198_I_2:   INV port map ( I0=>j2c_reg_shreg_4_busQ, 
            O=>GATE_T_198_B );
  GATE_T_198_I_3:   AND3 port map ( O=>T_198, 
            I0=>j2c_reg_shreg_7_busQ, 
            I2=>GATE_T_198_A, 
            I1=>GATE_T_198_B );
  GATE_T_199_I_1:   AND3 port map ( O=>T_199, 
            I2=>j2c_reg_shreg_6_busQ, 
            I1=>j2c_reg_shreg_4_busQ, 
            I0=>j2c_reg_shreg_7_busQ );
  GATE_T_200_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_200_A );
  GATE_T_200_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_200_B );
  GATE_T_200_I_3:   AND3 port map ( O=>T_200, 
            I0=>ni_nires_reg_data0pos_9_busQ, 
            I2=>GATE_T_200_A, 
            I1=>GATE_T_200_B );
  GATE_T_201_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_201_A );
  GATE_T_201_I_2:   AND3 port map ( O=>T_201, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1pos_9_busQ, 
            I0=>GATE_T_201_A );
  GATE_T_202_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_202_A );
  GATE_T_202_I_2:   AND3 port map ( O=>T_202, 
            I2=>ni_nires_reg_data3pos_9_busQ, 
            I1=>ni_nires_reg_old_cnt_1_busQ, 
            I0=>GATE_T_202_A );
  GATE_T_203_I_1:   AND3 port map ( O=>T_203, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data2pos_9_busQ, 
            I0=>ni_nires_reg_old_cnt_1_busQ );
  GATE_T_204_I_1:   INV port map ( I0=>j2c_reg_shreg_7_busQ, 
            O=>GATE_T_204_A );
  GATE_T_204_I_2:   INV port map ( I0=>j2c_reg_shreg_6_busQ, 
            O=>GATE_T_204_B );
  GATE_T_204_I_3:   AND3 port map ( O=>T_204, 
            I0=>j2c_reg_shreg_5_busQ, 
            I2=>GATE_T_204_A, 
            I1=>GATE_T_204_B );
  GATE_T_205_I_1:   INV port map ( I0=>j2c_reg_shreg_7_busQ, 
            O=>GATE_T_205_A );
  GATE_T_205_I_2:   INV port map ( I0=>j2c_reg_shreg_5_busQ, 
            O=>GATE_T_205_B );
  GATE_T_205_I_3:   AND3 port map ( O=>T_205, 
            I0=>j2c_reg_shreg_6_busQ, 
            I2=>GATE_T_205_A, 
            I1=>GATE_T_205_B );
  GATE_T_206_I_1:   INV port map ( I0=>j2c_reg_shreg_6_busQ, 
            O=>GATE_T_206_A );
  GATE_T_206_I_2:   INV port map ( I0=>j2c_reg_shreg_5_busQ, 
            O=>GATE_T_206_B );
  GATE_T_206_I_3:   AND3 port map ( O=>T_206, 
            I0=>j2c_reg_shreg_7_busQ, 
            I2=>GATE_T_206_A, 
            I1=>GATE_T_206_B );
  GATE_T_207_I_1:   AND3 port map ( O=>T_207, 
            I2=>j2c_reg_shreg_6_busQ, 
            I1=>j2c_reg_shreg_5_busQ, 
            I0=>j2c_reg_shreg_7_busQ );
  GATE_T_208_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_208_A );
  GATE_T_208_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_208_B );
  GATE_T_208_I_3:   AND3 port map ( O=>T_208, 
            I0=>ni_nires_reg_data0pos_8_busQ, 
            I2=>GATE_T_208_A, 
            I1=>GATE_T_208_B );
  GATE_T_209_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_209_A );
  GATE_T_209_I_2:   AND3 port map ( O=>T_209, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1pos_8_busQ, 
            I0=>GATE_T_209_A );
  GATE_T_210_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_210_A );
  GATE_T_210_I_2:   AND3 port map ( O=>T_210, 
            I2=>ni_nires_reg_data3pos_8_busQ, 
            I1=>ni_nires_reg_old_cnt_1_busQ, 
            I0=>GATE_T_210_A );
  GATE_T_211_I_1:   AND3 port map ( O=>T_211, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data2pos_8_busQ, 
            I0=>ni_nires_reg_old_cnt_1_busQ );
  GATE_T_212_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_212_A );
  GATE_T_212_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_212_B );
  GATE_T_212_I_3:   AND3 port map ( O=>T_212, 
            I0=>ni_nires_reg_data0pos_7_busQ, 
            I2=>GATE_T_212_A, 
            I1=>GATE_T_212_B );
  GATE_T_213_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_213_A );
  GATE_T_213_I_2:   AND3 port map ( O=>T_213, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1pos_7_busQ, 
            I0=>GATE_T_213_A );
  GATE_T_214_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_214_A );
  GATE_T_214_I_2:   AND3 port map ( O=>T_214, 
            I2=>ni_nires_reg_data3pos_7_busQ, 
            I1=>ni_nires_reg_old_cnt_1_busQ, 
            I0=>GATE_T_214_A );
  GATE_T_215_I_1:   AND3 port map ( O=>T_215, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data2pos_7_busQ, 
            I0=>ni_nires_reg_old_cnt_1_busQ );
  GATE_T_216_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_216_A );
  GATE_T_216_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_216_B );
  GATE_T_216_I_3:   AND3 port map ( O=>T_216, 
            I0=>ni_nires_reg_data0pos_6_busQ, 
            I2=>GATE_T_216_A, 
            I1=>GATE_T_216_B );
  GATE_T_217_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_217_A );
  GATE_T_217_I_2:   AND3 port map ( O=>T_217, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1pos_6_busQ, 
            I0=>GATE_T_217_A );
  GATE_T_218_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_218_A );
  GATE_T_218_I_2:   AND3 port map ( O=>T_218, 
            I2=>ni_nires_reg_data3pos_6_busQ, 
            I1=>ni_nires_reg_old_cnt_1_busQ, 
            I0=>GATE_T_218_A );
  GATE_T_219_I_1:   AND3 port map ( O=>T_219, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data2pos_6_busQ, 
            I0=>ni_nires_reg_old_cnt_1_busQ );
  GATE_T_220_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_220_A );
  GATE_T_220_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_220_B );
  GATE_T_220_I_3:   AND3 port map ( O=>T_220, 
            I0=>ni_nires_reg_data0pos_5_busQ, 
            I2=>GATE_T_220_A, 
            I1=>GATE_T_220_B );
  GATE_T_221_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_221_A );
  GATE_T_221_I_2:   AND3 port map ( O=>T_221, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1pos_5_busQ, 
            I0=>GATE_T_221_A );
  GATE_T_222_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_222_A );
  GATE_T_222_I_2:   AND3 port map ( O=>T_222, 
            I2=>ni_nires_reg_data3pos_5_busQ, 
            I1=>ni_nires_reg_old_cnt_1_busQ, 
            I0=>GATE_T_222_A );
  GATE_T_223_I_1:   AND3 port map ( O=>T_223, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data2pos_5_busQ, 
            I0=>ni_nires_reg_old_cnt_1_busQ );
  GATE_T_224_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_224_A );
  GATE_T_224_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_224_B );
  GATE_T_224_I_3:   AND3 port map ( O=>T_224, 
            I0=>ni_nires_reg_data0pos_4_busQ, 
            I2=>GATE_T_224_A, 
            I1=>GATE_T_224_B );
  GATE_T_225_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_225_A );
  GATE_T_225_I_2:   AND3 port map ( O=>T_225, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1pos_4_busQ, 
            I0=>GATE_T_225_A );
  GATE_T_226_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_226_A );
  GATE_T_226_I_2:   AND3 port map ( O=>T_226, 
            I2=>ni_nires_reg_data3pos_4_busQ, 
            I1=>ni_nires_reg_old_cnt_1_busQ, 
            I0=>GATE_T_226_A );
  GATE_T_227_I_1:   AND3 port map ( O=>T_227, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data2pos_4_busQ, 
            I0=>ni_nires_reg_old_cnt_1_busQ );
  GATE_T_228_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_228_A );
  GATE_T_228_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_228_B );
  GATE_T_228_I_3:   AND3 port map ( O=>T_228, 
            I0=>ni_nires_reg_data0pos_3_busQ, 
            I2=>GATE_T_228_A, 
            I1=>GATE_T_228_B );
  GATE_T_229_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_229_A );
  GATE_T_229_I_2:   AND3 port map ( O=>T_229, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1pos_3_busQ, 
            I0=>GATE_T_229_A );
  GATE_T_230_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_230_A );
  GATE_T_230_I_2:   AND3 port map ( O=>T_230, 
            I2=>ni_nires_reg_data3pos_3_busQ, 
            I1=>ni_nires_reg_old_cnt_1_busQ, 
            I0=>GATE_T_230_A );
  GATE_T_231_I_1:   AND3 port map ( O=>T_231, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data2pos_3_busQ, 
            I0=>ni_nires_reg_old_cnt_1_busQ );
  GATE_T_232_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_232_A );
  GATE_T_232_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_232_B );
  GATE_T_232_I_3:   AND3 port map ( O=>T_232, 
            I0=>ni_nires_reg_data0pos_2_busQ, 
            I2=>GATE_T_232_A, 
            I1=>GATE_T_232_B );
  GATE_T_233_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_233_A );
  GATE_T_233_I_2:   AND3 port map ( O=>T_233, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1pos_2_busQ, 
            I0=>GATE_T_233_A );
  GATE_T_234_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_234_A );
  GATE_T_234_I_2:   AND3 port map ( O=>T_234, 
            I2=>ni_nires_reg_data3pos_2_busQ, 
            I1=>ni_nires_reg_old_cnt_1_busQ, 
            I0=>GATE_T_234_A );
  GATE_T_235_I_1:   AND3 port map ( O=>T_235, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data2pos_2_busQ, 
            I0=>ni_nires_reg_old_cnt_1_busQ );
  GATE_T_236_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_236_A );
  GATE_T_236_I_2:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_236_B );
  GATE_T_236_I_3:   AND3 port map ( O=>T_236, 
            I0=>ni_nires_reg_data0pos_0_busQ, 
            I2=>GATE_T_236_A, 
            I1=>GATE_T_236_B );
  GATE_T_237_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_1_busQ, 
            O=>GATE_T_237_A );
  GATE_T_237_I_2:   AND3 port map ( O=>T_237, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data1pos_0_busQ, 
            I0=>GATE_T_237_A );
  GATE_T_238_I_1:   INV port map ( I0=>ni_nires_reg_old_cnt_0_busQ, 
            O=>GATE_T_238_A );
  GATE_T_238_I_2:   AND3 port map ( O=>T_238, 
            I2=>ni_nires_reg_data3pos_0_busQ, 
            I1=>ni_nires_reg_old_cnt_1_busQ, 
            I0=>GATE_T_238_A );
  GATE_T_239_I_1:   AND3 port map ( O=>T_239, 
            I2=>ni_nires_reg_old_cnt_0_busQ, 
            I1=>ni_nires_reg_data2pos_0_busQ, 
            I0=>ni_nires_reg_old_cnt_1_busQ );
  GATE_T_240_I_14:   NOR4 port map ( O=>T_240, 
            I3=>ix1598, 
            I2=>ix1578, 
            I1=>nx2294, 
            I0=>nx1271 );
  GATE_T_241_I_1:   NOR3 port map ( O=>T_241, 
            I2=>nx2294, 
            I1=>nx1271, 
            I0=>ix1610 );
  GATE_T_242_I_1:   INV port map ( I0=>TXD_4XQ, 
            O=>GATE_T_242_A );
  GATE_T_242_I_2:   INV port map ( I0=>TXD_5XQ, 
            O=>GATE_T_242_B );
  GATE_T_242_I_3:   AND3 port map ( O=>T_242, 
            I0=>nx1271, 
            I2=>GATE_T_242_A, 
            I1=>GATE_T_242_B );
  GATE_T_243_I_1:   AND3 port map ( O=>T_243, 
            I2=>TXD_4XQ, 
            I1=>TXD_5XQ, 
            I0=>nx1271 );
  GATE_T_244_I_1:   AND2 port map ( O=>T_244, 
            I1=>nx1949, 
            I0=>GATE_T_244_A );
  GATE_T_244_I_2:   INV port map ( O=>GATE_T_244_A, 
            I0=>nx2272 );
  GATE_T_245_I_1:   INV port map ( I0=>nx2272, 
            O=>GATE_T_245_A );
  GATE_T_245_I_2:   AND3 port map ( O=>T_245, 
            I2=>T_577, 
            I1=>T_576, 
            I0=>GATE_T_245_A );
  GATE_T_246_I_1:   NOR4 port map ( I0=>TXD_6XQ, 
            I1=>TXD_5XQ, 
            O=>T_246, 
            I2=>TXD_4XQ, 
            I3=>GATE_T_246_DN );
  GATE_T_246_I_2:   INV port map ( I0=>nx1271, 
            O=>GATE_T_246_DN );
  GATE_T_247_I_1:   INV port map ( I0=>ix1160, 
            O=>GATE_T_247_A );
  GATE_T_247_I_2:   INV port map ( I0=>nx1967, 
            O=>GATE_T_247_B );
  GATE_T_247_I_3:   AND3 port map ( O=>T_247, 
            I0=>ni_nires_reg_data_out_7_busQ, 
            I2=>GATE_T_247_A, 
            I1=>GATE_T_247_B );
  GATE_T_248_I_1:   INV port map ( I0=>nx1967, 
            O=>GATE_T_248_A );
  GATE_T_248_I_2:   AND3 port map ( O=>T_248, 
            I2=>ni_nires_reg_data_out_8_busQ, 
            I1=>ix1160, 
            I0=>GATE_T_248_A );
  GATE_T_249_I_1:   NOR3 port map ( O=>T_249, 
            I2=>ix1610, 
            I1=>nx1271, 
            I0=>nx2272 );
  GATE_T_250_I_1:   AND3 port map ( O=>T_250, 
            I2=>TXD_4XQ, 
            I1=>TXD_6XQ, 
            I0=>nx1271 );
  GATE_T_251_I_1:   AND3 port map ( O=>T_251, 
            I2=>TXD_5XQ, 
            I1=>TXD_6XQ, 
            I0=>nx1271 );
  GATE_T_252_I_1:   AND3 port map ( O=>T_252, 
            I2=>T_582, 
            I1=>T_583, 
            I0=>T_581 );
  GATE_T_253_I_1:   AND3 port map ( O=>T_253, 
            I2=>T_579, 
            I1=>T_580, 
            I0=>T_578 );
  GATE_T_254_I_1:   NOR2 port map ( O=>T_254, 
            I1=>ix1160, 
            I0=>ni_nires_reg_data_out_6_busQ );
  GATE_T_255_I_1:   INV port map ( I0=>nx1647, 
            O=>GATE_T_255_A );
  GATE_T_255_I_2:   AND3 port map ( O=>T_255, 
            I2=>T_594, 
            I1=>T_593, 
            I0=>GATE_T_255_A );
  GATE_T_256_I_1:   AND3 port map ( O=>T_256, 
            I2=>T_592, 
            I1=>nx1647, 
            I0=>T_591 );
  GATE_T_257_I_1:   INV port map ( I0=>nx1595, 
            O=>GATE_T_257_A );
  GATE_T_257_I_2:   AND3 port map ( O=>T_257, 
            I2=>T_590, 
            I1=>T_589, 
            I0=>GATE_T_257_A );
  GATE_T_258_I_1:   AND3 port map ( O=>T_258, 
            I2=>T_588, 
            I1=>nx1647, 
            I0=>T_587 );
  GATE_T_259_I_1:   NOR4 port map ( I0=>nx1519, 
            I1=>nx1647, 
            O=>T_259, 
            I2=>nx1271, 
            I3=>GATE_T_259_DN );
  GATE_T_259_I_2:   INV port map ( I0=>ni_nires_reg_data_out_10_busQ, 
            O=>GATE_T_259_DN );
  GATE_T_260_I_1:   NOR4 port map ( I0=>nx1271, 
            I1=>nx1647, 
            O=>T_260, 
            I2=>ix1266, 
            I3=>GATE_T_260_DN );
  GATE_T_260_I_2:   INV port map ( I0=>ni_nires_reg_data_out_10_busQ, 
            O=>GATE_T_260_DN );
  GATE_T_261_I_1:   NOR4 port map ( I0=>nx1519, 
            I1=>nx1595, 
            O=>T_261, 
            I2=>nx1271, 
            I3=>GATE_T_261_DN );
  GATE_T_261_I_2:   INV port map ( I0=>ni_nires_reg_data_out_10_busQ, 
            O=>GATE_T_261_DN );
  GATE_T_262_I_1:   NOR4 port map ( I0=>nx1271, 
            I1=>nx1595, 
            O=>T_262, 
            I2=>ix1266, 
            I3=>GATE_T_262_DN );
  GATE_T_262_I_2:   INV port map ( I0=>ni_nires_reg_data_out_10_busQ, 
            O=>GATE_T_262_DN );
  GATE_T_263_I_1:   AND2 port map ( O=>T_263, 
            I1=>nx1271, 
            I0=>GATE_T_263_A );
  GATE_T_263_I_2:   INV port map ( O=>GATE_T_263_A, 
            I0=>TXD_8XQ );
  GATE_T_264_I_1:   INV port map ( I0=>nx1909, 
            O=>GATE_T_264_A );
  GATE_T_264_I_2:   AND3 port map ( O=>T_264, 
            I2=>T_602, 
            I1=>T_601, 
            I0=>GATE_T_264_A );
  GATE_T_265_I_1:   AND3 port map ( O=>T_265, 
            I2=>T_600, 
            I1=>nx1909, 
            I0=>T_599 );
  GATE_T_266_I_1:   NOR4 port map ( I0=>nx1519, 
            I1=>nx1595, 
            O=>T_266, 
            I2=>nx1271, 
            I3=>GATE_T_266_DN );
  GATE_T_266_I_2:   INV port map ( I0=>ni_nires_reg_data_out_11_busQ, 
            O=>GATE_T_266_DN );
  GATE_T_267_I_1:   NOR4 port map ( I0=>nx1519, 
            I1=>ix1578, 
            O=>T_267, 
            I2=>nx1271, 
            I3=>GATE_T_267_DN );
  GATE_T_267_I_2:   INV port map ( I0=>ni_nires_reg_data_out_11_busQ, 
            O=>GATE_T_267_DN );
  GATE_T_268_I_3:   AND4 port map ( O=>T_268, 
            I3=>nx1519, 
            I2=>ni_nires_reg_data_out_12_busQ, 
            I1=>GATE_T_268_B, 
            I0=>GATE_T_268_A );
  GATE_T_268_I_2:   INV port map ( I0=>nx1595, 
            O=>GATE_T_268_B );
  GATE_T_268_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_268_A );
  GATE_T_269_I_3:   AND4 port map ( O=>T_269, 
            I3=>nx1519, 
            I2=>ni_nires_reg_data_out_12_busQ, 
            I1=>GATE_T_269_B, 
            I0=>GATE_T_269_A );
  GATE_T_269_I_2:   INV port map ( I0=>ix1578, 
            O=>GATE_T_269_B );
  GATE_T_269_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_269_A );
  GATE_T_270_I_1:   INV port map ( I0=>TXD_8XQ, 
            O=>GATE_T_270_A );
  GATE_T_270_I_2:   INV port map ( I0=>TXD_9XQ, 
            O=>GATE_T_270_B );
  GATE_T_270_I_3:   AND3 port map ( O=>T_270, 
            I0=>nx1271, 
            I2=>GATE_T_270_A, 
            I1=>GATE_T_270_B );
  GATE_T_271_I_1:   AND3 port map ( O=>T_271, 
            I2=>TXD_8XQ, 
            I1=>TXD_9XQ, 
            I0=>nx1271 );
  GATE_T_272_I_1:   AND3 port map ( O=>T_272, 
            I2=>T_622, 
            I1=>T_623, 
            I0=>T_621 );
  GATE_T_273_I_1:   AND3 port map ( O=>T_273, 
            I2=>T_619, 
            I1=>T_620, 
            I0=>T_618 );
  GATE_T_274_I_1:   INV port map ( I0=>ix1160, 
            O=>GATE_T_274_A );
  GATE_T_274_I_2:   AND3 port map ( O=>T_274, 
            I2=>T_617, 
            I1=>T_616, 
            I0=>GATE_T_274_A );
  GATE_T_275_I_1:   INV port map ( I0=>ix1160, 
            O=>GATE_T_275_A );
  GATE_T_275_I_2:   AND3 port map ( O=>T_275, 
            I2=>T_615, 
            I1=>T_614, 
            I0=>GATE_T_275_A );
  GATE_T_276_I_1:   INV port map ( I0=>ix1084, 
            O=>GATE_T_276_A );
  GATE_T_276_I_2:   AND3 port map ( O=>T_276, 
            I2=>T_613, 
            I1=>T_612, 
            I0=>GATE_T_276_A );
  GATE_T_277_I_1:   INV port map ( I0=>ix1084, 
            O=>GATE_T_277_A );
  GATE_T_277_I_2:   AND3 port map ( O=>T_277, 
            I2=>T_611, 
            I1=>T_610, 
            I0=>GATE_T_277_A );
  GATE_T_278_I_1:   INV port map ( I0=>nx1909, 
            O=>GATE_T_278_A );
  GATE_T_278_I_2:   AND3 port map ( O=>T_278, 
            I2=>T_609, 
            I1=>T_608, 
            I0=>GATE_T_278_A );
  GATE_T_279_I_1:   AND3 port map ( O=>T_279, 
            I2=>T_607, 
            I1=>nx1909, 
            I0=>T_606 );
  GATE_T_280_I_1:   NOR4 port map ( I0=>nx1595, 
            I1=>nx1909, 
            O=>T_280, 
            I2=>nx1271, 
            I3=>GATE_T_280_DN );
  GATE_T_280_I_2:   INV port map ( I0=>ni_nires_reg_data_out_12_busQ, 
            O=>GATE_T_280_DN );
  GATE_T_281_I_3:   AND4 port map ( O=>T_281, 
            I3=>nx1909, 
            I2=>ni_nires_reg_data_out_13_busQ, 
            I1=>GATE_T_281_B, 
            I0=>GATE_T_281_A );
  GATE_T_281_I_2:   INV port map ( I0=>nx1595, 
            O=>GATE_T_281_B );
  GATE_T_281_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_281_A );
  GATE_T_282_I_1:   NOR4 port map ( I0=>TXD_10XQ, 
            I1=>TXD_9XQ, 
            O=>T_282, 
            I2=>TXD_8XQ, 
            I3=>GATE_T_282_DN );
  GATE_T_282_I_2:   INV port map ( I0=>nx1271, 
            O=>GATE_T_282_DN );
  GATE_T_283_I_1:   AND3 port map ( O=>T_283, 
            I2=>TXD_8XQ, 
            I1=>TXD_10XQ, 
            I0=>nx1271 );
  GATE_T_284_I_1:   AND3 port map ( O=>T_284, 
            I2=>TXD_9XQ, 
            I1=>TXD_10XQ, 
            I0=>nx1271 );
  GATE_T_285_I_3:   AND4 port map ( O=>T_285, 
            I3=>nx1647, 
            I2=>ix1610, 
            I1=>GATE_T_285_B, 
            I0=>GATE_T_285_A );
  GATE_T_285_I_2:   INV port map ( I0=>nx1851, 
            O=>GATE_T_285_B );
  GATE_T_285_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_285_A );
  GATE_T_286_I_14:   NOR4 port map ( O=>T_286, 
            I3=>nx1759, 
            I2=>nx1647, 
            I1=>ix1598, 
            I0=>nx1271 );
  GATE_T_287_I_1:   INV port map ( I0=>nx1851, 
            O=>GATE_T_287_A );
  GATE_T_287_I_2:   INV port map ( I0=>nx1271, 
            O=>GATE_T_287_B );
  GATE_T_287_I_3:   AND3 port map ( O=>T_287, 
            I0=>nx1595, 
            I2=>GATE_T_287_A, 
            I1=>GATE_T_287_B );
  GATE_T_288_I_1:   NOR3 port map ( O=>T_288, 
            I2=>ix1610, 
            I1=>nx1271, 
            I0=>nx1759 );
  GATE_T_289_I_1:   AND2 port map ( O=>T_289, 
            I1=>nx1271, 
            I0=>GATE_T_289_A );
  GATE_T_289_I_2:   INV port map ( O=>GATE_T_289_A, 
            I0=>TXD_12XQ );
  GATE_T_290_I_1:   AND4 port map ( O=>T_290, 
            I3=>ix1164, 
            I2=>ix1160, 
            I1=>ix1266, 
            I0=>GATE_T_290_A );
  GATE_T_290_I_2:   INV port map ( I0=>ni_nires_reg_data_out_15_busQ, 
            O=>GATE_T_290_A );
  GATE_T_291_I_1:   NOR3 port map ( O=>T_291, 
            I2=>ix1084, 
            I1=>ni_nires_reg_data_out_14_busQ, 
            I0=>ix1164 );
  GATE_T_292_I_1:   INV port map ( I0=>ni_nires_reg_data_out_15_busQ, 
            O=>GATE_T_292_A );
  GATE_T_292_I_2:   AND3 port map ( O=>T_292, 
            I2=>ix1084, 
            I1=>ix1160, 
            I0=>GATE_T_292_A );
  GATE_T_293_I_1:   NOR3 port map ( O=>T_293, 
            I2=>ix1266, 
            I1=>ni_nires_reg_data_out_14_busQ, 
            I0=>ix1084 );
  GATE_T_294_I_1:   NOR2 port map ( O=>T_294, 
            I1=>ix1160, 
            I0=>ni_nires_reg_data_out_14_busQ );
  GATE_T_295_I_14:   NOR4 port map ( O=>T_295, 
            I3=>nx1851, 
            I2=>ix1598, 
            I1=>ix1578, 
            I0=>nx1271 );
  GATE_T_296_I_1:   NOR3 port map ( O=>T_296, 
            I2=>ix1610, 
            I1=>nx1271, 
            I0=>nx1851 );
  GATE_T_297_I_1:   INV port map ( I0=>TXD_12XQ, 
            O=>GATE_T_297_A );
  GATE_T_297_I_2:   AND3 port map ( O=>T_297, 
            I2=>TXD_13XQ, 
            I1=>nx1271, 
            I0=>GATE_T_297_A );
  GATE_T_298_I_1:   INV port map ( I0=>TXD_13XQ, 
            O=>GATE_T_298_A );
  GATE_T_298_I_2:   AND3 port map ( O=>T_298, 
            I2=>TXD_12XQ, 
            I1=>nx1271, 
            I0=>GATE_T_298_A );
  GATE_T_299_I_1:   AND2 port map ( O=>T_299, 
            I1=>nx1949, 
            I0=>GATE_T_299_A );
  GATE_T_299_I_2:   INV port map ( O=>GATE_T_299_A, 
            I0=>nx1815 );
  GATE_T_300_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_300_A );
  GATE_T_300_I_2:   AND3 port map ( O=>T_300, 
            I2=>ix1578, 
            I1=>ix1610, 
            I0=>GATE_T_300_A );
  GATE_T_301_I_1:   AND2 port map ( O=>T_301, 
            I1=>nx1595, 
            I0=>GATE_T_301_A );
  GATE_T_301_I_2:   INV port map ( O=>GATE_T_301_A, 
            I0=>nx1271 );
  GATE_T_302_I_1:   NOR3 port map ( O=>T_302, 
            I2=>ix1084, 
            I1=>ni_nires_reg_data_out_15_busQ, 
            I0=>ix1164 );
  GATE_T_303_I_1:   INV port map ( I0=>ni_nires_reg_data_out_16_busQ, 
            O=>GATE_T_303_A );
  GATE_T_303_I_2:   AND3 port map ( O=>T_303, 
            I2=>ix1160, 
            I1=>ix1164, 
            I0=>GATE_T_303_A );
  GATE_T_304_I_1:   INV port map ( I0=>ni_nires_reg_data_out_16_busQ, 
            O=>GATE_T_304_A );
  GATE_T_304_I_2:   AND3 port map ( O=>T_304, 
            I2=>ix1084, 
            I1=>ix1160, 
            I0=>GATE_T_304_A );
  GATE_T_305_I_1:   NOR2 port map ( O=>T_305, 
            I1=>ix1160, 
            I0=>ni_nires_reg_data_out_15_busQ );
  GATE_T_306_I_1:   INV port map ( I0=>nx1815, 
            O=>GATE_T_306_A );
  GATE_T_306_I_2:   AND3 port map ( O=>T_306, 
            I2=>T_634, 
            I1=>T_633, 
            I0=>GATE_T_306_A );
  GATE_T_307_I_1:   AND4 port map ( O=>T_307, 
            I3=>nx1271, 
            I2=>TXD_12XQ, 
            I1=>TXD_13XQ, 
            I0=>GATE_T_307_A );
  GATE_T_307_I_2:   INV port map ( I0=>TXD_14XQ, 
            O=>GATE_T_307_A );
  GATE_T_308_I_1:   INV port map ( I0=>ix1160, 
            O=>GATE_T_308_A );
  GATE_T_308_I_2:   INV port map ( I0=>nx1967, 
            O=>GATE_T_308_B );
  GATE_T_308_I_3:   AND3 port map ( O=>T_308, 
            I0=>ni_nires_reg_data_out_17_busQ, 
            I2=>GATE_T_308_A, 
            I1=>GATE_T_308_B );
  GATE_T_309_I_1:   INV port map ( I0=>nx1967, 
            O=>GATE_T_309_A );
  GATE_T_309_I_2:   AND3 port map ( O=>T_309, 
            I2=>ni_nires_reg_data_out_18_busQ, 
            I1=>ix1160, 
            I0=>GATE_T_309_A );
  GATE_T_310_I_1:   NOR3 port map ( O=>T_310, 
            I2=>ix1610, 
            I1=>nx1271, 
            I0=>nx1815 );
  GATE_T_311_I_1:   INV port map ( I0=>TXD_12XQ, 
            O=>GATE_T_311_A );
  GATE_T_311_I_2:   AND3 port map ( O=>T_311, 
            I2=>TXD_14XQ, 
            I1=>nx1271, 
            I0=>GATE_T_311_A );
  GATE_T_312_I_1:   INV port map ( I0=>TXD_13XQ, 
            O=>GATE_T_312_A );
  GATE_T_312_I_2:   AND3 port map ( O=>T_312, 
            I2=>TXD_14XQ, 
            I1=>nx1271, 
            I0=>GATE_T_312_A );
  GATE_T_313_I_1:   NOR3 port map ( O=>T_313, 
            I2=>ix1578, 
            I1=>ix1524, 
            I0=>nx1595 );
  GATE_T_314_I_1:   NOR2 port map ( O=>T_314, 
            I1=>ix1610, 
            I0=>nx1595 );
  GATE_T_315_I_1:   AND3 port map ( O=>T_315, 
            I2=>T_639, 
            I1=>T_640, 
            I0=>T_638 );
  GATE_T_316_I_1:   AND3 port map ( O=>T_316, 
            I2=>T_636, 
            I1=>T_637, 
            I0=>T_635 );
  GATE_T_317_I_1:   NOR2 port map ( O=>T_317, 
            I1=>ix1160, 
            I0=>ni_nires_reg_data_out_16_busQ );
  GATE_T_318_I_1:   AND3 port map ( O=>T_318, 
            I2=>T_642, 
            I1=>T_643, 
            I0=>T_641 );
  GATE_T_319_I_1:   NOR2 port map ( O=>T_319, 
            I1=>nx1271, 
            I0=>ni_nires_reg_validQ );
  GATE_T_320_I_1:   AND3 port map ( O=>T_320, 
            I2=>T_654, 
            I1=>nx1647, 
            I0=>T_653 );
  GATE_T_321_I_1:   INV port map ( I0=>nx1647, 
            O=>GATE_T_321_A );
  GATE_T_321_I_2:   AND3 port map ( O=>T_321, 
            I2=>T_652, 
            I1=>T_651, 
            I0=>GATE_T_321_A );
  GATE_T_322_I_1:   AND3 port map ( O=>T_322, 
            I2=>T_650, 
            I1=>nx1647, 
            I0=>T_649 );
  GATE_T_323_I_1:   INV port map ( I0=>nx1595, 
            O=>GATE_T_323_A );
  GATE_T_323_I_2:   AND3 port map ( O=>T_323, 
            I2=>T_648, 
            I1=>T_647, 
            I0=>GATE_T_323_A );
  GATE_T_324_I_1:   NOR4 port map ( I0=>nx1519, 
            I1=>nx1647, 
            O=>T_324, 
            I2=>nx1271, 
            I3=>GATE_T_324_DN );
  GATE_T_324_I_2:   INV port map ( I0=>ni_nires_reg_data_out_0_busQ, 
            O=>GATE_T_324_DN );
  GATE_T_325_I_1:   NOR4 port map ( I0=>nx1271, 
            I1=>nx1647, 
            O=>T_325, 
            I2=>ix1266, 
            I3=>GATE_T_325_DN );
  GATE_T_325_I_2:   INV port map ( I0=>ni_nires_reg_data_out_0_busQ, 
            O=>GATE_T_325_DN );
  GATE_T_326_I_1:   NOR4 port map ( I0=>nx1519, 
            I1=>nx1595, 
            O=>T_326, 
            I2=>nx1271, 
            I3=>GATE_T_326_DN );
  GATE_T_326_I_2:   INV port map ( I0=>ni_nires_reg_data_out_0_busQ, 
            O=>GATE_T_326_DN );
  GATE_T_327_I_1:   NOR4 port map ( I0=>nx1271, 
            I1=>nx1595, 
            O=>T_327, 
            I2=>ix1266, 
            I3=>GATE_T_327_DN );
  GATE_T_327_I_2:   INV port map ( I0=>ni_nires_reg_data_out_0_busQ, 
            O=>GATE_T_327_DN );
  GATE_T_328_I_1:   AND2 port map ( O=>T_328, 
            I1=>nx1271, 
            I0=>GATE_T_328_A );
  GATE_T_328_I_2:   INV port map ( O=>GATE_T_328_A, 
            I0=>TXD_0XQ );
  GATE_T_329_I_1:   AND3 port map ( O=>T_329, 
            I2=>T_662, 
            I1=>nx1909, 
            I0=>T_661 );
  GATE_T_330_I_1:   INV port map ( I0=>nx1909, 
            O=>GATE_T_330_A );
  GATE_T_330_I_2:   AND3 port map ( O=>T_330, 
            I2=>T_660, 
            I1=>T_659, 
            I0=>GATE_T_330_A );
  GATE_T_331_I_3:   AND4 port map ( O=>T_331, 
            I3=>nx1519, 
            I2=>ni_nires_reg_data_out_2_busQ, 
            I1=>GATE_T_331_B, 
            I0=>GATE_T_331_A );
  GATE_T_331_I_2:   INV port map ( I0=>nx1595, 
            O=>GATE_T_331_B );
  GATE_T_331_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_331_A );
  GATE_T_332_I_3:   AND4 port map ( O=>T_332, 
            I3=>nx1519, 
            I2=>ni_nires_reg_data_out_2_busQ, 
            I1=>GATE_T_332_B, 
            I0=>GATE_T_332_A );
  GATE_T_332_I_2:   INV port map ( I0=>ix1578, 
            O=>GATE_T_332_B );
  GATE_T_332_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_332_A );
  GATE_T_333_I_1:   NOR4 port map ( I0=>nx1519, 
            I1=>nx1595, 
            O=>T_333, 
            I2=>nx1271, 
            I3=>GATE_T_333_DN );
  GATE_T_333_I_2:   INV port map ( I0=>ni_nires_reg_data_out_1_busQ, 
            O=>GATE_T_333_DN );
  GATE_T_334_I_1:   NOR4 port map ( I0=>nx1519, 
            I1=>ix1578, 
            O=>T_334, 
            I2=>nx1271, 
            I3=>GATE_T_334_DN );
  GATE_T_334_I_2:   INV port map ( I0=>ni_nires_reg_data_out_1_busQ, 
            O=>GATE_T_334_DN );
  GATE_T_335_I_1:   INV port map ( I0=>TXD_0XQ, 
            O=>GATE_T_335_A );
  GATE_T_335_I_2:   AND3 port map ( O=>T_335, 
            I2=>TXD_1XQ, 
            I1=>nx1271, 
            I0=>GATE_T_335_A );
  GATE_T_336_I_1:   INV port map ( I0=>TXD_1XQ, 
            O=>GATE_T_336_A );
  GATE_T_336_I_2:   AND3 port map ( O=>T_336, 
            I2=>TXD_0XQ, 
            I1=>nx1271, 
            I0=>GATE_T_336_A );
  GATE_T_337_I_1:   AND3 port map ( O=>T_337, 
            I2=>T_682, 
            I1=>T_683, 
            I0=>T_681 );
  GATE_T_338_I_1:   AND3 port map ( O=>T_338, 
            I2=>T_679, 
            I1=>T_680, 
            I0=>T_678 );
  GATE_T_339_I_1:   INV port map ( I0=>ix1160, 
            O=>GATE_T_339_A );
  GATE_T_339_I_2:   AND3 port map ( O=>T_339, 
            I2=>T_677, 
            I1=>T_676, 
            I0=>GATE_T_339_A );
  GATE_T_340_I_1:   INV port map ( I0=>ix1160, 
            O=>GATE_T_340_A );
  GATE_T_340_I_2:   AND3 port map ( O=>T_340, 
            I2=>T_675, 
            I1=>T_674, 
            I0=>GATE_T_340_A );
  GATE_T_341_I_1:   INV port map ( I0=>ix1084, 
            O=>GATE_T_341_A );
  GATE_T_341_I_2:   AND3 port map ( O=>T_341, 
            I2=>T_673, 
            I1=>T_672, 
            I0=>GATE_T_341_A );
  GATE_T_342_I_1:   INV port map ( I0=>ix1084, 
            O=>GATE_T_342_A );
  GATE_T_342_I_2:   AND3 port map ( O=>T_342, 
            I2=>T_671, 
            I1=>T_670, 
            I0=>GATE_T_342_A );
  GATE_T_343_I_1:   AND3 port map ( O=>T_343, 
            I2=>T_669, 
            I1=>nx1909, 
            I0=>T_668 );
  GATE_T_344_I_1:   INV port map ( I0=>nx1909, 
            O=>GATE_T_344_A );
  GATE_T_344_I_2:   AND3 port map ( O=>T_344, 
            I2=>T_667, 
            I1=>T_666, 
            I0=>GATE_T_344_A );
  GATE_T_345_I_3:   AND4 port map ( O=>T_345, 
            I3=>nx1909, 
            I2=>ni_nires_reg_data_out_3_busQ, 
            I1=>GATE_T_345_B, 
            I0=>GATE_T_345_A );
  GATE_T_345_I_2:   INV port map ( I0=>nx1595, 
            O=>GATE_T_345_B );
  GATE_T_345_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_345_A );
  GATE_T_346_I_1:   NOR4 port map ( I0=>nx1595, 
            I1=>nx1909, 
            O=>T_346, 
            I2=>nx1271, 
            I3=>GATE_T_346_DN );
  GATE_T_346_I_2:   INV port map ( I0=>ni_nires_reg_data_out_2_busQ, 
            O=>GATE_T_346_DN );
  GATE_T_347_I_1:   AND4 port map ( O=>T_347, 
            I3=>nx1271, 
            I2=>TXD_0XQ, 
            I1=>TXD_1XQ, 
            I0=>GATE_T_347_A );
  GATE_T_347_I_2:   INV port map ( I0=>TXD_2XQ, 
            O=>GATE_T_347_A );
  GATE_T_348_I_1:   INV port map ( I0=>TXD_0XQ, 
            O=>GATE_T_348_A );
  GATE_T_348_I_2:   AND3 port map ( O=>T_348, 
            I2=>TXD_2XQ, 
            I1=>nx1271, 
            I0=>GATE_T_348_A );
  GATE_T_349_I_1:   INV port map ( I0=>TXD_1XQ, 
            O=>GATE_T_349_A );
  GATE_T_349_I_2:   AND3 port map ( O=>T_349, 
            I2=>TXD_2XQ, 
            I1=>nx1271, 
            I0=>GATE_T_349_A );
  GATE_T_350_I_1:   AND3 port map ( O=>T_350, 
            I2=>ix1160, 
            I1=>ix1084, 
            I0=>ix1164 );
  GATE_T_351_I_1:   AND3 port map ( O=>T_351, 
            I2=>ix1084, 
            I1=>ix1266, 
            I0=>ix1160 );
  GATE_T_352_I_1:   AND2 port map ( O=>T_352, 
            I1=>ni_nires_reg_validQ, 
            I0=>GATE_T_352_A );
  GATE_T_352_I_2:   INV port map ( O=>GATE_T_352_A, 
            I0=>nx1271 );
  GATE_T_353_I_1:   AND2 port map ( O=>T_353, 
            I1=>nx1271, 
            I0=>TX_ENQ );
  GATE_T_354_I_14:   NOR4 port map ( O=>T_354, 
            I3=>nx1647, 
            I2=>ix1598, 
            I1=>nx1271, 
            I0=>nx2236 );
  GATE_T_355_I_3:   AND4 port map ( O=>T_355, 
            I3=>nx1647, 
            I2=>ix1610, 
            I1=>GATE_T_355_B, 
            I0=>GATE_T_355_A );
  GATE_T_355_I_2:   INV port map ( I0=>nx2294, 
            O=>GATE_T_355_B );
  GATE_T_355_I_1:   INV port map ( I0=>nx1271, 
            O=>GATE_T_355_A );
  GATE_T_356_I_1:   NOR3 port map ( O=>T_356, 
            I2=>nx1271, 
            I1=>nx2236, 
            I0=>ix1610 );
  GATE_T_357_I_1:   INV port map ( I0=>nx2294, 
            O=>GATE_T_357_A );
  GATE_T_357_I_2:   INV port map ( I0=>nx1271, 
            O=>GATE_T_357_B );
  GATE_T_357_I_3:   AND3 port map ( O=>T_357, 
            I0=>nx1595, 
            I2=>GATE_T_357_A, 
            I1=>GATE_T_357_B );
  GATE_T_358_I_1:   AND2 port map ( O=>T_358, 
            I1=>nx1271, 
            I0=>GATE_T_358_A );
  GATE_T_358_I_2:   INV port map ( O=>GATE_T_358_A, 
            I0=>TXD_4XQ );
  GATE_T_359_I_1:   NOR3 port map ( O=>T_359, 
            I2=>ix1084, 
            I1=>ni_nires_reg_data_out_5_busQ, 
            I0=>ix1164 );
  GATE_T_360_I_1:   INV port map ( I0=>ni_nires_reg_data_out_6_busQ, 
            O=>GATE_T_360_A );
  GATE_T_360_I_2:   AND3 port map ( O=>T_360, 
            I2=>ix1160, 
            I1=>ix1164, 
            I0=>GATE_T_360_A );
  GATE_T_361_I_1:   INV port map ( I0=>ni_nires_reg_data_out_6_busQ, 
            O=>GATE_T_361_A );
  GATE_T_361_I_2:   AND3 port map ( O=>T_361, 
            I2=>ix1084, 
            I1=>ix1160, 
            I0=>GATE_T_361_A );
  GATE_T_362_I_1:   NOR2 port map ( O=>T_362, 
            I1=>ix1160, 
            I0=>ni_nires_reg_data_out_5_busQ );
  GATE_T_363_I_1:   AND4 port map ( O=>T_363, 
            I3=>ix1164, 
            I2=>ix1160, 
            I1=>ix1266, 
            I0=>GATE_T_363_A );
  GATE_T_363_I_2:   INV port map ( I0=>ni_nires_reg_data_out_5_busQ, 
            O=>GATE_T_363_A );
  GATE_T_364_I_1:   NOR3 port map ( O=>T_364, 
            I2=>ix1084, 
            I1=>ni_nires_reg_data_out_4_busQ, 
            I0=>ix1164 );
  GATE_T_365_I_1:   INV port map ( I0=>ni_nires_reg_data_out_5_busQ, 
            O=>GATE_T_365_A );
  GATE_T_365_I_2:   AND3 port map ( O=>T_365, 
            I2=>ix1084, 
            I1=>ix1160, 
            I0=>GATE_T_365_A );
  GATE_T_366_I_1:   NOR3 port map ( O=>T_366, 
            I2=>ix1266, 
            I1=>ni_nires_reg_data_out_4_busQ, 
            I0=>ix1084 );
  GATE_T_367_I_1:   NOR2 port map ( O=>T_367, 
            I1=>ix1160, 
            I0=>ni_nires_reg_data_out_4_busQ );
  GATE_T_368_I_1:   AND2 port map ( O=>T_368, 
            I1=>jTCKPIN, 
            I0=>GATE_T_368_A );
  GATE_T_368_I_2:   INV port map ( O=>GATE_T_368_A, 
            I0=>j2c_reg_clear_AR );
  GATE_T_369_I_1:   AND4 port map ( O=>T_369, 
            I3=>T_789, 
            I2=>T_790, 
            I1=>T_791, 
            I0=>T_792 );
  GATE_T_370_I_1:   AND4 port map ( O=>T_370, 
            I3=>T_786, 
            I2=>T_787, 
            I1=>T_788, 
            I0=>ix1160 );
  GATE_T_371_I_1:   AND4 port map ( O=>T_371, 
            I3=>T_783, 
            I2=>T_784, 
            I1=>T_785, 
            I0=>ix1084 );
  GATE_T_372_I_1:   AND4 port map ( O=>T_372, 
            I3=>T_780, 
            I2=>T_781, 
            I1=>T_782, 
            I0=>ix1266 );
  GATE_T_373_I_1:   AND4 port map ( O=>T_373, 
            I3=>T_777, 
            I2=>T_778, 
            I1=>T_779, 
            I0=>GATE_T_373_A );
  GATE_T_373_I_2:   INV port map ( I0=>ix71, 
            O=>GATE_T_373_A );
  GATE_T_374_I_1:   AND3 port map ( O=>T_374, 
            I2=>T_775, 
            I1=>T_776, 
            I0=>T_774 );
  GATE_T_375_I_1:   AND3 port map ( O=>T_375, 
            I2=>T_772, 
            I1=>T_773, 
            I0=>T_771 );
  GATE_T_376_I_1:   AND3 port map ( O=>T_376, 
            I2=>T_769, 
            I1=>T_770, 
            I0=>T_768 );
  GATE_T_377_I_1:   AND3 port map ( O=>T_377, 
            I2=>T_766, 
            I1=>T_767, 
            I0=>T_765 );
  GATE_T_378_I_1:   AND3 port map ( O=>T_378, 
            I2=>T_763, 
            I1=>T_764, 
            I0=>T_762 );
  GATE_T_379_I_1:   AND3 port map ( O=>T_379, 
            I2=>T_761, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>T_760 );
  GATE_T_380_I_1:   NOR4 port map ( I0=>DIS_JTGPIN, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            O=>T_380, 
            I2=>nx1912, 
            I3=>GATE_T_380_DN );
  GATE_T_380_I_2:   INV port map ( I0=>j2c_reg_cmdreg_1_busQ, 
            O=>GATE_T_380_DN );
  GATE_T_381_I_3:   AND4 port map ( O=>T_381, 
            I3=>j2c_reg_cmdreg_1_busQ, 
            I2=>j2c_reg_cmdreg_2_busQ, 
            I1=>GATE_T_381_B, 
            I0=>GATE_T_381_A );
  GATE_T_381_I_2:   INV port map ( I0=>j2c_bitcnt_2_busQ, 
            O=>GATE_T_381_B );
  GATE_T_381_I_1:   INV port map ( I0=>DIS_JTGPIN, 
            O=>GATE_T_381_A );
  GATE_T_382_I_1:   NOR4 port map ( I0=>DIS_JTGPIN, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            O=>T_382, 
            I2=>j2c_reg_cmdreg_1_busQ, 
            I3=>GATE_T_382_DN );
  GATE_T_382_I_2:   INV port map ( I0=>nx1195, 
            O=>GATE_T_382_DN );
  GATE_T_383_I_3:   AND4 port map ( O=>T_383, 
            I3=>j2c_reg_cmdreg_2_busQ, 
            I2=>j2c_reg_cmdreg_0_busQ, 
            I1=>GATE_T_383_B, 
            I0=>GATE_T_383_A );
  GATE_T_383_I_2:   INV port map ( I0=>j2c_reg_cmdreg_1_busQ, 
            O=>GATE_T_383_B );
  GATE_T_383_I_1:   INV port map ( I0=>DIS_JTGPIN, 
            O=>GATE_T_383_A );
  GATE_T_384_I_1:   AND2 port map ( O=>T_384, 
            I1=>DIS_JTGPIN, 
            I0=>GATE_T_384_A );
  GATE_T_384_I_2:   INV port map ( O=>GATE_T_384_A, 
            I0=>SDAPIN );
  GATE_T_385_I_1:   AND3 port map ( O=>T_385, 
            I2=>T_759, 
            I1=>ID_2_0_busQ, 
            I0=>T_758 );
  GATE_T_386_I_1:   AND3 port map ( O=>T_386, 
            I2=>T_757, 
            I1=>ID_2_1_busQ, 
            I0=>T_756 );
  GATE_T_387_I_1:   AND3 port map ( O=>T_387, 
            I2=>T_755, 
            I1=>ID_2_2_busQ, 
            I0=>T_754 );
  GATE_T_388_I_1:   AND3 port map ( O=>T_388, 
            I2=>T_753, 
            I1=>ID_2_3_busQ, 
            I0=>T_752 );
  GATE_T_389_I_1:   AND3 port map ( O=>T_389, 
            I2=>T_751, 
            I1=>ID_2_4_busQ, 
            I0=>T_750 );
  GATE_T_390_I_1:   AND3 port map ( O=>T_390, 
            I2=>T_749, 
            I1=>ID_2_6_busQ, 
            I0=>T_748 );
  GATE_T_391_I_1:   AND3 port map ( O=>T_391, 
            I2=>T_747, 
            I1=>ID_2_5_busQ, 
            I0=>T_746 );
  GATE_T_392_I_1:   INV port map ( I0=>j2c_bitcnt_0_busQ, 
            O=>GATE_T_392_A );
  GATE_T_392_I_2:   AND3 port map ( O=>T_392, 
            I2=>T_745, 
            I1=>T_744, 
            I0=>GATE_T_392_A );
  GATE_T_393_I_1:   INV port map ( I0=>j2c_bitcnt_0_busQ, 
            O=>GATE_T_393_A );
  GATE_T_393_I_2:   AND3 port map ( O=>T_393, 
            I2=>T_743, 
            I1=>T_742, 
            I0=>GATE_T_393_A );
  GATE_T_394_I_1:   INV port map ( I0=>j2c_bitcnt_0_busQ, 
            O=>GATE_T_394_A );
  GATE_T_394_I_2:   AND3 port map ( O=>T_394, 
            I2=>T_741, 
            I1=>T_740, 
            I0=>GATE_T_394_A );
  GATE_T_395_I_1:   INV port map ( I0=>j2c_bitcnt_0_busQ, 
            O=>GATE_T_395_A );
  GATE_T_395_I_2:   AND3 port map ( O=>T_395, 
            I2=>T_739, 
            I1=>T_738, 
            I0=>GATE_T_395_A );
  GATE_T_396_I_1:   AND3 port map ( O=>T_396, 
            I2=>T_737, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>T_736 );
  GATE_T_397_I_1:   AND3 port map ( O=>T_397, 
            I2=>T_735, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>T_734 );
  GATE_T_398_I_1:   AND3 port map ( O=>T_398, 
            I2=>T_733, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>T_732 );
  GATE_T_399_I_1:   AND4 port map ( O=>T_399, 
            I3=>j2c_bitcnt_0_busQ, 
            I2=>j2c_bitcnt_1_busQ, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>FAULTPIN );
  GATE_T_400_I_1:   AND4 port map ( O=>T_400, 
            I3=>ix397, 
            I2=>ix385, 
            I1=>ix373, 
            I0=>j2c_reg_creg0hm_6_busQ );
  GATE_T_401_I_1:   NOR2 port map ( O=>T_401, 
            I1=>ix397, 
            I0=>j2c_reg_creg0hm_6_busQ );
  GATE_T_402_I_1:   NOR2 port map ( O=>T_402, 
            I1=>ix385, 
            I0=>j2c_reg_creg0hm_6_busQ );
  GATE_T_403_I_1:   NOR2 port map ( O=>T_403, 
            I1=>ix373, 
            I0=>j2c_reg_creg0hm_6_busQ );
  GATE_T_404_I_1:   AND4 port map ( O=>T_404, 
            I3=>ix373, 
            I2=>j2c_reg_creg0hm_5_busQ, 
            I1=>ix385, 
            I0=>GATE_T_404_A );
  GATE_T_404_I_2:   INV port map ( I0=>ix397, 
            O=>GATE_T_404_A );
  GATE_T_405_I_1:   AND2 port map ( O=>T_405, 
            I1=>ix397, 
            I0=>GATE_T_405_A );
  GATE_T_405_I_2:   INV port map ( O=>GATE_T_405_A, 
            I0=>j2c_reg_creg0hm_5_busQ );
  GATE_T_406_I_1:   NOR2 port map ( O=>T_406, 
            I1=>ix385, 
            I0=>j2c_reg_creg0hm_5_busQ );
  GATE_T_407_I_1:   NOR2 port map ( O=>T_407, 
            I1=>ix373, 
            I0=>j2c_reg_creg0hm_5_busQ );
  GATE_T_408_I_1:   AND4 port map ( O=>T_408, 
            I3=>ix397, 
            I2=>ix385, 
            I1=>j2c_reg_creg0hm_4_busQ, 
            I0=>GATE_T_408_A );
  GATE_T_408_I_2:   INV port map ( I0=>ix373, 
            O=>GATE_T_408_A );
  GATE_T_409_I_1:   NOR2 port map ( O=>T_409, 
            I1=>ix397, 
            I0=>j2c_reg_creg0hm_4_busQ );
  GATE_T_410_I_1:   NOR2 port map ( O=>T_410, 
            I1=>ix385, 
            I0=>j2c_reg_creg0hm_4_busQ );
  GATE_T_411_I_1:   AND2 port map ( O=>T_411, 
            I1=>ix373, 
            I0=>GATE_T_411_A );
  GATE_T_411_I_2:   INV port map ( O=>GATE_T_411_A, 
            I0=>j2c_reg_creg0hm_4_busQ );
  GATE_T_412_I_1:   AND4 port map ( O=>T_412, 
            I3=>ix373, 
            I2=>j2c_reg_creg0hm_2_busQ, 
            I1=>ix397, 
            I0=>GATE_T_412_A );
  GATE_T_412_I_2:   INV port map ( I0=>ix385, 
            O=>GATE_T_412_A );
  GATE_T_413_I_1:   NOR2 port map ( O=>T_413, 
            I1=>ix397, 
            I0=>j2c_reg_creg0hm_2_busQ );
  GATE_T_414_I_1:   AND2 port map ( O=>T_414, 
            I1=>ix385, 
            I0=>GATE_T_414_A );
  GATE_T_414_I_2:   INV port map ( O=>GATE_T_414_A, 
            I0=>j2c_reg_creg0hm_2_busQ );
  GATE_T_415_I_1:   NOR2 port map ( O=>T_415, 
            I1=>ix373, 
            I0=>j2c_reg_creg0hm_2_busQ );
  GATE_T_416_I_1:   NOR3 port map ( O=>T_416, 
            I2=>j2c_reg_creg0hm_2_busQ, 
            I1=>j2c_reg_creg0hm_6_busQ, 
            I0=>j2c_reg_creg0hm_0_busQ );
  GATE_T_417_I_1:   INV port map ( I0=>j2c_reg_creg0hm_0_busQ, 
            O=>GATE_T_417_A );
  GATE_T_417_I_2:   AND3 port map ( O=>T_417, 
            I2=>j2c_reg_creg0hm_2_busQ, 
            I1=>j2c_reg_creg0hm_6_busQ, 
            I0=>GATE_T_417_A );
  GATE_T_418_I_1:   INV port map ( I0=>j2c_reg_creg0hm_2_busQ, 
            O=>GATE_T_418_A );
  GATE_T_418_I_2:   AND3 port map ( O=>T_418, 
            I2=>j2c_reg_creg0hm_6_busQ, 
            I1=>j2c_reg_creg0hm_0_busQ, 
            I0=>GATE_T_418_A );
  GATE_T_419_I_1:   INV port map ( I0=>j2c_reg_creg0hm_6_busQ, 
            O=>GATE_T_419_A );
  GATE_T_419_I_2:   AND3 port map ( O=>T_419, 
            I2=>j2c_reg_creg0hm_2_busQ, 
            I1=>j2c_reg_creg0hm_0_busQ, 
            I0=>GATE_T_419_A );
  GATE_T_420_I_1:   NOR3 port map ( O=>T_420, 
            I2=>j2c_reg_creg0hm_5_busQ, 
            I1=>j2c_reg_creg0hm_6_busQ, 
            I0=>j2c_reg_creg0hm_3_busQ );
  GATE_T_421_I_1:   INV port map ( I0=>j2c_reg_creg0hm_3_busQ, 
            O=>GATE_T_421_A );
  GATE_T_421_I_2:   AND3 port map ( O=>T_421, 
            I2=>j2c_reg_creg0hm_5_busQ, 
            I1=>j2c_reg_creg0hm_6_busQ, 
            I0=>GATE_T_421_A );
  GATE_T_422_I_1:   INV port map ( I0=>j2c_reg_creg0hm_5_busQ, 
            O=>GATE_T_422_A );
  GATE_T_422_I_2:   AND3 port map ( O=>T_422, 
            I2=>j2c_reg_creg0hm_6_busQ, 
            I1=>j2c_reg_creg0hm_3_busQ, 
            I0=>GATE_T_422_A );
  GATE_T_423_I_1:   INV port map ( I0=>j2c_reg_creg0hm_6_busQ, 
            O=>GATE_T_423_A );
  GATE_T_423_I_2:   AND3 port map ( O=>T_423, 
            I2=>j2c_reg_creg0hm_5_busQ, 
            I1=>j2c_reg_creg0hm_3_busQ, 
            I0=>GATE_T_423_A );
  GATE_T_424_I_1:   NOR3 port map ( O=>T_424, 
            I2=>j2c_reg_creg0hm_2_busQ, 
            I1=>j2c_reg_creg0hm_5_busQ, 
            I0=>j2c_reg_creg0hm_1_busQ );
  GATE_T_425_I_1:   INV port map ( I0=>j2c_reg_creg0hm_1_busQ, 
            O=>GATE_T_425_A );
  GATE_T_425_I_2:   AND3 port map ( O=>T_425, 
            I2=>j2c_reg_creg0hm_2_busQ, 
            I1=>j2c_reg_creg0hm_5_busQ, 
            I0=>GATE_T_425_A );
  GATE_T_426_I_1:   INV port map ( I0=>j2c_reg_creg0hm_2_busQ, 
            O=>GATE_T_426_A );
  GATE_T_426_I_2:   AND3 port map ( O=>T_426, 
            I2=>j2c_reg_creg0hm_5_busQ, 
            I1=>j2c_reg_creg0hm_1_busQ, 
            I0=>GATE_T_426_A );
  GATE_T_427_I_1:   INV port map ( I0=>j2c_reg_creg0hm_5_busQ, 
            O=>GATE_T_427_A );
  GATE_T_427_I_2:   AND3 port map ( O=>T_427, 
            I2=>j2c_reg_creg0hm_2_busQ, 
            I1=>j2c_reg_creg0hm_1_busQ, 
            I0=>GATE_T_427_A );
  GATE_T_428_I_1:   INV port map ( I0=>ID_1_6_busQ, 
            O=>GATE_T_428_A );
  GATE_T_428_I_2:   AND3 port map ( O=>T_428, 
            I2=>T_727, 
            I1=>T_726, 
            I0=>GATE_T_428_A );
  GATE_T_429_I_1:   INV port map ( I0=>ID_1_5_busQ, 
            O=>GATE_T_429_A );
  GATE_T_429_I_2:   AND3 port map ( O=>T_429, 
            I2=>T_725, 
            I1=>T_724, 
            I0=>GATE_T_429_A );
  GATE_T_430_I_1:   INV port map ( I0=>ID_1_0_busQ, 
            O=>GATE_T_430_A );
  GATE_T_430_I_2:   AND3 port map ( O=>T_430, 
            I2=>T_723, 
            I1=>T_722, 
            I0=>GATE_T_430_A );
  GATE_T_431_I_1:   INV port map ( I0=>ID_1_1_busQ, 
            O=>GATE_T_431_A );
  GATE_T_431_I_2:   AND3 port map ( O=>T_431, 
            I2=>T_721, 
            I1=>T_720, 
            I0=>GATE_T_431_A );
  GATE_T_432_I_1:   INV port map ( I0=>ID_1_2_busQ, 
            O=>GATE_T_432_A );
  GATE_T_432_I_2:   AND3 port map ( O=>T_432, 
            I2=>T_719, 
            I1=>T_718, 
            I0=>GATE_T_432_A );
  GATE_T_433_I_1:   INV port map ( I0=>ID_1_3_busQ, 
            O=>GATE_T_433_A );
  GATE_T_433_I_2:   AND3 port map ( O=>T_433, 
            I2=>T_717, 
            I1=>T_716, 
            I0=>GATE_T_433_A );
  GATE_T_434_I_1:   INV port map ( I0=>ID_1_4_busQ, 
            O=>GATE_T_434_A );
  GATE_T_434_I_2:   AND3 port map ( O=>T_434, 
            I2=>T_715, 
            I1=>T_714, 
            I0=>GATE_T_434_A );
  GATE_T_435_I_1:   INV port map ( I0=>ID_0_7_busQ, 
            O=>GATE_T_435_A );
  GATE_T_435_I_2:   AND3 port map ( O=>T_435, 
            I2=>T_713, 
            I1=>T_712, 
            I0=>GATE_T_435_A );
  GATE_T_436_I_1:   INV port map ( I0=>ID_0_0_busQ, 
            O=>GATE_T_436_A );
  GATE_T_436_I_2:   AND3 port map ( O=>T_436, 
            I2=>T_711, 
            I1=>T_710, 
            I0=>GATE_T_436_A );
  GATE_T_437_I_1:   INV port map ( I0=>ID_0_1_busQ, 
            O=>GATE_T_437_A );
  GATE_T_437_I_2:   AND3 port map ( O=>T_437, 
            I2=>T_709, 
            I1=>T_708, 
            I0=>GATE_T_437_A );
  GATE_T_438_I_1:   INV port map ( I0=>ID_0_2_busQ, 
            O=>GATE_T_438_A );
  GATE_T_438_I_2:   AND3 port map ( O=>T_438, 
            I2=>T_707, 
            I1=>T_706, 
            I0=>GATE_T_438_A );
  GATE_T_439_I_1:   INV port map ( I0=>ID_0_3_busQ, 
            O=>GATE_T_439_A );
  GATE_T_439_I_2:   AND3 port map ( O=>T_439, 
            I2=>T_705, 
            I1=>T_704, 
            I0=>GATE_T_439_A );
  GATE_T_440_I_1:   INV port map ( I0=>ID_0_4_busQ, 
            O=>GATE_T_440_A );
  GATE_T_440_I_2:   AND3 port map ( O=>T_440, 
            I2=>T_703, 
            I1=>T_702, 
            I0=>GATE_T_440_A );
  GATE_T_441_I_1:   INV port map ( I0=>ID_0_5_busQ, 
            O=>GATE_T_441_A );
  GATE_T_441_I_2:   AND3 port map ( O=>T_441, 
            I2=>T_701, 
            I1=>T_700, 
            I0=>GATE_T_441_A );
  GATE_T_442_I_1:   INV port map ( I0=>ID_0_6_busQ, 
            O=>GATE_T_442_A );
  GATE_T_442_I_2:   AND3 port map ( O=>T_442, 
            I2=>T_699, 
            I1=>T_698, 
            I0=>GATE_T_442_A );
  GATE_T_443_I_1:   AND3 port map ( O=>T_443, 
            I2=>T_697, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>T_696 );
  GATE_T_444_I_1:   NOR4 port map ( I0=>ix1160, 
            I1=>ix1164, 
            O=>T_444, 
            I2=>ix1084, 
            I3=>GATE_T_444_DN );
  GATE_T_444_I_2:   INV port map ( I0=>ix1266, 
            O=>GATE_T_444_DN );
  GATE_T_445_I_1:   NOR4 port map ( I0=>ix1160, 
            I1=>ix1164, 
            O=>T_445, 
            I2=>ix1084, 
            I3=>GATE_T_445_DN );
  GATE_T_445_I_2:   INV port map ( I0=>ix1266, 
            O=>GATE_T_445_DN );
  GATE_T_446_I_1:   NOR4 port map ( I0=>ix1160, 
            I1=>ix1164, 
            O=>T_446, 
            I2=>ix1084, 
            I3=>GATE_T_446_DN );
  GATE_T_446_I_2:   INV port map ( I0=>ix1266, 
            O=>GATE_T_446_DN );
  GATE_T_447_I_1:   AND4 port map ( O=>T_447, 
            I3=>ix47, 
            I2=>j2c_reg_creg1hm_4_busQ, 
            I1=>ix71, 
            I0=>GATE_T_447_A );
  GATE_T_447_I_2:   INV port map ( I0=>ix59, 
            O=>GATE_T_447_A );
  GATE_T_448_I_1:   NOR2 port map ( O=>T_448, 
            I1=>ix71, 
            I0=>j2c_reg_creg1hm_4_busQ );
  GATE_T_449_I_1:   AND2 port map ( O=>T_449, 
            I1=>ix59, 
            I0=>GATE_T_449_A );
  GATE_T_449_I_2:   INV port map ( O=>GATE_T_449_A, 
            I0=>j2c_reg_creg1hm_4_busQ );
  GATE_T_450_I_1:   NOR2 port map ( O=>T_450, 
            I1=>ix47, 
            I0=>j2c_reg_creg1hm_4_busQ );
  GATE_T_451_I_1:   AND4 port map ( O=>T_451, 
            I3=>ix71, 
            I2=>ix59, 
            I1=>ix47, 
            I0=>j2c_reg_creg1hm_6_busQ );
  GATE_T_452_I_1:   NOR2 port map ( O=>T_452, 
            I1=>ix71, 
            I0=>j2c_reg_creg1hm_6_busQ );
  GATE_T_453_I_1:   NOR2 port map ( O=>T_453, 
            I1=>ix59, 
            I0=>j2c_reg_creg1hm_6_busQ );
  GATE_T_454_I_1:   NOR2 port map ( O=>T_454, 
            I1=>ix47, 
            I0=>j2c_reg_creg1hm_6_busQ );
  GATE_T_455_I_1:   AND4 port map ( O=>T_455, 
            I3=>ix47, 
            I2=>j2c_reg_creg1hm_5_busQ, 
            I1=>ix59, 
            I0=>GATE_T_455_A );
  GATE_T_455_I_2:   INV port map ( I0=>ix71, 
            O=>GATE_T_455_A );
  GATE_T_456_I_1:   AND2 port map ( O=>T_456, 
            I1=>ix71, 
            I0=>GATE_T_456_A );
  GATE_T_456_I_2:   INV port map ( O=>GATE_T_456_A, 
            I0=>j2c_reg_creg1hm_5_busQ );
  GATE_T_457_I_1:   NOR2 port map ( O=>T_457, 
            I1=>ix59, 
            I0=>j2c_reg_creg1hm_5_busQ );
  GATE_T_458_I_1:   NOR2 port map ( O=>T_458, 
            I1=>ix47, 
            I0=>j2c_reg_creg1hm_5_busQ );
  GATE_T_459_I_1:   AND4 port map ( O=>T_459, 
            I3=>ix71, 
            I2=>ix59, 
            I1=>j2c_reg_creg1hm_2_busQ, 
            I0=>GATE_T_459_A );
  GATE_T_459_I_2:   INV port map ( I0=>ix47, 
            O=>GATE_T_459_A );
  GATE_T_460_I_1:   NOR2 port map ( O=>T_460, 
            I1=>ix71, 
            I0=>j2c_reg_creg1hm_2_busQ );
  GATE_T_461_I_1:   NOR2 port map ( O=>T_461, 
            I1=>ix59, 
            I0=>j2c_reg_creg1hm_2_busQ );
  GATE_T_462_I_1:   AND2 port map ( O=>T_462, 
            I1=>ix47, 
            I0=>GATE_T_462_A );
  GATE_T_462_I_2:   INV port map ( O=>GATE_T_462_A, 
            I0=>j2c_reg_creg1hm_2_busQ );
  GATE_T_463_I_1:   NOR3 port map ( O=>T_463, 
            I2=>j2c_reg_creg1hm_4_busQ, 
            I1=>j2c_reg_creg1hm_6_busQ, 
            I0=>j2c_reg_creg1hm_0_busQ );
  GATE_T_464_I_1:   INV port map ( I0=>j2c_reg_creg1hm_0_busQ, 
            O=>GATE_T_464_A );
  GATE_T_464_I_2:   AND3 port map ( O=>T_464, 
            I2=>j2c_reg_creg1hm_4_busQ, 
            I1=>j2c_reg_creg1hm_6_busQ, 
            I0=>GATE_T_464_A );
  GATE_T_465_I_1:   INV port map ( I0=>j2c_reg_creg1hm_4_busQ, 
            O=>GATE_T_465_A );
  GATE_T_465_I_2:   AND3 port map ( O=>T_465, 
            I2=>j2c_reg_creg1hm_6_busQ, 
            I1=>j2c_reg_creg1hm_0_busQ, 
            I0=>GATE_T_465_A );
  GATE_T_466_I_1:   INV port map ( I0=>j2c_reg_creg1hm_6_busQ, 
            O=>GATE_T_466_A );
  GATE_T_466_I_2:   AND3 port map ( O=>T_466, 
            I2=>j2c_reg_creg1hm_4_busQ, 
            I1=>j2c_reg_creg1hm_0_busQ, 
            I0=>GATE_T_466_A );
  GATE_T_467_I_1:   NOR3 port map ( O=>T_467, 
            I2=>j2c_reg_creg1hm_5_busQ, 
            I1=>j2c_reg_creg1hm_6_busQ, 
            I0=>j2c_reg_creg1hm_1_busQ );
  GATE_T_468_I_1:   INV port map ( I0=>j2c_reg_creg1hm_1_busQ, 
            O=>GATE_T_468_A );
  GATE_T_468_I_2:   AND3 port map ( O=>T_468, 
            I2=>j2c_reg_creg1hm_5_busQ, 
            I1=>j2c_reg_creg1hm_6_busQ, 
            I0=>GATE_T_468_A );
  GATE_T_469_I_1:   INV port map ( I0=>j2c_reg_creg1hm_5_busQ, 
            O=>GATE_T_469_A );
  GATE_T_469_I_2:   AND3 port map ( O=>T_469, 
            I2=>j2c_reg_creg1hm_6_busQ, 
            I1=>j2c_reg_creg1hm_1_busQ, 
            I0=>GATE_T_469_A );
  GATE_T_470_I_1:   INV port map ( I0=>j2c_reg_creg1hm_6_busQ, 
            O=>GATE_T_470_A );
  GATE_T_470_I_2:   AND3 port map ( O=>T_470, 
            I2=>j2c_reg_creg1hm_5_busQ, 
            I1=>j2c_reg_creg1hm_1_busQ, 
            I0=>GATE_T_470_A );
  GATE_T_471_I_1:   NOR3 port map ( O=>T_471, 
            I2=>j2c_reg_creg1hm_4_busQ, 
            I1=>j2c_reg_creg1hm_5_busQ, 
            I0=>j2c_reg_creg1hm_3_busQ );
  GATE_T_472_I_1:   INV port map ( I0=>j2c_reg_creg1hm_3_busQ, 
            O=>GATE_T_472_A );
  GATE_T_472_I_2:   AND3 port map ( O=>T_472, 
            I2=>j2c_reg_creg1hm_4_busQ, 
            I1=>j2c_reg_creg1hm_5_busQ, 
            I0=>GATE_T_472_A );
  GATE_T_473_I_1:   INV port map ( I0=>j2c_reg_creg1hm_4_busQ, 
            O=>GATE_T_473_A );
  GATE_T_473_I_2:   AND3 port map ( O=>T_473, 
            I2=>j2c_reg_creg1hm_5_busQ, 
            I1=>j2c_reg_creg1hm_3_busQ, 
            I0=>GATE_T_473_A );
  GATE_T_474_I_1:   INV port map ( I0=>j2c_reg_creg1hm_5_busQ, 
            O=>GATE_T_474_A );
  GATE_T_474_I_2:   AND3 port map ( O=>T_474, 
            I2=>j2c_reg_creg1hm_4_busQ, 
            I1=>j2c_reg_creg1hm_3_busQ, 
            I0=>GATE_T_474_A );
  GATE_T_475_I_1:   OR2 port map ( O=>T_475, 
            I1=>T_18, 
            I0=>T_17 );
  GATE_T_476_I_1:   OR2 port map ( O=>T_476, 
            I1=>T_16, 
            I0=>T_15 );
  GATE_T_477_I_1:   OR2 port map ( O=>T_477, 
            I1=>T_25, 
            I0=>T_24 );
  GATE_T_478_I_1:   OR2 port map ( O=>T_478, 
            I1=>T_23, 
            I0=>T_22 );
  GATE_T_479_I_1:   OR2 port map ( O=>T_479, 
            I1=>T_21, 
            I0=>T_20 );
  GATE_T_480_I_1:   AND2 port map ( O=>T_480, 
            I1=>ix1160, 
            I0=>ix1084 );
  GATE_T_481_I_1:   NOR2 port map ( O=>T_481, 
            I1=>nx1595, 
            I0=>nx1271 );
  GATE_T_482_I_1:   AND2 port map ( O=>T_482, 
            I1=>ni_nires_reg_data_out_14_busQ, 
            I0=>GATE_T_482_A );
  GATE_T_482_I_2:   INV port map ( O=>GATE_T_482_A, 
            I0=>ni_nires_reg_data_out_13_busQ );
  GATE_T_483_I_1:   OR2 port map ( O=>T_483, 
            I1=>T_29, 
            I0=>T_28 );
  GATE_T_484_I_1:   OR2 port map ( O=>T_484, 
            I1=>T_27, 
            I0=>T_26 );
  GATE_T_485_I_1:   OR2 port map ( O=>T_485, 
            I1=>T_36, 
            I0=>T_35 );
  GATE_T_486_I_1:   OR2 port map ( O=>T_486, 
            I1=>T_34, 
            I0=>T_33 );
  GATE_T_487_I_1:   OR2 port map ( O=>T_487, 
            I1=>T_32, 
            I0=>T_31 );
  GATE_T_488_I_1:   AND2 port map ( O=>T_488, 
            I1=>ix1160, 
            I0=>ix1084 );
  GATE_T_489_I_1:   NOR2 port map ( O=>T_489, 
            I1=>nx1595, 
            I0=>nx1271 );
  GATE_T_490_I_1:   AND2 port map ( O=>T_490, 
            I1=>ni_nires_reg_data_out_4_busQ, 
            I0=>GATE_T_490_A );
  GATE_T_490_I_2:   INV port map ( O=>GATE_T_490_A, 
            I0=>ni_nires_reg_data_out_3_busQ );
  GATE_T_491_I_1:   AND2 port map ( O=>T_491, 
            I1=>ID_1_0_busQ, 
            I0=>ID_1_1_busQ );
  GATE_T_492_I_1:   AND2 port map ( O=>T_492, 
            I1=>ID_1_2_busQ, 
            I0=>ID_1_3_busQ );
  GATE_T_493_I_1:   AND2 port map ( O=>T_493, 
            I1=>nx1361, 
            I0=>ID_1_4_busQ );
  GATE_T_494_I_1:   AND2 port map ( O=>T_494, 
            I1=>ID_1_0_busQ, 
            I0=>ID_1_1_busQ );
  GATE_T_495_I_1:   AND2 port map ( O=>T_495, 
            I1=>ID_1_2_busQ, 
            I0=>ID_1_3_busQ );
  GATE_T_496_I_1:   AND2 port map ( O=>T_496, 
            I1=>nx1361, 
            I0=>ID_1_4_busQ );
  GATE_T_497_I_1:   AND2 port map ( O=>T_497, 
            I1=>ID_1_1_busQ, 
            I0=>ID_1_2_busQ );
  GATE_T_498_I_1:   AND2 port map ( O=>T_498, 
            I1=>nx1361, 
            I0=>ID_1_3_busQ );
  GATE_T_499_I_1:   AND2 port map ( O=>T_499, 
            I1=>ID_0_7_busQ, 
            I0=>ID_0_0_busQ );
  GATE_T_500_I_1:   AND2 port map ( O=>T_500, 
            I1=>ID_0_1_busQ, 
            I0=>ID_0_2_busQ );
  GATE_T_501_I_1:   AND2 port map ( O=>T_501, 
            I1=>ID_0_3_busQ, 
            I0=>ID_0_4_busQ );
  GATE_T_502_I_1:   AND2 port map ( O=>T_502, 
            I1=>ID_0_5_busQ, 
            I0=>ID_0_6_busQ );
  GATE_T_503_I_1:   AND2 port map ( O=>T_503, 
            I1=>ID_0_1_busQ, 
            I0=>ID_0_2_busQ );
  GATE_T_504_I_1:   AND2 port map ( O=>T_504, 
            I1=>ID_0_3_busQ, 
            I0=>ID_0_4_busQ );
  GATE_T_505_I_1:   AND2 port map ( O=>T_505, 
            I1=>ID_0_5_busQ, 
            I0=>ID_0_6_busQ );
  GATE_T_506_I_1:   AND2 port map ( O=>T_506, 
            I1=>ID_0_1_busQ, 
            I0=>ID_0_2_busQ );
  GATE_T_507_I_1:   AND2 port map ( O=>T_507, 
            I1=>ID_0_3_busQ, 
            I0=>ID_0_4_busQ );
  GATE_T_508_I_1:   AND2 port map ( O=>T_508, 
            I1=>ID_0_0_busQ, 
            I0=>ID_0_1_busQ );
  GATE_T_509_I_1:   AND2 port map ( O=>T_509, 
            I1=>ID_0_2_busQ, 
            I0=>ID_0_3_busQ );
  GATE_T_510_I_1:   AND2 port map ( O=>T_510, 
            I1=>ID_0_4_busQ, 
            I0=>ID_0_5_busQ );
  GATE_T_511_I_1:   AND2 port map ( O=>T_511, 
            I1=>ID_2_0_busQ, 
            I0=>ID_2_1_busQ );
  GATE_T_512_I_1:   AND2 port map ( O=>T_512, 
            I1=>ID_2_2_busQ, 
            I0=>ID_2_3_busQ );
  GATE_T_513_I_1:   AND2 port map ( O=>T_513, 
            I1=>ID_2_4_busQ, 
            I0=>ID_2_5_busQ );
  GATE_T_514_I_1:   OR4 port map ( I0=>T_126, 
            I1=>T_127, 
            O=>T_514, 
            I2=>T_128, 
            I3=>T_129 );
  GATE_T_515_I_1:   OR4 port map ( I0=>T_122, 
            I1=>T_123, 
            O=>T_515, 
            I2=>T_124, 
            I3=>T_125 );
  GATE_T_516_I_1:   OR4 port map ( I0=>T_118, 
            I1=>T_119, 
            O=>T_516, 
            I2=>T_120, 
            I3=>T_121 );
  GATE_T_517_I_1:   OR2 port map ( O=>T_517, 
            I1=>T_134, 
            I0=>T_133 );
  GATE_T_518_I_1:   OR2 port map ( O=>T_518, 
            I1=>T_132, 
            I0=>T_131 );
  GATE_T_519_I_1:   AND2 port map ( O=>T_519, 
            I1=>ix1578, 
            I0=>GATE_T_519_A );
  GATE_T_519_I_2:   INV port map ( O=>GATE_T_519_A, 
            I0=>ix1524 );
  GATE_T_520_I_1:   AND2 port map ( O=>T_520, 
            I1=>nx1519, 
            I0=>ni_nires_reg_data_out_12_busQ );
  GATE_T_521_I_1:   AND2 port map ( O=>T_521, 
            I1=>nx1595, 
            I0=>GATE_T_521_A );
  GATE_T_521_I_2:   INV port map ( O=>GATE_T_521_A, 
            I0=>ix1578 );
  GATE_T_522_I_1:   AND2 port map ( O=>T_522, 
            I1=>ix1524, 
            I0=>ni_nires_reg_data_out_13_busQ );
  GATE_T_523_I_1:   AND2 port map ( O=>T_523, 
            I1=>nx1595, 
            I0=>GATE_T_523_A );
  GATE_T_523_I_2:   INV port map ( O=>GATE_T_523_A, 
            I0=>ix1578 );
  GATE_T_524_I_1:   AND2 port map ( O=>T_524, 
            I1=>ix1524, 
            I0=>ni_nires_reg_data_out_12_busQ );
  GATE_T_525_I_1:   AND2 port map ( O=>T_525, 
            I1=>nx1595, 
            I0=>GATE_T_525_A );
  GATE_T_525_I_2:   INV port map ( O=>GATE_T_525_A, 
            I0=>ix1578 );
  GATE_T_526_I_1:   AND2 port map ( O=>T_526, 
            I1=>ni_nires_reg_data_out_13_busQ, 
            I0=>GATE_T_526_A );
  GATE_T_526_I_2:   INV port map ( O=>GATE_T_526_A, 
            I0=>ix1524 );
  GATE_T_527_I_1:   AND2 port map ( O=>T_527, 
            I1=>ix1578, 
            I0=>GATE_T_527_A );
  GATE_T_527_I_2:   INV port map ( O=>GATE_T_527_A, 
            I0=>ix1524 );
  GATE_T_528_I_1:   AND2 port map ( O=>T_528, 
            I1=>ni_nires_reg_data_out_11_busQ, 
            I0=>GATE_T_528_A );
  GATE_T_528_I_2:   INV port map ( O=>GATE_T_528_A, 
            I0=>nx1519 );
  GATE_T_529_I_1:   AND2 port map ( O=>T_529, 
            I1=>nx1595, 
            I0=>nx1519 );
  GATE_T_530_I_1:   AND2 port map ( O=>T_530, 
            I1=>ix1266, 
            I0=>ni_nires_reg_data_out_11_busQ );
  GATE_T_531_I_1:   AND2 port map ( O=>T_531, 
            I1=>nx1595, 
            I0=>GATE_T_531_A );
  GATE_T_531_I_2:   INV port map ( O=>GATE_T_531_A, 
            I0=>ix1578 );
  GATE_T_532_I_1:   AND2 port map ( O=>T_532, 
            I1=>ni_nires_reg_data_out_13_busQ, 
            I0=>GATE_T_532_A );
  GATE_T_532_I_2:   INV port map ( O=>GATE_T_532_A, 
            I0=>ix1524 );
  GATE_T_533_I_1:   AND2 port map ( O=>T_533, 
            I1=>ix1160, 
            I0=>ix1084 );
  GATE_T_534_I_1:   AND2 port map ( O=>T_534, 
            I1=>nx1595, 
            I0=>GATE_T_534_A );
  GATE_T_534_I_2:   INV port map ( O=>GATE_T_534_A, 
            I0=>ix1578 );
  GATE_T_535_I_1:   AND2 port map ( O=>T_535, 
            I1=>ni_nires_reg_data_out_14_busQ, 
            I0=>GATE_T_535_A );
  GATE_T_535_I_2:   INV port map ( O=>GATE_T_535_A, 
            I0=>ix1524 );
  GATE_T_536_I_1:   AND2 port map ( O=>T_536, 
            I1=>ID_2_1_busQ, 
            I0=>ID_2_2_busQ );
  GATE_T_537_I_1:   AND2 port map ( O=>T_537, 
            I1=>ID_2_3_busQ, 
            I0=>ID_2_4_busQ );
  GATE_T_538_I_1:   AND2 port map ( O=>T_538, 
            I1=>ID_2_6_busQ, 
            I0=>ID_2_5_busQ );
  GATE_T_539_I_1:   AND2 port map ( O=>T_539, 
            I1=>ID_2_1_busQ, 
            I0=>ID_2_2_busQ );
  GATE_T_540_I_1:   AND2 port map ( O=>T_540, 
            I1=>ID_2_3_busQ, 
            I0=>ID_2_4_busQ );
  GATE_T_541_I_1:   AND2 port map ( O=>T_541, 
            I1=>ID_3_0_busQ, 
            I0=>ID_3_1_busQ );
  GATE_T_542_I_1:   AND2 port map ( O=>T_542, 
            I1=>ID_3_2_busQ, 
            I0=>ID_3_3_busQ );
  GATE_T_543_I_1:   AND2 port map ( O=>T_543, 
            I1=>ID_3_4_busQ, 
            I0=>ID_3_5_busQ );
  GATE_T_544_I_1:   OR4 port map ( I0=>T_168, 
            I1=>T_169, 
            O=>T_544, 
            I2=>T_170, 
            I3=>T_171 );
  GATE_T_545_I_1:   OR4 port map ( I0=>T_164, 
            I1=>T_165, 
            O=>T_545, 
            I2=>T_166, 
            I3=>T_167 );
  GATE_T_546_I_1:   OR4 port map ( I0=>T_160, 
            I1=>T_161, 
            O=>T_546, 
            I2=>T_162, 
            I3=>T_163 );
  GATE_T_547_I_1:   OR2 port map ( O=>T_547, 
            I1=>T_176, 
            I0=>T_175 );
  GATE_T_548_I_1:   OR2 port map ( O=>T_548, 
            I1=>T_174, 
            I0=>T_173 );
  GATE_T_549_I_1:   AND2 port map ( O=>T_549, 
            I1=>ix1578, 
            I0=>GATE_T_549_A );
  GATE_T_549_I_2:   INV port map ( O=>GATE_T_549_A, 
            I0=>ix1524 );
  GATE_T_550_I_1:   AND2 port map ( O=>T_550, 
            I1=>ni_nires_reg_data_out_1_busQ, 
            I0=>GATE_T_550_A );
  GATE_T_550_I_2:   INV port map ( O=>GATE_T_550_A, 
            I0=>nx1519 );
  GATE_T_551_I_1:   AND2 port map ( O=>T_551, 
            I1=>nx1595, 
            I0=>nx1519 );
  GATE_T_552_I_1:   AND2 port map ( O=>T_552, 
            I1=>ix1266, 
            I0=>ni_nires_reg_data_out_1_busQ );
  GATE_T_553_I_1:   AND2 port map ( O=>T_553, 
            I1=>ix1578, 
            I0=>GATE_T_553_A );
  GATE_T_553_I_2:   INV port map ( O=>GATE_T_553_A, 
            I0=>ix1524 );
  GATE_T_554_I_1:   AND2 port map ( O=>T_554, 
            I1=>nx1519, 
            I0=>ni_nires_reg_data_out_2_busQ );
  GATE_T_555_I_1:   AND2 port map ( O=>T_555, 
            I1=>nx1595, 
            I0=>GATE_T_555_A );
  GATE_T_555_I_2:   INV port map ( O=>GATE_T_555_A, 
            I0=>ix1578 );
  GATE_T_556_I_1:   AND2 port map ( O=>T_556, 
            I1=>ix1524, 
            I0=>ni_nires_reg_data_out_2_busQ );
  GATE_T_557_I_1:   AND2 port map ( O=>T_557, 
            I1=>nx1595, 
            I0=>GATE_T_557_A );
  GATE_T_557_I_2:   INV port map ( O=>GATE_T_557_A, 
            I0=>ix1578 );
  GATE_T_558_I_1:   AND2 port map ( O=>T_558, 
            I1=>ix1524, 
            I0=>ni_nires_reg_data_out_3_busQ );
  GATE_T_559_I_1:   AND2 port map ( O=>T_559, 
            I1=>nx1595, 
            I0=>GATE_T_559_A );
  GATE_T_559_I_2:   INV port map ( O=>GATE_T_559_A, 
            I0=>ix1578 );
  GATE_T_560_I_1:   AND2 port map ( O=>T_560, 
            I1=>ni_nires_reg_data_out_3_busQ, 
            I0=>GATE_T_560_A );
  GATE_T_560_I_2:   INV port map ( O=>GATE_T_560_A, 
            I0=>ix1524 );
  GATE_T_561_I_1:   AND2 port map ( O=>T_561, 
            I1=>nx1595, 
            I0=>GATE_T_561_A );
  GATE_T_561_I_2:   INV port map ( O=>GATE_T_561_A, 
            I0=>ix1578 );
  GATE_T_562_I_1:   AND2 port map ( O=>T_562, 
            I1=>ni_nires_reg_data_out_3_busQ, 
            I0=>GATE_T_562_A );
  GATE_T_562_I_2:   INV port map ( O=>GATE_T_562_A, 
            I0=>ix1524 );
  GATE_T_563_I_1:   AND2 port map ( O=>T_563, 
            I1=>ix1160, 
            I0=>ix1084 );
  GATE_T_564_I_1:   AND2 port map ( O=>T_564, 
            I1=>nx1595, 
            I0=>GATE_T_564_A );
  GATE_T_564_I_2:   INV port map ( O=>GATE_T_564_A, 
            I0=>ix1578 );
  GATE_T_565_I_1:   AND2 port map ( O=>T_565, 
            I1=>ni_nires_reg_data_out_4_busQ, 
            I0=>GATE_T_565_A );
  GATE_T_565_I_2:   INV port map ( O=>GATE_T_565_A, 
            I0=>ix1524 );
  GATE_T_566_I_1:   AND2 port map ( O=>T_566, 
            I1=>ID_3_1_busQ, 
            I0=>ID_3_2_busQ );
  GATE_T_567_I_1:   AND2 port map ( O=>T_567, 
            I1=>ID_3_3_busQ, 
            I0=>ID_3_4_busQ );
  GATE_T_568_I_1:   AND2 port map ( O=>T_568, 
            I1=>ID_3_6_busQ, 
            I0=>ID_3_5_busQ );
  GATE_T_569_I_1:   AND2 port map ( O=>T_569, 
            I1=>ID_3_1_busQ, 
            I0=>ID_3_2_busQ );
  GATE_T_570_I_1:   AND2 port map ( O=>T_570, 
            I1=>ID_3_3_busQ, 
            I0=>ID_3_4_busQ );
  GATE_T_571_I_1:   OR2 port map ( O=>T_571, 
            I1=>T_243, 
            I0=>T_242 );
  GATE_T_572_I_1:   OR2 port map ( O=>T_572, 
            I1=>T_241, 
            I0=>T_240 );
  GATE_T_573_I_1:   OR2 port map ( O=>T_573, 
            I1=>T_250, 
            I0=>T_249 );
  GATE_T_574_I_1:   OR2 port map ( O=>T_574, 
            I1=>T_248, 
            I0=>T_247 );
  GATE_T_575_I_1:   OR2 port map ( O=>T_575, 
            I1=>T_246, 
            I0=>T_245 );
  GATE_T_576_I_1:   NOR2 port map ( O=>T_576, 
            I1=>ix1598, 
            I0=>ix1578 );
  GATE_T_577_I_1:   NOR2 port map ( O=>T_577, 
            I1=>ix1524, 
            I0=>nx1271 );
  GATE_T_578_I_1:   AND2 port map ( O=>T_578, 
            I1=>ix1160, 
            I0=>GATE_T_578_A );
  GATE_T_578_I_2:   INV port map ( O=>GATE_T_578_A, 
            I0=>ix1164 );
  GATE_T_579_I_1:   NOR2 port map ( O=>T_579, 
            I1=>ix1084, 
            I0=>ix1266 );
  GATE_T_580_I_1:   AND2 port map ( O=>T_580, 
            I1=>ni_nires_reg_data_out_7_busQ, 
            I0=>GATE_T_580_A );
  GATE_T_580_I_2:   INV port map ( O=>GATE_T_580_A, 
            I0=>ni_nires_reg_data_out_6_busQ );
  GATE_T_581_I_1:   AND2 port map ( O=>T_581, 
            I1=>ix1160, 
            I0=>GATE_T_581_A );
  GATE_T_581_I_2:   INV port map ( O=>GATE_T_581_A, 
            I0=>ix1164 );
  GATE_T_582_I_1:   NOR2 port map ( O=>T_582, 
            I1=>ix1084, 
            I0=>ix1266 );
  GATE_T_583_I_1:   AND2 port map ( O=>T_583, 
            I1=>ni_nires_reg_data_out_6_busQ, 
            I0=>GATE_T_583_A );
  GATE_T_583_I_2:   INV port map ( O=>GATE_T_583_A, 
            I0=>ni_nires_reg_data_out_7_busQ );
  GATE_T_584_I_1:   OR3 port map ( O=>T_584, 
            I2=>T_262, 
            I1=>T_261, 
            I0=>T_263 );
  GATE_T_585_I_1:   OR3 port map ( O=>T_585, 
            I2=>T_259, 
            I1=>T_258, 
            I0=>T_260 );
  GATE_T_586_I_1:   OR3 port map ( O=>T_586, 
            I2=>T_256, 
            I1=>T_255, 
            I0=>T_257 );
  GATE_T_587_I_1:   AND2 port map ( O=>T_587, 
            I1=>nx1595, 
            I0=>nx1519 );
  GATE_T_588_I_1:   AND2 port map ( O=>T_588, 
            I1=>ni_nires_reg_data_out_12_busQ, 
            I0=>GATE_T_588_A );
  GATE_T_588_I_2:   INV port map ( O=>GATE_T_588_A, 
            I0=>nx1271 );
  GATE_T_589_I_1:   AND2 port map ( O=>T_589, 
            I1=>nx1519, 
            I0=>GATE_T_589_A );
  GATE_T_589_I_2:   INV port map ( O=>GATE_T_589_A, 
            I0=>nx1271 );
  GATE_T_590_I_1:   AND2 port map ( O=>T_590, 
            I1=>ix1266, 
            I0=>ni_nires_reg_data_out_11_busQ );
  GATE_T_591_I_1:   AND2 port map ( O=>T_591, 
            I1=>nx1595, 
            I0=>GATE_T_591_A );
  GATE_T_591_I_2:   INV port map ( O=>GATE_T_591_A, 
            I0=>nx1519 );
  GATE_T_592_I_1:   AND2 port map ( O=>T_592, 
            I1=>ni_nires_reg_data_out_11_busQ, 
            I0=>GATE_T_592_A );
  GATE_T_592_I_2:   INV port map ( O=>GATE_T_592_A, 
            I0=>nx1271 );
  GATE_T_593_I_1:   AND2 port map ( O=>T_593, 
            I1=>nx1519, 
            I0=>GATE_T_593_A );
  GATE_T_593_I_2:   INV port map ( O=>GATE_T_593_A, 
            I0=>nx1271 );
  GATE_T_594_I_1:   AND2 port map ( O=>T_594, 
            I1=>ix1266, 
            I0=>ni_nires_reg_data_out_11_busQ );
  GATE_T_595_I_1:   OR2 port map ( O=>T_595, 
            I1=>T_271, 
            I0=>T_270 );
  GATE_T_596_I_1:   OR2 port map ( O=>T_596, 
            I1=>T_269, 
            I0=>T_268 );
  GATE_T_597_I_1:   OR2 port map ( O=>T_597, 
            I1=>T_267, 
            I0=>T_266 );
  GATE_T_598_I_1:   OR2 port map ( O=>T_598, 
            I1=>T_265, 
            I0=>T_264 );
  GATE_T_599_I_1:   AND2 port map ( O=>T_599, 
            I1=>nx1595, 
            I0=>ix1578 );
  GATE_T_600_I_1:   AND2 port map ( O=>T_600, 
            I1=>ni_nires_reg_data_out_13_busQ, 
            I0=>GATE_T_600_A );
  GATE_T_600_I_2:   INV port map ( O=>GATE_T_600_A, 
            I0=>nx1271 );
  GATE_T_601_I_1:   AND2 port map ( O=>T_601, 
            I1=>nx1595, 
            I0=>ix1578 );
  GATE_T_602_I_1:   AND2 port map ( O=>T_602, 
            I1=>ni_nires_reg_data_out_12_busQ, 
            I0=>GATE_T_602_A );
  GATE_T_602_I_2:   INV port map ( O=>GATE_T_602_A, 
            I0=>nx1271 );
  GATE_T_603_I_1:   OR4 port map ( I0=>T_280, 
            I1=>T_281, 
            O=>T_603, 
            I2=>T_282, 
            I3=>T_283 );
  GATE_T_604_I_1:   OR4 port map ( I0=>T_276, 
            I1=>T_277, 
            O=>T_604, 
            I2=>T_278, 
            I3=>T_279 );
  GATE_T_605_I_1:   OR4 port map ( I0=>T_272, 
            I1=>T_273, 
            O=>T_605, 
            I2=>T_274, 
            I3=>T_275 );
  GATE_T_606_I_1:   NOR2 port map ( O=>T_606, 
            I1=>ix1578, 
            I0=>ix1524 );
  GATE_T_607_I_1:   AND2 port map ( O=>T_607, 
            I1=>ni_nires_reg_data_out_13_busQ, 
            I0=>GATE_T_607_A );
  GATE_T_607_I_2:   INV port map ( O=>GATE_T_607_A, 
            I0=>nx1271 );
  GATE_T_608_I_1:   NOR2 port map ( O=>T_608, 
            I1=>ix1578, 
            I0=>ix1524 );
  GATE_T_609_I_1:   AND2 port map ( O=>T_609, 
            I1=>ni_nires_reg_data_out_12_busQ, 
            I0=>GATE_T_609_A );
  GATE_T_609_I_2:   INV port map ( O=>GATE_T_609_A, 
            I0=>nx1271 );
  GATE_T_610_I_1:   AND2 port map ( O=>T_610, 
            I1=>nx1595, 
            I0=>ix1524 );
  GATE_T_611_I_1:   AND2 port map ( O=>T_611, 
            I1=>ni_nires_reg_data_out_13_busQ, 
            I0=>GATE_T_611_A );
  GATE_T_611_I_2:   INV port map ( O=>GATE_T_611_A, 
            I0=>nx1271 );
  GATE_T_612_I_1:   AND2 port map ( O=>T_612, 
            I1=>nx1595, 
            I0=>ix1578 );
  GATE_T_613_I_1:   AND2 port map ( O=>T_613, 
            I1=>ni_nires_reg_data_out_13_busQ, 
            I0=>GATE_T_613_A );
  GATE_T_613_I_2:   INV port map ( O=>GATE_T_613_A, 
            I0=>nx1271 );
  GATE_T_614_I_1:   AND2 port map ( O=>T_614, 
            I1=>nx1595, 
            I0=>ix1524 );
  GATE_T_615_I_1:   AND2 port map ( O=>T_615, 
            I1=>ni_nires_reg_data_out_13_busQ, 
            I0=>GATE_T_615_A );
  GATE_T_615_I_2:   INV port map ( O=>GATE_T_615_A, 
            I0=>nx1271 );
  GATE_T_616_I_1:   AND2 port map ( O=>T_616, 
            I1=>nx1595, 
            I0=>ix1578 );
  GATE_T_617_I_1:   AND2 port map ( O=>T_617, 
            I1=>ni_nires_reg_data_out_13_busQ, 
            I0=>GATE_T_617_A );
  GATE_T_617_I_2:   INV port map ( O=>GATE_T_617_A, 
            I0=>nx1271 );
  GATE_T_618_I_1:   AND2 port map ( O=>T_618, 
            I1=>ix1160, 
            I0=>ix1084 );
  GATE_T_619_I_1:   AND2 port map ( O=>T_619, 
            I1=>nx1595, 
            I0=>ix1524 );
  GATE_T_620_I_1:   AND2 port map ( O=>T_620, 
            I1=>ni_nires_reg_data_out_14_busQ, 
            I0=>GATE_T_620_A );
  GATE_T_620_I_2:   INV port map ( O=>GATE_T_620_A, 
            I0=>nx1271 );
  GATE_T_621_I_1:   AND2 port map ( O=>T_621, 
            I1=>ix1160, 
            I0=>ix1084 );
  GATE_T_622_I_1:   AND2 port map ( O=>T_622, 
            I1=>nx1595, 
            I0=>ix1578 );
  GATE_T_623_I_1:   AND2 port map ( O=>T_623, 
            I1=>ni_nires_reg_data_out_14_busQ, 
            I0=>GATE_T_623_A );
  GATE_T_623_I_2:   INV port map ( O=>GATE_T_623_A, 
            I0=>nx1271 );
  GATE_T_624_I_1:   OR2 port map ( O=>T_624, 
            I1=>T_288, 
            I0=>T_287 );
  GATE_T_625_I_1:   OR2 port map ( O=>T_625, 
            I1=>T_286, 
            I0=>T_285 );
  GATE_T_626_I_1:   OR2 port map ( O=>T_626, 
            I1=>T_293, 
            I0=>T_292 );
  GATE_T_627_I_1:   OR2 port map ( O=>T_627, 
            I1=>T_291, 
            I0=>T_290 );
  GATE_T_628_I_1:   OR2 port map ( O=>T_628, 
            I1=>T_298, 
            I0=>T_297 );
  GATE_T_629_I_1:   OR2 port map ( O=>T_629, 
            I1=>T_296, 
            I0=>T_295 );
  GATE_T_630_I_1:   OR2 port map ( O=>T_630, 
            I1=>T_311, 
            I0=>T_310 );
  GATE_T_631_I_1:   OR2 port map ( O=>T_631, 
            I1=>T_309, 
            I0=>T_308 );
  GATE_T_632_I_1:   OR2 port map ( O=>T_632, 
            I1=>T_307, 
            I0=>T_306 );
  GATE_T_633_I_1:   NOR2 port map ( O=>T_633, 
            I1=>ix1598, 
            I0=>ix1578 );
  GATE_T_634_I_1:   NOR2 port map ( O=>T_634, 
            I1=>ix1524, 
            I0=>nx1271 );
  GATE_T_635_I_1:   AND2 port map ( O=>T_635, 
            I1=>ix1160, 
            I0=>GATE_T_635_A );
  GATE_T_635_I_2:   INV port map ( O=>GATE_T_635_A, 
            I0=>ix1164 );
  GATE_T_636_I_1:   NOR2 port map ( O=>T_636, 
            I1=>ix1084, 
            I0=>ix1266 );
  GATE_T_637_I_1:   AND2 port map ( O=>T_637, 
            I1=>ni_nires_reg_data_out_17_busQ, 
            I0=>GATE_T_637_A );
  GATE_T_637_I_2:   INV port map ( O=>GATE_T_637_A, 
            I0=>ni_nires_reg_data_out_16_busQ );
  GATE_T_638_I_1:   AND2 port map ( O=>T_638, 
            I1=>ix1160, 
            I0=>GATE_T_638_A );
  GATE_T_638_I_2:   INV port map ( O=>GATE_T_638_A, 
            I0=>ix1164 );
  GATE_T_639_I_1:   NOR2 port map ( O=>T_639, 
            I1=>ix1084, 
            I0=>ix1266 );
  GATE_T_640_I_1:   AND2 port map ( O=>T_640, 
            I1=>ni_nires_reg_data_out_16_busQ, 
            I0=>GATE_T_640_A );
  GATE_T_640_I_2:   INV port map ( O=>GATE_T_640_A, 
            I0=>ni_nires_reg_data_out_17_busQ );
  GATE_T_641_I_1:   AND2 port map ( O=>T_641, 
            I1=>nx1271, 
            I0=>GATE_T_641_A );
  GATE_T_641_I_2:   INV port map ( O=>GATE_T_641_A, 
            I0=>ni_pattcount_3_busQ );
  GATE_T_642_I_1:   NOR2 port map ( O=>T_642, 
            I1=>ni_pattcount_4_busQ, 
            I0=>ni_pattcount_0_busQ );
  GATE_T_643_I_1:   NOR2 port map ( O=>T_643, 
            I1=>ni_pattcount_1_busQ, 
            I0=>ni_pattcount_2_busQ );
  GATE_T_644_I_1:   OR3 port map ( O=>T_644, 
            I2=>T_327, 
            I1=>T_326, 
            I0=>T_328 );
  GATE_T_645_I_1:   OR3 port map ( O=>T_645, 
            I2=>T_324, 
            I1=>T_323, 
            I0=>T_325 );
  GATE_T_646_I_1:   OR3 port map ( O=>T_646, 
            I2=>T_321, 
            I1=>T_320, 
            I0=>T_322 );
  GATE_T_647_I_1:   AND2 port map ( O=>T_647, 
            I1=>nx1519, 
            I0=>GATE_T_647_A );
  GATE_T_647_I_2:   INV port map ( O=>GATE_T_647_A, 
            I0=>nx1271 );
  GATE_T_648_I_1:   AND2 port map ( O=>T_648, 
            I1=>ix1266, 
            I0=>ni_nires_reg_data_out_1_busQ );
  GATE_T_649_I_1:   AND2 port map ( O=>T_649, 
            I1=>nx1595, 
            I0=>GATE_T_649_A );
  GATE_T_649_I_2:   INV port map ( O=>GATE_T_649_A, 
            I0=>nx1519 );
  GATE_T_650_I_1:   AND2 port map ( O=>T_650, 
            I1=>ni_nires_reg_data_out_1_busQ, 
            I0=>GATE_T_650_A );
  GATE_T_650_I_2:   INV port map ( O=>GATE_T_650_A, 
            I0=>nx1271 );
  GATE_T_651_I_1:   AND2 port map ( O=>T_651, 
            I1=>nx1519, 
            I0=>GATE_T_651_A );
  GATE_T_651_I_2:   INV port map ( O=>GATE_T_651_A, 
            I0=>nx1271 );
  GATE_T_652_I_1:   AND2 port map ( O=>T_652, 
            I1=>ix1266, 
            I0=>ni_nires_reg_data_out_1_busQ );
  GATE_T_653_I_1:   AND2 port map ( O=>T_653, 
            I1=>nx1595, 
            I0=>nx1519 );
  GATE_T_654_I_1:   AND2 port map ( O=>T_654, 
            I1=>ni_nires_reg_data_out_2_busQ, 
            I0=>GATE_T_654_A );
  GATE_T_654_I_2:   INV port map ( O=>GATE_T_654_A, 
            I0=>nx1271 );
  GATE_T_655_I_1:   OR2 port map ( O=>T_655, 
            I1=>T_336, 
            I0=>T_335 );
  GATE_T_656_I_1:   OR2 port map ( O=>T_656, 
            I1=>T_334, 
            I0=>T_333 );
  GATE_T_657_I_1:   OR2 port map ( O=>T_657, 
            I1=>T_332, 
            I0=>T_331 );
  GATE_T_658_I_1:   OR2 port map ( O=>T_658, 
            I1=>T_330, 
            I0=>T_329 );
  GATE_T_659_I_1:   AND2 port map ( O=>T_659, 
            I1=>nx1595, 
            I0=>ix1578 );
  GATE_T_660_I_1:   AND2 port map ( O=>T_660, 
            I1=>ni_nires_reg_data_out_2_busQ, 
            I0=>GATE_T_660_A );
  GATE_T_660_I_2:   INV port map ( O=>GATE_T_660_A, 
            I0=>nx1271 );
  GATE_T_661_I_1:   AND2 port map ( O=>T_661, 
            I1=>nx1595, 
            I0=>ix1578 );
  GATE_T_662_I_1:   AND2 port map ( O=>T_662, 
            I1=>ni_nires_reg_data_out_3_busQ, 
            I0=>GATE_T_662_A );
  GATE_T_662_I_2:   INV port map ( O=>GATE_T_662_A, 
            I0=>nx1271 );
  GATE_T_663_I_1:   OR4 port map ( I0=>T_345, 
            I1=>T_346, 
            O=>T_663, 
            I2=>T_347, 
            I3=>T_348 );
  GATE_T_664_I_1:   OR4 port map ( I0=>T_341, 
            I1=>T_342, 
            O=>T_664, 
            I2=>T_343, 
            I3=>T_344 );
  GATE_T_665_I_1:   OR4 port map ( I0=>T_337, 
            I1=>T_338, 
            O=>T_665, 
            I2=>T_339, 
            I3=>T_340 );
  GATE_T_666_I_1:   NOR2 port map ( O=>T_666, 
            I1=>ix1578, 
            I0=>ix1524 );
  GATE_T_667_I_1:   AND2 port map ( O=>T_667, 
            I1=>ni_nires_reg_data_out_2_busQ, 
            I0=>GATE_T_667_A );
  GATE_T_667_I_2:   INV port map ( O=>GATE_T_667_A, 
            I0=>nx1271 );
  GATE_T_668_I_1:   NOR2 port map ( O=>T_668, 
            I1=>ix1578, 
            I0=>ix1524 );
  GATE_T_669_I_1:   AND2 port map ( O=>T_669, 
            I1=>ni_nires_reg_data_out_3_busQ, 
            I0=>GATE_T_669_A );
  GATE_T_669_I_2:   INV port map ( O=>GATE_T_669_A, 
            I0=>nx1271 );
  GATE_T_670_I_1:   AND2 port map ( O=>T_670, 
            I1=>nx1595, 
            I0=>ix1524 );
  GATE_T_671_I_1:   AND2 port map ( O=>T_671, 
            I1=>ni_nires_reg_data_out_3_busQ, 
            I0=>GATE_T_671_A );
  GATE_T_671_I_2:   INV port map ( O=>GATE_T_671_A, 
            I0=>nx1271 );
  GATE_T_672_I_1:   AND2 port map ( O=>T_672, 
            I1=>nx1595, 
            I0=>ix1578 );
  GATE_T_673_I_1:   AND2 port map ( O=>T_673, 
            I1=>ni_nires_reg_data_out_3_busQ, 
            I0=>GATE_T_673_A );
  GATE_T_673_I_2:   INV port map ( O=>GATE_T_673_A, 
            I0=>nx1271 );
  GATE_T_674_I_1:   AND2 port map ( O=>T_674, 
            I1=>nx1595, 
            I0=>ix1524 );
  GATE_T_675_I_1:   AND2 port map ( O=>T_675, 
            I1=>ni_nires_reg_data_out_3_busQ, 
            I0=>GATE_T_675_A );
  GATE_T_675_I_2:   INV port map ( O=>GATE_T_675_A, 
            I0=>nx1271 );
  GATE_T_676_I_1:   AND2 port map ( O=>T_676, 
            I1=>nx1595, 
            I0=>ix1578 );
  GATE_T_677_I_1:   AND2 port map ( O=>T_677, 
            I1=>ni_nires_reg_data_out_3_busQ, 
            I0=>GATE_T_677_A );
  GATE_T_677_I_2:   INV port map ( O=>GATE_T_677_A, 
            I0=>nx1271 );
  GATE_T_678_I_1:   AND2 port map ( O=>T_678, 
            I1=>ix1160, 
            I0=>ix1084 );
  GATE_T_679_I_1:   AND2 port map ( O=>T_679, 
            I1=>nx1595, 
            I0=>ix1524 );
  GATE_T_680_I_1:   AND2 port map ( O=>T_680, 
            I1=>ni_nires_reg_data_out_4_busQ, 
            I0=>GATE_T_680_A );
  GATE_T_680_I_2:   INV port map ( O=>GATE_T_680_A, 
            I0=>nx1271 );
  GATE_T_681_I_1:   AND2 port map ( O=>T_681, 
            I1=>ix1160, 
            I0=>ix1084 );
  GATE_T_682_I_1:   AND2 port map ( O=>T_682, 
            I1=>nx1595, 
            I0=>ix1578 );
  GATE_T_683_I_1:   AND2 port map ( O=>T_683, 
            I1=>ni_nires_reg_data_out_4_busQ, 
            I0=>GATE_T_683_A );
  GATE_T_683_I_2:   INV port map ( O=>GATE_T_683_A, 
            I0=>nx1271 );
  GATE_T_684_I_1:   OR2 port map ( O=>T_684, 
            I1=>T_357, 
            I0=>T_356 );
  GATE_T_685_I_1:   OR2 port map ( O=>T_685, 
            I1=>T_355, 
            I0=>T_354 );
  GATE_T_686_I_1:   OR2 port map ( O=>T_686, 
            I1=>T_366, 
            I0=>T_365 );
  GATE_T_687_I_1:   OR2 port map ( O=>T_687, 
            I1=>T_364, 
            I0=>T_363 );
  GATE_T_688_I_1:   OR4 port map ( I0=>T_381, 
            I1=>T_382, 
            O=>T_688, 
            I2=>T_383, 
            I3=>T_384 );
  GATE_T_689_I_1:   OR4 port map ( I0=>T_377, 
            I1=>T_378, 
            O=>T_689, 
            I2=>T_379, 
            I3=>T_380 );
  GATE_T_690_I_1:   OR4 port map ( I0=>T_373, 
            I1=>T_374, 
            O=>T_690, 
            I2=>T_375, 
            I3=>T_376 );
  GATE_T_691_I_1:   OR4 port map ( I0=>T_369, 
            I1=>T_370, 
            O=>T_691, 
            I2=>T_371, 
            I3=>T_372 );
  GATE_T_692_I_1:   OR4 port map ( I0=>T_440, 
            I1=>T_441, 
            O=>T_692, 
            I2=>T_442, 
            I3=>T_443 );
  GATE_T_693_I_1:   OR4 port map ( I0=>T_436, 
            I1=>T_437, 
            O=>T_693, 
            I2=>T_438, 
            I3=>T_439 );
  GATE_T_694_I_1:   OR4 port map ( I0=>T_432, 
            I1=>T_433, 
            O=>T_694, 
            I2=>T_434, 
            I3=>T_435 );
  GATE_T_695_I_1:   OR4 port map ( I0=>T_428, 
            I1=>T_429, 
            O=>T_695, 
            I2=>T_430, 
            I3=>T_431 );
  GATE_T_696_I_1:   AND2 port map ( O=>T_696, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_697_I_1:   AND2 port map ( O=>T_697, 
            I1=>j2c_reg_cmdreg_0_busQ, 
            I0=>GATE_T_697_A );
  GATE_T_697_I_2:   INV port map ( O=>GATE_T_697_A, 
            I0=>FAULTPIN );
  GATE_T_698_I_1:   AND2 port map ( O=>T_698, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>GATE_T_698_A );
  GATE_T_698_I_2:   INV port map ( O=>GATE_T_698_A, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_699_I_1:   AND2 port map ( O=>T_699, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_699_A );
  GATE_T_699_I_2:   INV port map ( O=>GATE_T_699_A, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_700_I_1:   AND2 port map ( O=>T_700, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>GATE_T_700_A );
  GATE_T_700_I_2:   INV port map ( O=>GATE_T_700_A, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_701_I_1:   AND2 port map ( O=>T_701, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_701_A );
  GATE_T_701_I_2:   INV port map ( O=>GATE_T_701_A, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_702_I_1:   NOR2 port map ( O=>T_702, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_703_I_1:   AND2 port map ( O=>T_703, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_703_A );
  GATE_T_703_I_2:   INV port map ( O=>GATE_T_703_A, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_704_I_1:   AND2 port map ( O=>T_704, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_705_I_1:   NOR2 port map ( O=>T_705, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_706_I_1:   AND2 port map ( O=>T_706, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>GATE_T_706_A );
  GATE_T_706_I_2:   INV port map ( O=>GATE_T_706_A, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_707_I_1:   NOR2 port map ( O=>T_707, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_708_I_1:   AND2 port map ( O=>T_708, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>GATE_T_708_A );
  GATE_T_708_I_2:   INV port map ( O=>GATE_T_708_A, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_709_I_1:   NOR2 port map ( O=>T_709, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_710_I_1:   NOR2 port map ( O=>T_710, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_711_I_1:   NOR2 port map ( O=>T_711, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_712_I_1:   AND2 port map ( O=>T_712, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_713_I_1:   AND2 port map ( O=>T_713, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_713_A );
  GATE_T_713_I_2:   INV port map ( O=>GATE_T_713_A, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_714_I_1:   NOR2 port map ( O=>T_714, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_715_I_1:   AND2 port map ( O=>T_715, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_716_I_1:   AND2 port map ( O=>T_716, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_717_I_1:   AND2 port map ( O=>T_717, 
            I1=>j2c_reg_cmdreg_0_busQ, 
            I0=>GATE_T_717_A );
  GATE_T_717_I_2:   INV port map ( O=>GATE_T_717_A, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_718_I_1:   AND2 port map ( O=>T_718, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>GATE_T_718_A );
  GATE_T_718_I_2:   INV port map ( O=>GATE_T_718_A, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_719_I_1:   AND2 port map ( O=>T_719, 
            I1=>j2c_reg_cmdreg_0_busQ, 
            I0=>GATE_T_719_A );
  GATE_T_719_I_2:   INV port map ( O=>GATE_T_719_A, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_720_I_1:   AND2 port map ( O=>T_720, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>GATE_T_720_A );
  GATE_T_720_I_2:   INV port map ( O=>GATE_T_720_A, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_721_I_1:   AND2 port map ( O=>T_721, 
            I1=>j2c_reg_cmdreg_0_busQ, 
            I0=>GATE_T_721_A );
  GATE_T_721_I_2:   INV port map ( O=>GATE_T_721_A, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_722_I_1:   NOR2 port map ( O=>T_722, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_723_I_1:   AND2 port map ( O=>T_723, 
            I1=>j2c_reg_cmdreg_0_busQ, 
            I0=>GATE_T_723_A );
  GATE_T_723_I_2:   INV port map ( O=>GATE_T_723_A, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_724_I_1:   AND2 port map ( O=>T_724, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>GATE_T_724_A );
  GATE_T_724_I_2:   INV port map ( O=>GATE_T_724_A, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_725_I_1:   AND2 port map ( O=>T_725, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_726_I_1:   AND2 port map ( O=>T_726, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>GATE_T_726_A );
  GATE_T_726_I_2:   INV port map ( O=>GATE_T_726_A, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_727_I_1:   AND2 port map ( O=>T_727, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_728_I_1:   OR3 port map ( O=>T_728, 
            I2=>T_398, 
            I1=>T_397, 
            I0=>T_399 );
  GATE_T_729_I_1:   OR4 port map ( I0=>T_393, 
            I1=>T_394, 
            O=>T_729, 
            I2=>T_395, 
            I3=>T_396 );
  GATE_T_730_I_1:   OR4 port map ( I0=>T_389, 
            I1=>T_390, 
            O=>T_730, 
            I2=>T_391, 
            I3=>T_392 );
  GATE_T_731_I_1:   OR4 port map ( I0=>T_385, 
            I1=>T_386, 
            O=>T_731, 
            I2=>T_387, 
            I3=>T_388 );
  GATE_T_732_I_1:   AND2 port map ( O=>T_732, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>GATE_T_732_A );
  GATE_T_732_I_2:   INV port map ( O=>GATE_T_732_A, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_733_I_1:   AND2 port map ( O=>T_733, 
            I1=>ID_3_3_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_734_I_1:   AND2 port map ( O=>T_734, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_734_A );
  GATE_T_734_I_2:   INV port map ( O=>GATE_T_734_A, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_735_I_1:   AND2 port map ( O=>T_735, 
            I1=>ID_3_5_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_736_I_1:   NOR2 port map ( O=>T_736, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_737_I_1:   AND2 port map ( O=>T_737, 
            I1=>ID_3_1_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_738_I_1:   AND2 port map ( O=>T_738, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_739_I_1:   AND2 port map ( O=>T_739, 
            I1=>ID_3_6_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_740_I_1:   AND2 port map ( O=>T_740, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>GATE_T_740_A );
  GATE_T_740_I_2:   INV port map ( O=>GATE_T_740_A, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_741_I_1:   AND2 port map ( O=>T_741, 
            I1=>ID_3_2_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_742_I_1:   AND2 port map ( O=>T_742, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_742_A );
  GATE_T_742_I_2:   INV port map ( O=>GATE_T_742_A, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_743_I_1:   AND2 port map ( O=>T_743, 
            I1=>ID_3_4_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_744_I_1:   NOR2 port map ( O=>T_744, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_745_I_1:   AND2 port map ( O=>T_745, 
            I1=>ID_3_0_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_746_I_1:   AND2 port map ( O=>T_746, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>GATE_T_746_A );
  GATE_T_746_I_2:   INV port map ( O=>GATE_T_746_A, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_747_I_1:   AND2 port map ( O=>T_747, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_747_A );
  GATE_T_747_I_2:   INV port map ( O=>GATE_T_747_A, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_748_I_1:   AND2 port map ( O=>T_748, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>GATE_T_748_A );
  GATE_T_748_I_2:   INV port map ( O=>GATE_T_748_A, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_749_I_1:   AND2 port map ( O=>T_749, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_749_A );
  GATE_T_749_I_2:   INV port map ( O=>GATE_T_749_A, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_750_I_1:   NOR2 port map ( O=>T_750, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_751_I_1:   AND2 port map ( O=>T_751, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_751_A );
  GATE_T_751_I_2:   INV port map ( O=>GATE_T_751_A, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_752_I_1:   AND2 port map ( O=>T_752, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_753_I_1:   NOR2 port map ( O=>T_753, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_754_I_1:   AND2 port map ( O=>T_754, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>GATE_T_754_A );
  GATE_T_754_I_2:   INV port map ( O=>GATE_T_754_A, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_755_I_1:   NOR2 port map ( O=>T_755, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_756_I_1:   AND2 port map ( O=>T_756, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>GATE_T_756_A );
  GATE_T_756_I_2:   INV port map ( O=>GATE_T_756_A, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_757_I_1:   NOR2 port map ( O=>T_757, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_758_I_1:   NOR2 port map ( O=>T_758, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_759_I_1:   NOR2 port map ( O=>T_759, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>j2c_reg_cmdreg_0_busQ );
  GATE_T_760_I_1:   AND2 port map ( O=>T_760, 
            I1=>j2c_reg_cmdreg_1_busQ, 
            I0=>GATE_T_760_A );
  GATE_T_760_I_2:   INV port map ( O=>GATE_T_760_A, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_761_I_1:   AND2 port map ( O=>T_761, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            I0=>GATE_T_761_A );
  GATE_T_761_I_2:   INV port map ( O=>GATE_T_761_A, 
            I0=>DIS_JTGPIN );
  GATE_T_762_I_1:   AND2 port map ( O=>T_762, 
            I1=>ix1610, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_763_I_1:   AND2 port map ( O=>T_763, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>GATE_T_763_A );
  GATE_T_763_I_2:   INV port map ( O=>GATE_T_763_A, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_764_I_1:   AND2 port map ( O=>T_764, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            I0=>GATE_T_764_A );
  GATE_T_764_I_2:   INV port map ( O=>GATE_T_764_A, 
            I0=>DIS_JTGPIN );
  GATE_T_765_I_1:   AND2 port map ( O=>T_765, 
            I1=>ix1578, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_766_I_1:   NOR2 port map ( O=>T_766, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_767_I_1:   AND2 port map ( O=>T_767, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            I0=>GATE_T_767_A );
  GATE_T_767_I_2:   INV port map ( O=>GATE_T_767_A, 
            I0=>DIS_JTGPIN );
  GATE_T_768_I_1:   AND2 port map ( O=>T_768, 
            I1=>ix1598, 
            I0=>GATE_T_768_A );
  GATE_T_768_I_2:   INV port map ( O=>GATE_T_768_A, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_769_I_1:   AND2 port map ( O=>T_769, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>GATE_T_769_A );
  GATE_T_769_I_2:   INV port map ( O=>GATE_T_769_A, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_770_I_1:   AND2 port map ( O=>T_770, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            I0=>GATE_T_770_A );
  GATE_T_770_I_2:   INV port map ( O=>GATE_T_770_A, 
            I0=>DIS_JTGPIN );
  GATE_T_771_I_1:   AND2 port map ( O=>T_771, 
            I1=>ix1524, 
            I0=>GATE_T_771_A );
  GATE_T_771_I_2:   INV port map ( O=>GATE_T_771_A, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_772_I_1:   NOR2 port map ( O=>T_772, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>j2c_bitcnt_2_busQ );
  GATE_T_773_I_1:   AND2 port map ( O=>T_773, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            I0=>GATE_T_773_A );
  GATE_T_773_I_2:   INV port map ( O=>GATE_T_773_A, 
            I0=>DIS_JTGPIN );
  GATE_T_774_I_1:   AND2 port map ( O=>T_774, 
            I1=>ix1164, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_775_I_1:   AND2 port map ( O=>T_775, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_775_A );
  GATE_T_775_I_2:   INV port map ( O=>GATE_T_775_A, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_776_I_1:   AND2 port map ( O=>T_776, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            I0=>GATE_T_776_A );
  GATE_T_776_I_2:   INV port map ( O=>GATE_T_776_A, 
            I0=>DIS_JTGPIN );
  GATE_T_777_I_1:   NOR2 port map ( O=>T_777, 
            I1=>ix59, 
            I0=>ix47 );
  GATE_T_778_I_1:   AND2 port map ( O=>T_778, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_reg_cmdreg_1_busQ );
  GATE_T_779_I_1:   AND2 port map ( O=>T_779, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            I0=>GATE_T_779_A );
  GATE_T_779_I_2:   INV port map ( O=>GATE_T_779_A, 
            I0=>DIS_JTGPIN );
  GATE_T_780_I_1:   NOR2 port map ( O=>T_780, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_781_I_1:   AND2 port map ( O=>T_781, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_781_A );
  GATE_T_781_I_2:   INV port map ( O=>GATE_T_781_A, 
            I0=>j2c_reg_cmdreg_1_busQ );
  GATE_T_782_I_1:   AND2 port map ( O=>T_782, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            I0=>GATE_T_782_A );
  GATE_T_782_I_2:   INV port map ( O=>GATE_T_782_A, 
            I0=>DIS_JTGPIN );
  GATE_T_783_I_1:   AND2 port map ( O=>T_783, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>GATE_T_783_A );
  GATE_T_783_I_2:   INV port map ( O=>GATE_T_783_A, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_784_I_1:   AND2 port map ( O=>T_784, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_784_A );
  GATE_T_784_I_2:   INV port map ( O=>GATE_T_784_A, 
            I0=>j2c_reg_cmdreg_1_busQ );
  GATE_T_785_I_1:   AND2 port map ( O=>T_785, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            I0=>GATE_T_785_A );
  GATE_T_785_I_2:   INV port map ( O=>GATE_T_785_A, 
            I0=>DIS_JTGPIN );
  GATE_T_786_I_1:   AND2 port map ( O=>T_786, 
            I1=>j2c_bitcnt_0_busQ, 
            I0=>j2c_bitcnt_1_busQ );
  GATE_T_787_I_1:   AND2 port map ( O=>T_787, 
            I1=>j2c_bitcnt_2_busQ, 
            I0=>GATE_T_787_A );
  GATE_T_787_I_2:   INV port map ( O=>GATE_T_787_A, 
            I0=>j2c_reg_cmdreg_1_busQ );
  GATE_T_788_I_1:   AND2 port map ( O=>T_788, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            I0=>GATE_T_788_A );
  GATE_T_788_I_2:   INV port map ( O=>GATE_T_788_A, 
            I0=>DIS_JTGPIN );
  GATE_T_789_I_1:   NOR2 port map ( O=>T_789, 
            I1=>ix397, 
            I0=>ix385 );
  GATE_T_790_I_1:   NOR2 port map ( O=>T_790, 
            I1=>ix373, 
            I0=>j2c_bitcnt_0_busQ );
  GATE_T_791_I_1:   AND2 port map ( O=>T_791, 
            I1=>j2c_bitcnt_1_busQ, 
            I0=>j2c_reg_cmdreg_1_busQ );
  GATE_T_792_I_1:   AND2 port map ( O=>T_792, 
            I1=>j2c_reg_cmdreg_2_busQ, 
            I0=>GATE_T_792_A );
  GATE_T_792_I_2:   INV port map ( O=>GATE_T_792_A, 
            I0=>DIS_JTGPIN );

end NetList;