|--------------------------------------------------- ----------| |- ispLEVER 6.1.00.38.44.06 Equations File -| |- Copyright(C), 1992-2001, Lattice Semiconductor Corporation -| |- All Rights Reserved. -| |--------------------------------------------------------------| Equations: EN = ENABLE ; (1 pterm, 1 signal) ENABLE = !( j2c__ix77 & j2c__ix99 & j2c__ix85 & !j2c__ix107 ) ; (1 pterm, 4 signals) LCKREFN = 0 ; (0 pterm, 0 signal) LOOPEN = 0 ; (0 pterm, 0 signal) PRBSEN = j2c__ix77 & !j2c__ix99 & j2c__ix85 & !j2c__ix107 ; (1 pterm, 4 signals) SCL = 0 ; (0 pterm, 0 signal) SCL.OE = nx12 ; (1 pterm, 1 signal) SD2ANL = ENABLE ; (1 pterm, 1 signal) SDA = 0 ; (0 pterm, 0 signal) SDA.OE = nx20 ; (1 pterm, 1 signal) TESTEN = 0 ; (0 pterm, 0 signal) TXD_0_.D = !( !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & nx972 & nx988 & !testpatt & !j2c__ix107 # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & nx988 & !testpatt & !j2c__reg_creg0hm_0_.Q # TXD_0_.Q & nx988 & testpatt # nx972 & nx988 & !testpatt & !ni_nires__reg_data_out_0_.Q # !ENABLE & nx988 ) ; (5 pterms, 14 signals) TXD_0_.C = clk ; (1 pterm, 1 signal) TXD_0_.CE = nx148 ; (1 pterm, 1 signal) TXD_0_.AR = !reset_n ; (1 pterm, 1 signal) TXD_10_.D = ENABLE & !j2c__ix77 & !j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_14_.Q # ENABLE & !j2c__ix77 & !j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_14_.Q # ENABLE & j2c__reg_creg0hm_1_.Q & !testpatt & nx1039 & j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1039 & j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_12_.Q # ENABLE & !TXD_10_.Q & !TXD_9_.Q & !TXD_8_.Q & testpatt # ENABLE & j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_13_.Q # ENABLE & TXD_10_.Q & TXD_8_.Q & testpatt # ENABLE & TXD_10_.Q & TXD_9_.Q & testpatt # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & nx1039 & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & nx1039 & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & !nx1039 & ni_nires__reg_data_out_12_.Q # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1039 & ni_nires__reg_data_out_12_.Q ; (15 pterms, 15 signals) TXD_10_.C = clk ; (1 pterm, 1 signal) TXD_10_.CE = nx148 ; (1 pterm, 1 signal) TXD_10_.AP = !reset_n ; (1 pterm, 1 signal) TXD_11_.D.X1 = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !nx1309 # ENABLE & !j2c__ix77 & !j2c__ix99 & j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_14_.Q # ENABLE & !j2c__ix77 & !j2c__ix99 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_14_.Q # ENABLE & j2c__ix99 & j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__ix99 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__ix77 & j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_13_.Q # ENABLE & j2c__ix77 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_13_.Q # ENABLE & !TXD_10_.Q & !TXD_9_.Q & !TXD_8_.Q & testpatt ; (8 pterms, 12 signals) TXD_11_.D.X2 = ENABLE & TXD_11_.Q & testpatt ; (1 pterm, 3 signals) TXD_11_.C = clk ; (1 pterm, 1 signal) TXD_11_.CE = nx148 ; (1 pterm, 1 signal) TXD_11_.AP = !reset_n ; (1 pterm, 1 signal) TXD_12_.D = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & !nx1333 # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & j2c__reg_creg0hm_0_.Q & !nx1309 # ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1309 # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !nx1333 # ENABLE & !TXD_12_.Q & testpatt # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1309 ; (6 pterms, 9 signals) TXD_12_.C = clk ; (1 pterm, 1 signal) TXD_12_.CE = nx148 ; (1 pterm, 1 signal) TXD_12_.AR = !reset_n ; (1 pterm, 1 signal) TXD_13_.D = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !nx1325 # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !nx1325 # ENABLE & TXD_13_.Q & !TXD_12_.Q & testpatt # ENABLE & !TXD_13_.Q & TXD_12_.Q & testpatt # ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1333 # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1333 ; (6 pterms, 9 signals) TXD_13_.C = clk ; (1 pterm, 1 signal) TXD_13_.CE = nx148 ; (1 pterm, 1 signal) TXD_13_.AR = !reset_n ; (1 pterm, 1 signal) TXD_14_.D = ENABLE & !TXD_14_.Q & TXD_13_.Q & TXD_12_.Q & testpatt # ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & j2c__reg_creg0hm_0_.Q & !nx1325 # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_17_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_17_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_17_.Q # ENABLE & !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_18_.Q # ENABLE & !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_18_.Q # ENABLE & !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_18_.Q # ENABLE & TXD_14_.Q & !TXD_12_.Q & testpatt # ENABLE & TXD_14_.Q & !TXD_13_.Q & testpatt # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1325 ; (11 pterms, 13 signals) TXD_14_.C = clk ; (1 pterm, 1 signal) TXD_14_.CE = nx148 ; (1 pterm, 1 signal) TXD_14_.AR = !reset_n ; (1 pterm, 1 signal) TXD_15_.D.X1 = ENABLE & !j2c__reg_creg0hm_3_.Q & !testpatt & !nx1341 # ENABLE & !j2c__ix77 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_18_.Q # ENABLE & j2c__ix77 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_17_.Q # ENABLE & TXD_14_.Q & TXD_13_.Q & TXD_12_.Q & testpatt ; (4 pterms, 10 signals) TXD_15_.D.X2 = ENABLE & TXD_15_.Q & testpatt ; (1 pterm, 3 signals) TXD_15_.C = clk ; (1 pterm, 1 signal) TXD_15_.CE = nx148 ; (1 pterm, 1 signal) TXD_15_.AR = !reset_n ; (1 pterm, 1 signal) TXD_1_.D = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & nx1039 & ni_nires__reg_data_out_3_.Q # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !nx1039 & ni_nires__reg_data_out_2_.Q # ENABLE & TXD_1_.Q & !TXD_0_.Q & testpatt # ENABLE & !TXD_1_.Q & TXD_0_.Q & testpatt # ENABLE & j2c__reg_creg0hm_1_.Q & !nx990 & !testpatt # ENABLE & j2c__reg_creg0hm_2_.Q & !nx990 & !testpatt # ENABLE & j2c__reg_creg0hm_3_.Q & !nx990 & !testpatt ; (7 pterms, 11 signals) TXD_1_.C = clk ; (1 pterm, 1 signal) TXD_1_.CE = nx148 ; (1 pterm, 1 signal) TXD_1_.AR = !reset_n ; (1 pterm, 1 signal) TXD_2_.D = ENABLE & !j2c__ix77 & !j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_4_.Q # ENABLE & !j2c__ix77 & !j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_4_.Q # ENABLE & j2c__reg_creg0hm_1_.Q & !testpatt & nx1039 & j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1039 & j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_2_.Q # ENABLE & !TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & testpatt # ENABLE & j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_3_.Q # ENABLE & TXD_2_.Q & !TXD_0_.Q & testpatt # ENABLE & TXD_2_.Q & !TXD_1_.Q & testpatt # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & nx1039 & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & nx1039 & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & !nx1039 & ni_nires__reg_data_out_2_.Q # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1039 & ni_nires__reg_data_out_2_.Q ; (15 pterms, 15 signals) TXD_2_.C = clk ; (1 pterm, 1 signal) TXD_2_.CE = nx148 ; (1 pterm, 1 signal) TXD_2_.AR = !reset_n ; (1 pterm, 1 signal) TXD_3_.D.X1 = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !nx1052 # ENABLE & !j2c__ix77 & !j2c__ix99 & j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_4_.Q # ENABLE & !j2c__ix77 & !j2c__ix99 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_4_.Q # ENABLE & j2c__ix99 & j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__ix99 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__ix77 & j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_3_.Q # ENABLE & j2c__ix77 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_3_.Q # ENABLE & TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & testpatt ; (8 pterms, 12 signals) TXD_3_.D.X2 = ENABLE & TXD_3_.Q & testpatt ; (1 pterm, 3 signals) TXD_3_.C = clk ; (1 pterm, 1 signal) TXD_3_.CE = nx148 ; (1 pterm, 1 signal) TXD_3_.AR = !reset_n ; (1 pterm, 1 signal) TXD_4_.D = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & nx1059 & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_6_.Q # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !nx1059 & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_5_.Q # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & nx1059 & ni_nires__reg_data_out_6_.Q # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & !nx1052 & j2c__reg_creg0hm_0_.Q # ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1052 # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !nx1059 & ni_nires__reg_data_out_5_.Q # ENABLE & !TXD_4_.Q & testpatt # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1052 ; (8 pterms, 11 signals) TXD_4_.C = clk ; (1 pterm, 1 signal) TXD_4_.CE = nx148 ; (1 pterm, 1 signal) TXD_4_.AP = !reset_n ; (1 pterm, 1 signal) TXD_5_.D = ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & nx1059 & ni_nires__reg_data_out_6_.Q # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !nx1076 # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & !nx1076 # ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1059 & ni_nires__reg_data_out_5_.Q # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & nx1059 & ni_nires__reg_data_out_6_.Q # ENABLE & !TXD_5_.Q & !TXD_4_.Q & testpatt # ENABLE & TXD_5_.Q & TXD_4_.Q & testpatt # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1059 & ni_nires__reg_data_out_5_.Q ; (8 pterms, 11 signals) TXD_5_.C = clk ; (1 pterm, 1 signal) TXD_5_.CE = nx148 ; (1 pterm, 1 signal) TXD_5_.AP = !reset_n ; (1 pterm, 1 signal) TXD_6_.D = ENABLE & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1076 & j2c__reg_creg0hm_0_.Q # ENABLE & !TXD_6_.Q & !TXD_5_.Q & !TXD_4_.Q & testpatt # ENABLE & !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_8_.Q # ENABLE & !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_8_.Q # ENABLE & !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_8_.Q # ENABLE & TXD_6_.Q & TXD_4_.Q & testpatt # ENABLE & TXD_6_.Q & TXD_5_.Q & testpatt # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & ni_nires__reg_data_out_7_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & ni_nires__reg_data_out_7_.Q # ENABLE & j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !testpatt & ni_nires__reg_data_out_7_.Q # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1076 ; (11 pterms, 13 signals) TXD_6_.C = clk ; (1 pterm, 1 signal) TXD_6_.CE = nx148 ; (1 pterm, 1 signal) TXD_6_.AP = !reset_n ; (1 pterm, 1 signal) TXD_7_.D.X1 = ENABLE & !j2c__reg_creg0hm_3_.Q & !testpatt & !nx1099 # ENABLE & !j2c__ix77 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_8_.Q # ENABLE & j2c__ix77 & j2c__reg_creg0hm_3_.Q & !testpatt & ni_nires__reg_data_out_7_.Q # ENABLE & !TXD_6_.Q & !TXD_5_.Q & !TXD_4_.Q & testpatt ; (4 pterms, 10 signals) TXD_7_.D.X2 = ENABLE & TXD_7_.Q & testpatt ; (1 pterm, 3 signals) TXD_7_.C = clk ; (1 pterm, 1 signal) TXD_7_.CE = nx148 ; (1 pterm, 1 signal) TXD_7_.AP = !reset_n ; (1 pterm, 1 signal) TXD_8_.D = !( !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !testpatt & !j2c__ix107 & nx1255 & nx1263 # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & nx1263 # TXD_8_.Q & testpatt & nx1263 # !testpatt & nx1255 & nx1263 & !ni_nires__reg_data_out_10_.Q # !ENABLE & nx1263 ) ; (5 pterms, 14 signals) TXD_8_.C = clk ; (1 pterm, 1 signal) TXD_8_.CE = nx148 ; (1 pterm, 1 signal) TXD_8_.AP = !reset_n ; (1 pterm, 1 signal) TXD_9_.D = ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & nx1039 & ni_nires__reg_data_out_13_.Q # ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !nx1039 & ni_nires__reg_data_out_12_.Q # ENABLE & !TXD_9_.Q & !TXD_8_.Q & testpatt # ENABLE & TXD_9_.Q & TXD_8_.Q & testpatt # ENABLE & j2c__reg_creg0hm_1_.Q & !testpatt & !nx1265 # ENABLE & j2c__reg_creg0hm_2_.Q & !testpatt & !nx1265 # ENABLE & j2c__reg_creg0hm_3_.Q & !testpatt & !nx1265 ; (7 pterms, 11 signals) TXD_9_.C = clk ; (1 pterm, 1 signal) TXD_9_.CE = nx148 ; (1 pterm, 1 signal) TXD_9_.AP = !reset_n ; (1 pterm, 1 signal) TX_EN.D = !( testpatt & !reg_ni_pattcount_2_.Q & !reg_ni_pattcount_1_.Q & !reg_ni_pattcount_0_.Q & !reg_ni_pattcount_4_.Q & !reg_ni_pattcount_3_.Q # !testpatt & !ni_nires__reg_valid.Q # !ENABLE ) ; (3 pterms, 8 signals) TX_EN.C = clk ; (1 pterm, 1 signal) TX_ER = 0 ; (0 pterm, 0 signal) WP_EEP = !( j2c__ix77 & !j2c__ix99 & j2c__ix85 & j2c__ix107 ) ; (1 pterm, 4 signals) ix449.X1 = !TXD_14_.Q & !TXD_13_.Q & !ni_reg_prty_bit_neg_r.Q # !TXD_14_.Q & TXD_13_.Q & ni_reg_prty_bit_neg_r.Q # TXD_14_.Q & !TXD_13_.Q & ni_reg_prty_bit_neg_r.Q # TXD_14_.Q & TXD_13_.Q & !ni_reg_prty_bit_neg_r.Q ; (4 pterms, 3 signals) ix449.X2 = !TXD_15_.Q ; (1 pterm, 1 signal) ix521 = TXD_12_.Q & !TXD_11_.Q # !TXD_12_.Q & TXD_11_.Q ; (2 pterms, 2 signals) ix523 = TXD_10_.Q & !TXD_9_.Q # !TXD_10_.Q & TXD_9_.Q ; (2 pterms, 2 signals) ix793 = TXD_7_.Q & !ni_reg_prty_bit_pos_r.Q # !TXD_7_.Q & ni_reg_prty_bit_pos_r.Q ; (2 pterms, 2 signals) ix865.X1 = !TXD_3_.Q & !TXD_2_.Q & !TXD_1_.Q # !TXD_3_.Q & TXD_2_.Q & TXD_1_.Q # TXD_3_.Q & !TXD_2_.Q & TXD_1_.Q # TXD_3_.Q & TXD_2_.Q & !TXD_1_.Q ; (4 pterms, 3 signals) ix865.X2 = !TXD_4_.Q ; (1 pterm, 1 signal) ix867.X1 = !TXD_5_.Q & !ix793 & !ix865 # !TXD_5_.Q & ix793 & ix865 # TXD_5_.Q & !ix793 & ix865 # TXD_5_.Q & ix793 & !ix865 ; (4 pterms, 3 signals) ix867.X2 = !TXD_6_.Q ; (1 pterm, 1 signal) j2c__bitcnt_0_.D = !j2c__bitcnt_0_.Q ; (1 pterm, 1 signal) j2c__bitcnt_0_.C = !jTCK ; (1 pterm, 1 signal) j2c__bitcnt_0_.AR = !j2c__nx0 ; (1 pterm, 1 signal) j2c__bitcnt_1_.D = j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q # !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q ; (2 pterms, 2 signals) j2c__bitcnt_1_.C = !jTCK ; (1 pterm, 1 signal) j2c__bitcnt_1_.AR = !j2c__nx0 ; (1 pterm, 1 signal) j2c__bitcnt_2_.D = j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !j2c__bitcnt_0_.Q & j2c__bitcnt_2_.Q ; (3 pterms, 3 signals) j2c__bitcnt_2_.C = !jTCK ; (1 pterm, 1 signal) j2c__bitcnt_2_.AR = !j2c__nx0 ; (1 pterm, 1 signal) j2c__ix107 = !j2c__reg_creg1hm_2_.Q & j2c__ix59 & j2c__ix71 & !j2c__ix45 # j2c__reg_creg1hm_2_.Q & !j2c__ix71 # j2c__reg_creg1hm_2_.Q & !j2c__ix59 # j2c__reg_creg1hm_2_.Q & j2c__ix45 ; (4 pterms, 4 signals) j2c__ix45.X1 = !j2c__reg_creg1hm_5_.Q & !j2c__reg_creg1hm_4_.Q & !j2c__reg_creg1hm_3_.Q # !j2c__reg_creg1hm_5_.Q & j2c__reg_creg1hm_4_.Q & j2c__reg_creg1hm_3_.Q # j2c__reg_creg1hm_5_.Q & !j2c__reg_creg1hm_4_.Q & j2c__reg_creg1hm_3_.Q # j2c__reg_creg1hm_5_.Q & j2c__reg_creg1hm_4_.Q & !j2c__reg_creg1hm_3_.Q ; (4 pterms, 3 signals) j2c__ix45.X2 = !j2c__reg_creg1hm_6_.Q ; (1 pterm, 1 signal) j2c__ix59.X1 = !j2c__reg_creg1hm_6_.Q & !j2c__reg_creg1hm_5_.Q & !j2c__reg_creg1hm_1_.Q # !j2c__reg_creg1hm_6_.Q & j2c__reg_creg1hm_5_.Q & j2c__reg_creg1hm_1_.Q # j2c__reg_creg1hm_6_.Q & !j2c__reg_creg1hm_5_.Q & j2c__reg_creg1hm_1_.Q # j2c__reg_creg1hm_6_.Q & j2c__reg_creg1hm_5_.Q & !j2c__reg_creg1hm_1_.Q ; (4 pterms, 3 signals) j2c__ix59.X2 = !j2c__reg_creg1hm_2_.Q ; (1 pterm, 1 signal) j2c__ix71.X1 = !j2c__reg_creg1hm_6_.Q & !j2c__reg_creg1hm_4_.Q & !j2c__reg_creg1hm_0_.Q # !j2c__reg_creg1hm_6_.Q & j2c__reg_creg1hm_4_.Q & j2c__reg_creg1hm_0_.Q # j2c__reg_creg1hm_6_.Q & !j2c__reg_creg1hm_4_.Q & j2c__reg_creg1hm_0_.Q # j2c__reg_creg1hm_6_.Q & j2c__reg_creg1hm_4_.Q & !j2c__reg_creg1hm_0_.Q ; (4 pterms, 3 signals) j2c__ix71.X2 = !j2c__reg_creg1hm_2_.Q ; (1 pterm, 1 signal) j2c__ix77 = j2c__ix59 & j2c__ix71 & !j2c__reg_creg1hm_6_.Q & j2c__ix45 # !j2c__ix71 & j2c__reg_creg1hm_6_.Q # !j2c__ix59 & j2c__reg_creg1hm_6_.Q # j2c__reg_creg1hm_6_.Q & !j2c__ix45 ; (4 pterms, 4 signals) j2c__ix85 = !j2c__ix59 & j2c__ix71 & !j2c__reg_creg1hm_4_.Q & j2c__ix45 # !j2c__ix71 & j2c__reg_creg1hm_4_.Q # j2c__ix59 & j2c__reg_creg1hm_4_.Q # j2c__reg_creg1hm_4_.Q & !j2c__ix45 ; (4 pterms, 4 signals) j2c__ix99 = j2c__ix59 & !j2c__ix71 & !j2c__reg_creg1hm_5_.Q & j2c__ix45 # j2c__ix71 & j2c__reg_creg1hm_5_.Q # !j2c__ix59 & j2c__reg_creg1hm_5_.Q # j2c__reg_creg1hm_5_.Q & !j2c__ix45 ; (4 pterms, 4 signals) j2c__nx0 = !( !DIS_JTG & !jTMS ) ; (1 pterm, 2 signals) j2c__nx330 = reg_ID_1_0_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # reg_ID_1_1_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # reg_ID_1_2_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # reg_ID_1_3_.Q & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # reg_ID_1_4_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # reg_ID_1_5_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # reg_ID_1_6_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # FAULT & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q ; (8 pterms, 11 signals) j2c__nx365 = !reg_ID_0_4_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !reg_ID_0_5_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !reg_ID_0_6_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !reg_ID_0_7_.Q & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !reg_ID_0_0_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !reg_ID_0_1_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !reg_ID_0_2_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !reg_ID_0_3_.Q & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q ; (8 pterms, 11 signals) j2c__nx414 = j2c__reg_cmdreg_0_.Q & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & reg_ID_3_3_.Q # j2c__reg_cmdreg_0_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & reg_ID_3_5_.Q & j2c__bitcnt_2_.Q # j2c__reg_cmdreg_0_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & reg_ID_3_6_.Q & j2c__bitcnt_2_.Q # j2c__reg_cmdreg_0_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & reg_ID_3_1_.Q # j2c__reg_cmdreg_0_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & reg_ID_3_2_.Q # j2c__reg_cmdreg_0_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q & reg_ID_3_4_.Q # !j2c__reg_cmdreg_0_.Q & reg_ID_2_3_.Q & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !j2c__reg_cmdreg_0_.Q & reg_ID_2_5_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !j2c__reg_cmdreg_0_.Q & reg_ID_2_6_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !j2c__reg_cmdreg_0_.Q & j2c__bitcnt_0_.Q & reg_ID_2_1_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !j2c__reg_cmdreg_0_.Q & reg_ID_2_2_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # !j2c__reg_cmdreg_0_.Q & reg_ID_2_4_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # !j2c__reg_cmdreg_0_.Q & !j2c__bitcnt_0_.Q & reg_ID_2_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q # FAULT & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # j2c__reg_cmdreg_0_.Q & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & reg_ID_3_0_.Q ; (15 pterms, 19 signals) j2c__reg_cmdreg_0_.D = j2c__reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c__reg_cmdreg_0_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_cmdreg_0_.CE = jTDI ; (1 pterm, 1 signal) j2c__reg_cmdreg_0_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_cmdreg_1_.D = j2c__reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c__reg_cmdreg_1_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_cmdreg_1_.CE = jTDI ; (1 pterm, 1 signal) j2c__reg_cmdreg_1_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_cmdreg_2_.D = j2c__reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c__reg_cmdreg_2_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_cmdreg_2_.CE = jTDI ; (1 pterm, 1 signal) j2c__reg_cmdreg_2_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_cmdreg_3_.D = jTDI & j2c__reg_shreg_7_.Q ; (1 pterm, 2 signals) j2c__reg_cmdreg_3_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_cmdreg_3_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg0hm_0_.D = j2c__reg_shreg_0_.Q ; (1 pterm, 1 signal) j2c__reg_creg0hm_0_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg0hm_0_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg0hm_0_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg0hm_1_.D = j2c__reg_shreg_1_.Q ; (1 pterm, 1 signal) j2c__reg_creg0hm_1_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg0hm_1_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg0hm_1_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg0hm_2_.D = j2c__reg_shreg_2_.Q ; (1 pterm, 1 signal) j2c__reg_creg0hm_2_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg0hm_2_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg0hm_2_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg0hm_3_.D = j2c__reg_shreg_3_.Q ; (1 pterm, 1 signal) j2c__reg_creg0hm_3_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg0hm_3_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg0hm_3_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_0_.D = j2c__reg_shreg_4_.Q & !j2c__reg_shreg_5_.Q & !j2c__reg_shreg_7_.Q # !j2c__reg_shreg_4_.Q & j2c__reg_shreg_5_.Q & !j2c__reg_shreg_7_.Q # !j2c__reg_shreg_4_.Q & !j2c__reg_shreg_5_.Q & j2c__reg_shreg_7_.Q # j2c__reg_shreg_4_.Q & j2c__reg_shreg_5_.Q & j2c__reg_shreg_7_.Q ; (4 pterms, 3 signals) j2c__reg_creg1hm_0_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_0_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_0_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_1_.D = j2c__reg_shreg_4_.Q & !j2c__reg_shreg_6_.Q & !j2c__reg_shreg_7_.Q # !j2c__reg_shreg_4_.Q & j2c__reg_shreg_6_.Q & !j2c__reg_shreg_7_.Q # !j2c__reg_shreg_4_.Q & !j2c__reg_shreg_6_.Q & j2c__reg_shreg_7_.Q # j2c__reg_shreg_4_.Q & j2c__reg_shreg_6_.Q & j2c__reg_shreg_7_.Q ; (4 pterms, 3 signals) j2c__reg_creg1hm_1_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_1_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_1_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_2_.D = j2c__reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c__reg_creg1hm_2_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_2_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_2_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_3_.D = j2c__reg_shreg_5_.Q & !j2c__reg_shreg_6_.Q & !j2c__reg_shreg_7_.Q # !j2c__reg_shreg_5_.Q & j2c__reg_shreg_6_.Q & !j2c__reg_shreg_7_.Q # !j2c__reg_shreg_5_.Q & !j2c__reg_shreg_6_.Q & j2c__reg_shreg_7_.Q # j2c__reg_shreg_5_.Q & j2c__reg_shreg_6_.Q & j2c__reg_shreg_7_.Q ; (4 pterms, 3 signals) j2c__reg_creg1hm_3_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_3_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_3_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_4_.D = j2c__reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c__reg_creg1hm_4_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_4_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_4_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_5_.D = j2c__reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c__reg_creg1hm_5_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_5_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_5_.AR = !reset_n ; (1 pterm, 1 signal) j2c__reg_creg1hm_6_.D = j2c__reg_shreg_7_.Q ; (1 pterm, 1 signal) j2c__reg_creg1hm_6_.C = j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_creg1hm_6_.CE = !jTDI & !j2c__reg_cmdreg_0_.Q & j2c__reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c__reg_creg1hm_6_.AP = !reset_n ; (1 pterm, 1 signal) j2c__reg_rstout_n_i.D = j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q ; (1 pterm, 3 signals) j2c__reg_rstout_n_i.C = !jTCK ; (1 pterm, 1 signal) j2c__reg_rstout_n_i.CE = j2c__reg_rstout_n_i_0 ; (1 pterm, 1 signal) j2c__reg_rstout_n_i.AP = !j2c__nx0 ; (1 pterm, 1 signal) j2c__reg_rstout_n_i_0 = j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q # j2c__reg_cmdreg_3_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q ; (2 pterms, 4 signals) j2c__reg_shreg_0_.D = j2c__reg_shreg_1_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_0_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_1_.D = j2c__reg_shreg_2_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_1_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_2_.D = j2c__reg_shreg_3_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_2_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_3_.D = j2c__reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_3_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_4_.D = j2c__reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_4_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_5_.D = j2c__reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_5_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_6_.D = j2c__reg_shreg_7_.Q ; (1 pterm, 1 signal) j2c__reg_shreg_6_.C = jTCK ; (1 pterm, 1 signal) j2c__reg_shreg_7_.D = jTDI ; (1 pterm, 1 signal) j2c__reg_shreg_7_.C = jTCK ; (1 pterm, 1 signal) jTDO.X1 = !DIS_JTG & !j2c__reg_cmdreg_0_.Q & !j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q & !j2c__nx365 # !DIS_JTG & j2c__reg_cmdreg_0_.Q & !j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q & j2c__nx330 # !DIS_JTG & !j2c__reg_cmdreg_2_.Q & j2c__reg_cmdreg_1_.Q & j2c__nx414 # !DIS_JTG & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q & j2c__reg_creg0hm_0_.Q # !DIS_JTG & !j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q & j2c__ix107 # !DIS_JTG & j2c__reg_creg0hm_2_.Q & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q # !DIS_JTG & j2c__ix99 & !j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q # !DIS_JTG & j2c__reg_creg0hm_1_.Q & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q # !DIS_JTG & j2c__ix85 & j2c__bitcnt_0_.Q & !j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q # !DIS_JTG & j2c__reg_creg0hm_3_.Q & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & !j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q # !DIS_JTG & j2c__ix77 & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & !j2c__reg_cmdreg_1_.Q # !DIS_JTG & !j2c__ix59 & !j2c__ix71 & !j2c__ix45 & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__bitcnt_2_.Q & j2c__reg_cmdreg_2_.Q & j2c__reg_cmdreg_1_.Q # DIS_JTG & SDA.PIN ; (13 pterms, 22 signals) jTDO.X2 = !DIS_JTG & j2c__bitcnt_0_.Q & j2c__bitcnt_1_.Q & j2c__reg_cmdreg_2_.Q & j2c__reg_cmdreg_1_.Q ; (1 pterm, 5 signals) jTDO.OE = nx197 ; (1 pterm, 1 signal) ni_nires__nx1078 = ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_new_cnt_1_.Q # !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_new_cnt_1_.Q # ni_nires__reg_old_cnt_0_.Q & !ni_nires__reg_new_cnt_0_.Q # !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_new_cnt_0_.Q ; (4 pterms, 4 signals) ni_nires__reg_clear_n_i.D = reset_n & j2c__reg_rstout_n_i.Q ; (1 pterm, 2 signals) ni_nires__reg_clear_n_i.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data0neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_0_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_1_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_2_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_3_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_4_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_5_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_6_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_7_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_8_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data0neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0neg_9_.CE = !ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_0_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_1_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_2_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_3_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_4_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_5_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_6_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_7_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_8_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data0pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data0pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data0pos_9_.CE = !ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_0_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_1_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_2_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_3_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_4_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_5_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_6_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_7_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_8_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data1neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1neg_9_.CE = !ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_0_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_1_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_2_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_3_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_4_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_5_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_6_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_7_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_8_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data1pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data1pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data1pos_9_.CE = !ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_0_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_1_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_2_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_3_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_4_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_5_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_6_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_7_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_8_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data2neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2neg_9_.CE = ni_nires__reg_gray_cntf_1_.Q & ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_0_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_1_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_2_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_3_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_4_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_5_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_6_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_7_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_8_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data2pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data2pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data2pos_9_.CE = ni_nires__reg_gray_cnt_1_.Q & ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_0_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_1_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_2_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_3_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_4_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_5_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_6_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_7_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_8_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data3neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3neg_9_.CE = ni_nires__reg_gray_cntf_1_.Q & !ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_0_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_1_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_2_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_3_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_4_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_5_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_6_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_7_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_8_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data3pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires__reg_data3pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_data3pos_9_.CE = ni_nires__reg_gray_cnt_1_.Q & !ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires__reg_data_out_0_.D = !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data0neg_0_.Q # ni_nires__reg_data2neg_0_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data1neg_0_.Q # ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data3neg_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_0_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_10_.D = ni_nires__reg_data0pos_0_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_0_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_0_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_0_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_10_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_11_.D = ni_nires__reg_data0pos_1_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_1_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_1_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_1_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_11_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_12_.D = ni_nires__reg_data0pos_2_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_2_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_2_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_2_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_12_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_13_.D = ni_nires__reg_data0pos_3_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_3_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_3_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_3_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_13_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_14_.D = ni_nires__reg_data0pos_4_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_4_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_4_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_4_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_14_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_15_.D = ni_nires__reg_data0pos_5_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_5_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_5_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_5_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_15_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_16_.D = ni_nires__reg_data0pos_6_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_6_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_6_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_6_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_16_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_17_.D = ni_nires__reg_data0pos_7_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_7_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_7_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_7_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_17_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_18_.D = ni_nires__reg_data0pos_8_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_8_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_8_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_8_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_18_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_19_.D = ni_nires__reg_data0pos_9_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3pos_9_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1pos_9_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2pos_9_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_19_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_1_.D = !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data0neg_1_.Q # ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data2neg_1_.Q # !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data1neg_1_.Q # ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data3neg_1_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_1_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_2_.D = !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data0neg_2_.Q # ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data2neg_2_.Q # !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data1neg_2_.Q # ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data3neg_2_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_2_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_3_.D = !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data0neg_3_.Q # ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data2neg_3_.Q # !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data1neg_3_.Q # ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_data3neg_3_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_3_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_4_.D = ni_nires__reg_data0neg_4_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3neg_4_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1neg_4_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2neg_4_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_4_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_5_.D = ni_nires__reg_data0neg_5_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3neg_5_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1neg_5_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2neg_5_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_5_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_6_.D = ni_nires__reg_data0neg_6_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3neg_6_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1neg_6_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2neg_6_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_6_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_7_.D = ni_nires__reg_data0neg_7_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3neg_7_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1neg_7_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2neg_7_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_7_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_8_.D = ni_nires__reg_data0neg_8_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3neg_8_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1neg_8_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2neg_8_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_8_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_data_out_9_.D = ni_nires__reg_data0neg_9_.Q & !ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data3neg_9_.Q & ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data1neg_9_.Q & !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q # ni_nires__reg_data2neg_9_.Q & ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_old_cnt_0_.Q ; (4 pterms, 6 signals) ni_nires__reg_data_out_9_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_gray_cnt_0_.D = !ni_nires__reg_gray_cnt_1_.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cnt_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_gray_cnt_0_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cnt_1_.D = ni_nires__reg_gray_cnt_0_.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cnt_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires__reg_gray_cnt_1_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cntf_0_.D = !ni_nires__reg_gray_cntf_1_.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cntf_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_gray_cntf_0_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cntf_1_.D = ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 1 signal) ni_nires__reg_gray_cntf_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires__reg_gray_cntf_1_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_new_cnt_0_.D = ni_nires__reg_gray_cntf_0_.Q ; (1 pterm, 1 signal) ni_nires__reg_new_cnt_0_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_new_cnt_0_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_new_cnt_1_.D = ni_nires__reg_gray_cntf_1_.Q ; (1 pterm, 1 signal) ni_nires__reg_new_cnt_1_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_new_cnt_1_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_0_.D = !ni_nires__reg_old_cnt_1_.Q ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_0_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_0_.CE = ni_nires__nx1078 ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_0_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_1_.D = ni_nires__reg_old_cnt_0_.Q ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_1_.C = clk ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_1_.CE = ni_nires__nx1078 ; (1 pterm, 1 signal) ni_nires__reg_old_cnt_1_.AR = !ni_nires__reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires__reg_valid.D = ni_nires__reg_old_cnt_1_.Q & !ni_nires__reg_new_cnt_1_.Q # !ni_nires__reg_old_cnt_1_.Q & ni_nires__reg_new_cnt_1_.Q # ni_nires__reg_old_cnt_0_.Q & !ni_nires__reg_new_cnt_0_.Q # !ni_nires__reg_old_cnt_0_.Q & ni_nires__reg_new_cnt_0_.Q ; (4 pterms, 4 signals) ni_nires__reg_valid.C = clk ; (1 pterm, 1 signal) ni_reg_ce_prty_bit_neg.D.X1 = TX_EN.Q & !ix449 & !ix521 & !ix523 # TX_EN.Q & !ix449 & ix521 & ix523 # TX_EN.Q & ix449 & !ix521 & ix523 # TX_EN.Q & ix449 & ix521 & !ix523 ; (4 pterms, 4 signals) ni_reg_ce_prty_bit_neg.D.X2 = TX_EN.Q & !TXD_8_.Q ; (1 pterm, 2 signals) ni_reg_ce_prty_bit_neg.C = clk ; (1 pterm, 1 signal) ni_reg_ce_prty_bit_pos.D = TX_EN.Q & TXD_0_.Q & !ix867 # TX_EN.Q & !TXD_0_.Q & ix867 ; (2 pterms, 3 signals) ni_reg_ce_prty_bit_pos.C = clk ; (1 pterm, 1 signal) ni_reg_prty_bit_neg_r.D = !( !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !j2c__ix107 & !j2c__reg_creg0hm_0_.Q & nx1255 # !j2c__ix77 & !j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_14_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !j2c__reg_creg0hm_0_.Q & nx1255 & !ni_nires__reg_data_out_10_.Q # j2c__ix77 & !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_17_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !nx1039 & !j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_12_.Q # !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_18_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & nx1039 & !j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_13_.Q # j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_13_.Q # j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_13_.Q # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !j2c__reg_creg0hm_0_.Q & nx1309 # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & nx1333 # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !j2c__reg_creg0hm_0_.Q & nx1325 # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & nx1265 # j2c__reg_creg0hm_3_.Q & nx1341 ) ; (14 pterms, 21 signals) ni_reg_prty_bit_neg_r.C = clk ; (1 pterm, 1 signal) ni_reg_prty_bit_pos_r.D = !( !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & nx972 & !j2c__ix107 & !j2c__reg_creg0hm_0_.Q # !j2c__ix77 & !j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_4_.Q # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !nx1059 & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_5_.Q # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & nx1059 & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_6_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & !nx1039 & !j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_2_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & nx1039 & !j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_3_.Q # j2c__ix77 & !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_7_.Q # !j2c__ix77 & !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_8_.Q # j2c__ix99 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_3_.Q # j2c__ix77 & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_3_.Q # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & nx1052 & !j2c__reg_creg0hm_0_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & nx972 & !j2c__reg_creg0hm_0_.Q & !ni_nires__reg_data_out_0_.Q # !j2c__reg_creg0hm_3_.Q & j2c__reg_creg0hm_2_.Q & j2c__reg_creg0hm_1_.Q & nx1076 & !j2c__reg_creg0hm_0_.Q # !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & nx990 & j2c__reg_creg0hm_0_.Q # j2c__reg_creg0hm_3_.Q & nx1099 ) ; (15 pterms, 23 signals) ni_reg_prty_bit_pos_r.C = clk ; (1 pterm, 1 signal) nx1039 = !j2c__ix77 & !j2c__ix99 & !j2c__ix85 # !j2c__ix77 & !j2c__ix99 & !j2c__ix107 ; (2 pterms, 4 signals) nx1052 = nx1059 & !j2c__ix107 & !ni_nires__reg_data_out_5_.Q # !j2c__ix99 & nx1059 & !ni_nires__reg_data_out_5_.Q # j2c__ix99 & j2c__ix107 & !ni_nires__reg_data_out_4_.Q # !nx1059 & !ni_nires__reg_data_out_4_.Q ; (4 pterms, 5 signals) nx1059 = !j2c__ix77 & !j2c__ix99 # !j2c__ix77 & !j2c__ix85 ; (2 pterms, 3 signals) nx1076.X1 = j2c__ix77 & !ni_nires__reg_data_out_6_.Q # !j2c__ix77 & j2c__ix99 & j2c__ix85 & j2c__ix107 & !ni_nires__reg_data_out_7_.Q & ni_nires__reg_data_out_6_.Q # !j2c__ix77 & j2c__ix99 & j2c__ix85 & j2c__ix107 & ni_nires__reg_data_out_7_.Q & !ni_nires__reg_data_out_6_.Q ; (3 pterms, 6 signals) nx1076.X2 = !j2c__ix77 & !ni_nires__reg_data_out_7_.Q ; (1 pterm, 2 signals) nx1099.X1 = !j2c__ix77 & !ni_nires__reg_data_out_9_.Q # j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__ix107 & ni_nires__reg_data_out_9_.Q & !ni_nires__reg_data_out_8_.Q # j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__ix107 & !ni_nires__reg_data_out_9_.Q & ni_nires__reg_data_out_8_.Q ; (3 pterms, 6 signals) nx1099.X2 = j2c__ix77 & !ni_nires__reg_data_out_8_.Q ; (1 pterm, 2 signals) nx12 = DIS_JTG & !jTCK # !ENABLE ; (2 pterms, 3 signals) nx1255 = !( !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__ix107 & ni_nires__reg_data_out_11_.Q ) ; (1 pterm, 5 signals) nx1263 = !( ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !testpatt & !j2c__reg_creg0hm_0_.Q & !nx1265 ) ; (1 pterm, 7 signals) nx1265 = !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !ni_nires__reg_data_out_12_.Q # j2c__ix85 & !ni_nires__reg_data_out_11_.Q # j2c__ix99 & !ni_nires__reg_data_out_11_.Q # j2c__ix77 & !ni_nires__reg_data_out_11_.Q ; (4 pterms, 5 signals) nx1309 = nx1059 & !j2c__ix107 & !ni_nires__reg_data_out_15_.Q # !j2c__ix99 & nx1059 & !ni_nires__reg_data_out_15_.Q # j2c__ix99 & j2c__ix107 & !ni_nires__reg_data_out_14_.Q # !nx1059 & !ni_nires__reg_data_out_14_.Q ; (4 pterms, 5 signals) nx1325.X1 = j2c__ix77 & !ni_nires__reg_data_out_16_.Q # !j2c__ix77 & j2c__ix99 & j2c__ix85 & j2c__ix107 & !ni_nires__reg_data_out_17_.Q & ni_nires__reg_data_out_16_.Q # !j2c__ix77 & j2c__ix99 & j2c__ix85 & j2c__ix107 & ni_nires__reg_data_out_17_.Q & !ni_nires__reg_data_out_16_.Q ; (3 pterms, 6 signals) nx1325.X2 = !j2c__ix77 & !ni_nires__reg_data_out_17_.Q ; (1 pterm, 2 signals) nx1333 = nx1059 & !ni_nires__reg_data_out_16_.Q # !nx1059 & !ni_nires__reg_data_out_15_.Q ; (2 pterms, 3 signals) nx1341.X1 = !j2c__ix77 & !ni_nires__reg_data_out_19_.Q # j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__ix107 & ni_nires__reg_data_out_19_.Q & !ni_nires__reg_data_out_18_.Q # j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__ix107 & !ni_nires__reg_data_out_19_.Q & ni_nires__reg_data_out_18_.Q ; (3 pterms, 6 signals) nx1341.X2 = j2c__ix77 & !ni_nires__reg_data_out_18_.Q ; (1 pterm, 2 signals) nx148 = !( ENABLE & !TX_EN.Q & testpatt # ENABLE & !testpatt & !ni_nires__reg_valid.Q ) ; (2 pterms, 4 signals) nx197 = DIS_JTG # jTCK & j2c__nx0 ; (2 pterms, 3 signals) nx20 = DIS_JTG & !jTMS # !ENABLE ; (2 pterms, 3 signals) nx96 = reg_ID_0_7_.Q & reg_ID_0_6_.Q & reg_ID_0_5_.Q & reg_ID_0_4_.Q & reg_ID_0_3_.Q & reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q ; (1 pterm, 8 signals) nx972 = !( !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !j2c__ix107 & ni_nires__reg_data_out_1_.Q ) ; (1 pterm, 5 signals) nx988 = !( ENABLE & !j2c__reg_creg0hm_3_.Q & !j2c__reg_creg0hm_2_.Q & !j2c__reg_creg0hm_1_.Q & !nx990 & !testpatt & !j2c__reg_creg0hm_0_.Q ) ; (1 pterm, 7 signals) nx990 = !j2c__ix77 & !j2c__ix99 & !j2c__ix85 & !ni_nires__reg_data_out_2_.Q # j2c__ix85 & !ni_nires__reg_data_out_1_.Q # j2c__ix99 & !ni_nires__reg_data_out_1_.Q # j2c__ix77 & !ni_nires__reg_data_out_1_.Q ; (4 pterms, 5 signals) reg_ID_0_0_.D = !reg_ID_0_0_.Q ; (1 pterm, 1 signal) reg_ID_0_0_.C = clk ; (1 pterm, 1 signal) reg_ID_0_0_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_0_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_1_.D = reg_ID_0_1_.Q & !reg_ID_0_0_.Q # !reg_ID_0_1_.Q & reg_ID_0_0_.Q ; (2 pterms, 2 signals) reg_ID_0_1_.C = clk ; (1 pterm, 1 signal) reg_ID_0_1_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_1_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_2_.D = !reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q # reg_ID_0_2_.Q & !reg_ID_0_1_.Q # reg_ID_0_2_.Q & !reg_ID_0_0_.Q ; (3 pterms, 3 signals) reg_ID_0_2_.C = clk ; (1 pterm, 1 signal) reg_ID_0_2_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_2_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_3_.D = !reg_ID_0_3_.Q & reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q # reg_ID_0_3_.Q & !reg_ID_0_1_.Q # reg_ID_0_3_.Q & !reg_ID_0_2_.Q # reg_ID_0_3_.Q & !reg_ID_0_0_.Q ; (4 pterms, 4 signals) reg_ID_0_3_.C = clk ; (1 pterm, 1 signal) reg_ID_0_3_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_3_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_4_.D.X1 = reg_ID_0_4_.Q ; (1 pterm, 1 signal) reg_ID_0_4_.D.X2 = reg_ID_0_3_.Q & reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q ; (1 pterm, 4 signals) reg_ID_0_4_.C = clk ; (1 pterm, 1 signal) reg_ID_0_4_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_4_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_5_.T = reg_ID_0_4_.Q & reg_ID_0_3_.Q & reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q ; (1 pterm, 5 signals) reg_ID_0_5_.C = clk ; (1 pterm, 1 signal) reg_ID_0_5_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_5_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_6_.T = reg_ID_0_5_.Q & reg_ID_0_4_.Q & reg_ID_0_3_.Q & reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q ; (1 pterm, 6 signals) reg_ID_0_6_.C = clk ; (1 pterm, 1 signal) reg_ID_0_6_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_6_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_7_.T = reg_ID_0_6_.Q & reg_ID_0_5_.Q & reg_ID_0_4_.Q & reg_ID_0_3_.Q & reg_ID_0_2_.Q & reg_ID_0_1_.Q & reg_ID_0_0_.Q ; (1 pterm, 7 signals) reg_ID_0_7_.C = clk ; (1 pterm, 1 signal) reg_ID_0_7_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_0_7_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_0_7__0 = !( reset_n & j2c__reg_rstout_n_i.Q ) ; (1 pterm, 2 signals) reg_ID_1_0_.D = reg_ID_1_0_.Q & !nx96 # !reg_ID_1_0_.Q & nx96 ; (2 pterms, 2 signals) reg_ID_1_0_.C = clk ; (1 pterm, 1 signal) reg_ID_1_0_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_0_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_1_1_.D = !reg_ID_1_1_.Q & reg_ID_1_0_.Q & nx96 # reg_ID_1_1_.Q & !reg_ID_1_0_.Q # reg_ID_1_1_.Q & !nx96 ; (3 pterms, 3 signals) reg_ID_1_1_.C = clk ; (1 pterm, 1 signal) reg_ID_1_1_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_1_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_1_2_.D = !reg_ID_1_2_.Q & reg_ID_1_1_.Q & reg_ID_1_0_.Q & nx96 # reg_ID_1_2_.Q & !reg_ID_1_0_.Q # reg_ID_1_2_.Q & !reg_ID_1_1_.Q # reg_ID_1_2_.Q & !nx96 ; (4 pterms, 4 signals) reg_ID_1_2_.C = clk ; (1 pterm, 1 signal) reg_ID_1_2_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_2_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_1_3_.D.X1 = reg_ID_1_3_.Q ; (1 pterm, 1 signal) reg_ID_1_3_.D.X2 = reg_ID_1_2_.Q & reg_ID_1_1_.Q & reg_ID_1_0_.Q & nx96 ; (1 pterm, 4 signals) reg_ID_1_3_.C = clk ; (1 pterm, 1 signal) reg_ID_1_3_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_3_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_1_4_.T = reg_ID_1_3_.Q & reg_ID_1_2_.Q & reg_ID_1_1_.Q & reg_ID_1_0_.Q & nx96 ; (1 pterm, 5 signals) reg_ID_1_4_.C = clk ; (1 pterm, 1 signal) reg_ID_1_4_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_4_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_1_5_.T = reg_ID_1_4_.Q & reg_ID_1_3_.Q & reg_ID_1_2_.Q & reg_ID_1_1_.Q & reg_ID_1_0_.Q & nx96 ; (1 pterm, 6 signals) reg_ID_1_5_.C = clk ; (1 pterm, 1 signal) reg_ID_1_5_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_5_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_1_6_.T = reg_ID_1_5_.Q & reg_ID_1_4_.Q & reg_ID_1_3_.Q & reg_ID_1_2_.Q & reg_ID_1_1_.Q & reg_ID_1_0_.Q & nx96 ; (1 pterm, 7 signals) reg_ID_1_6_.C = clk ; (1 pterm, 1 signal) reg_ID_1_6_.CE = TX_EN.Q ; (1 pterm, 1 signal) reg_ID_1_6_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_0_.D = !reg_ID_2_0_.Q ; (1 pterm, 1 signal) reg_ID_2_0_.C = clk ; (1 pterm, 1 signal) reg_ID_2_0_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_0_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_1_.D = reg_ID_2_1_.Q & !reg_ID_2_0_.Q # !reg_ID_2_1_.Q & reg_ID_2_0_.Q ; (2 pterms, 2 signals) reg_ID_2_1_.C = clk ; (1 pterm, 1 signal) reg_ID_2_1_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_1_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_2_.D = !reg_ID_2_2_.Q & reg_ID_2_1_.Q & reg_ID_2_0_.Q # reg_ID_2_2_.Q & !reg_ID_2_1_.Q # reg_ID_2_2_.Q & !reg_ID_2_0_.Q ; (3 pterms, 3 signals) reg_ID_2_2_.C = clk ; (1 pterm, 1 signal) reg_ID_2_2_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_2_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_3_.D = !reg_ID_2_3_.Q & reg_ID_2_2_.Q & reg_ID_2_1_.Q & reg_ID_2_0_.Q # reg_ID_2_3_.Q & !reg_ID_2_1_.Q # reg_ID_2_3_.Q & !reg_ID_2_2_.Q # reg_ID_2_3_.Q & !reg_ID_2_0_.Q ; (4 pterms, 4 signals) reg_ID_2_3_.C = clk ; (1 pterm, 1 signal) reg_ID_2_3_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_3_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_4_.D.X1 = reg_ID_2_4_.Q ; (1 pterm, 1 signal) reg_ID_2_4_.D.X2 = reg_ID_2_3_.Q & reg_ID_2_2_.Q & reg_ID_2_1_.Q & reg_ID_2_0_.Q ; (1 pterm, 4 signals) reg_ID_2_4_.C = clk ; (1 pterm, 1 signal) reg_ID_2_4_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_4_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_5_.T = reg_ID_2_4_.Q & reg_ID_2_3_.Q & reg_ID_2_2_.Q & reg_ID_2_1_.Q & reg_ID_2_0_.Q ; (1 pterm, 5 signals) reg_ID_2_5_.C = clk ; (1 pterm, 1 signal) reg_ID_2_5_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_5_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_6_.T = reg_ID_2_5_.Q & reg_ID_2_4_.Q & reg_ID_2_3_.Q & reg_ID_2_2_.Q & reg_ID_2_1_.Q & reg_ID_2_0_.Q ; (1 pterm, 6 signals) reg_ID_2_6_.C = clk ; (1 pterm, 1 signal) reg_ID_2_6_.CE = !( reg_ID_2_6__0 ) ; (1 pterm, 1 signal) reg_ID_2_6_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_2_6__0 = !ni_reg_ce_prty_bit_neg.Q # reg_ID_2_6_.Q & reg_ID_2_5_.Q & reg_ID_2_4_.Q & reg_ID_2_3_.Q & reg_ID_2_2_.Q & reg_ID_2_1_.Q & reg_ID_2_0_.Q ; (2 pterms, 8 signals) reg_ID_3_0_.D = !reg_ID_3_0_.Q ; (1 pterm, 1 signal) reg_ID_3_0_.C = clk ; (1 pterm, 1 signal) reg_ID_3_0_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_0_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_1_.D = reg_ID_3_1_.Q & !reg_ID_3_0_.Q # !reg_ID_3_1_.Q & reg_ID_3_0_.Q ; (2 pterms, 2 signals) reg_ID_3_1_.C = clk ; (1 pterm, 1 signal) reg_ID_3_1_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_1_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_2_.D = !reg_ID_3_2_.Q & reg_ID_3_1_.Q & reg_ID_3_0_.Q # reg_ID_3_2_.Q & !reg_ID_3_1_.Q # reg_ID_3_2_.Q & !reg_ID_3_0_.Q ; (3 pterms, 3 signals) reg_ID_3_2_.C = clk ; (1 pterm, 1 signal) reg_ID_3_2_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_2_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_3_.D = !reg_ID_3_3_.Q & reg_ID_3_2_.Q & reg_ID_3_1_.Q & reg_ID_3_0_.Q # reg_ID_3_3_.Q & !reg_ID_3_1_.Q # reg_ID_3_3_.Q & !reg_ID_3_2_.Q # reg_ID_3_3_.Q & !reg_ID_3_0_.Q ; (4 pterms, 4 signals) reg_ID_3_3_.C = clk ; (1 pterm, 1 signal) reg_ID_3_3_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_3_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_4_.D.X1 = reg_ID_3_4_.Q ; (1 pterm, 1 signal) reg_ID_3_4_.D.X2 = reg_ID_3_3_.Q & reg_ID_3_2_.Q & reg_ID_3_1_.Q & reg_ID_3_0_.Q ; (1 pterm, 4 signals) reg_ID_3_4_.C = clk ; (1 pterm, 1 signal) reg_ID_3_4_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_4_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_5_.T = reg_ID_3_4_.Q & reg_ID_3_3_.Q & reg_ID_3_2_.Q & reg_ID_3_1_.Q & reg_ID_3_0_.Q ; (1 pterm, 5 signals) reg_ID_3_5_.C = clk ; (1 pterm, 1 signal) reg_ID_3_5_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_5_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_6_.T = reg_ID_3_5_.Q & reg_ID_3_4_.Q & reg_ID_3_3_.Q & reg_ID_3_2_.Q & reg_ID_3_1_.Q & reg_ID_3_0_.Q ; (1 pterm, 6 signals) reg_ID_3_6_.C = clk ; (1 pterm, 1 signal) reg_ID_3_6_.CE = !( reg_ID_3_6__0 ) ; (1 pterm, 1 signal) reg_ID_3_6_.AR = reg_ID_0_7__0 ; (1 pterm, 1 signal) reg_ID_3_6__0 = !ni_reg_ce_prty_bit_pos.Q # reg_ID_3_6_.Q & reg_ID_3_5_.Q & reg_ID_3_4_.Q & reg_ID_3_3_.Q & reg_ID_3_2_.Q & reg_ID_3_1_.Q & reg_ID_3_0_.Q ; (2 pterms, 8 signals) reg_ni_pattcount_0_.D = !reg_ni_pattcount_0_.Q ; (1 pterm, 1 signal) reg_ni_pattcount_0_.C = clk ; (1 pterm, 1 signal) reg_ni_pattcount_1_.D = reg_ni_pattcount_1_.Q & !reg_ni_pattcount_0_.Q # !reg_ni_pattcount_1_.Q & reg_ni_pattcount_0_.Q ; (2 pterms, 2 signals) reg_ni_pattcount_1_.C = clk ; (1 pterm, 1 signal) reg_ni_pattcount_2_.D = !reg_ni_pattcount_2_.Q & reg_ni_pattcount_1_.Q & reg_ni_pattcount_0_.Q # reg_ni_pattcount_2_.Q & !reg_ni_pattcount_1_.Q # reg_ni_pattcount_2_.Q & !reg_ni_pattcount_0_.Q ; (3 pterms, 3 signals) reg_ni_pattcount_2_.C = clk ; (1 pterm, 1 signal) reg_ni_pattcount_3_.D = reg_ni_pattcount_2_.Q & reg_ni_pattcount_1_.Q & reg_ni_pattcount_0_.Q & !reg_ni_pattcount_3_.Q # !reg_ni_pattcount_0_.Q & reg_ni_pattcount_3_.Q # !reg_ni_pattcount_1_.Q & reg_ni_pattcount_3_.Q # !reg_ni_pattcount_2_.Q & reg_ni_pattcount_3_.Q ; (4 pterms, 4 signals) reg_ni_pattcount_3_.C = clk ; (1 pterm, 1 signal) reg_ni_pattcount_4_.D.X1 = reg_ni_pattcount_2_.Q & reg_ni_pattcount_1_.Q & reg_ni_pattcount_0_.Q & reg_ni_pattcount_3_.Q ; (1 pterm, 4 signals) reg_ni_pattcount_4_.D.X2 = reg_ni_pattcount_4_.Q ; (1 pterm, 1 signal) reg_ni_pattcount_4_.C = clk ; (1 pterm, 1 signal) testpatt = j2c__ix77 & j2c__ix99 & !j2c__ix85 & !j2c__ix107 ; (1 pterm, 4 signals)