MODELDATA
MODELDATA_VERSION "1.0";
DESIGN "oase";
DATE "Fri Sep 23 10:38:45 2005";
VENDOR "Lattice Semiconductor Corporation";
PROGRAM "STAMP Model Generator";

/* port drive, max transition and max capacitance */
PORTDATA
GTX_CLK_OE: MAXTRANS(0.0);
NI_CTR: MAXTRANS(0.0);
NI_STR: MAXTRANS(0.0);
clk: MAXTRANS(0.0);
reset_n: MAXTRANS(0.0);
EN: MAXTRANS(0.0);
ENABLE: MAXTRANS(0.0);
GTX_CLK: MAXTRANS(0.0);
LCKREFN: MAXTRANS(0.0);
LED_5: MAXTRANS(0.0);
LED_6: MAXTRANS(0.0);
LED_7: MAXTRANS(0.0);
LED_8: MAXTRANS(0.0);
LED_9: MAXTRANS(0.0);
LED_10: MAXTRANS(0.0);
LOOPEN: MAXTRANS(0.0);
PRBSEN: MAXTRANS(0.0);
TESTEN: MAXTRANS(0.0);
TXD_0: MAXTRANS(0.0);
TXD_1: MAXTRANS(0.0);
TXD_2: MAXTRANS(0.0);
TXD_3: MAXTRANS(0.0);
TXD_4: MAXTRANS(0.0);
TXD_5: MAXTRANS(0.0);
TXD_6: MAXTRANS(0.0);
TXD_7: MAXTRANS(0.0);
TXD_8: MAXTRANS(0.0);
TXD_9: MAXTRANS(0.0);
TXD_10: MAXTRANS(0.0);
TXD_11: MAXTRANS(0.0);
TXD_12: MAXTRANS(0.0);
TXD_13: MAXTRANS(0.0);
TXD_14: MAXTRANS(0.0);
TXD_15: MAXTRANS(0.0);
TX_EN: MAXTRANS(0.0);
TX_ER: MAXTRANS(0.0);
ENDPORTDATA

/* timing arc data */
TIMINGDATA

ARCDATA
clk_GTX_CLK_delay:
CELL_RISE(scalar) {
VALUES(4.0);
}
CELL_FALL(scalar) {
VALUES(4.0);
}
ENDARCDATA

ARCDATA
NI_STR_LED_5_delay:
CELL_RISE(scalar) {
VALUES(5.3);
}
CELL_FALL(scalar) {
VALUES(5.3);
}
ENDARCDATA

ARCDATA
NI_STR_LED_6_delay:
CELL_RISE(scalar) {
VALUES(5.3);
}
CELL_FALL(scalar) {
VALUES(5.3);
}
ENDARCDATA

ARCDATA
NI_STR_LED_7_delay:
CELL_RISE(scalar) {
VALUES(5.3);
}
CELL_FALL(scalar) {
VALUES(5.3);
}
ENDARCDATA

ARCDATA
NI_STR_LED_8_delay:
CELL_RISE(scalar) {
VALUES(5.3);
}
CELL_FALL(scalar) {
VALUES(5.3);
}
ENDARCDATA

ARCDATA
NI_STR_LED_9_delay:
CELL_RISE(scalar) {
VALUES(5.3);
}
CELL_FALL(scalar) {
VALUES(5.3);
}
ENDARCDATA

ARCDATA
NI_STR_LED_10_delay:
CELL_RISE(scalar) {
VALUES(5.3);
}
CELL_FALL(scalar) {
VALUES(5.3);
}
ENDARCDATA

ARCDATA
clk_TX_EN_delay:
CELL_RISE(scalar) {
VALUES(2.9);
}
CELL_FALL(scalar) {
VALUES(2.9);
}
ENDARCDATA

ENDTIMINGDATA
ENDMODELDATA