#$ TOOL ispLEVER 6.1.00.38.44.06
#$ DATE Mon Sep 10 14:07:14 2007
#$ MODULE oase
#$ PINS 47 NI_D_9_ NI_STR reset_n clk TESTEN PRBSEN LCKREFN ENABLE LOOPEN TX_ER TX_EN \
#  TXD_15_ DIS_JTG FAULT EN SD2ANL WP_EEP SCL SDA jTCK jTDI jTDO jTMS NI_D_8_ NI_D_7_ NI_D_6_ \
#  NI_D_5_ NI_D_4_ NI_D_3_ NI_D_2_ NI_D_1_ NI_D_0_ TXD_14_ TXD_13_ TXD_12_ TXD_11_ TXD_10_ \
#  TXD_9_ TXD_8_ TXD_7_ TXD_6_ TXD_5_ TXD_4_ TXD_3_ TXD_2_ TXD_1_ TXD_0_
#$ NODES 232 ni_nires__reg_data2neg_4_ ni_nires__reg_data0neg_4_ \
#  ni_nires__reg_data1neg_4_ ni_nires__reg_data3neg_4_ ni_nires__reg_data2neg_5_ \
#  ni_nires__reg_data0neg_5_ ni_nires__reg_data1neg_5_ ni_nires__reg_data3neg_5_ \
#  int_SD2ANL ni_reg_valid2reg reg_TXD_15_reg ni_nires__reg_data2neg_6_ \
#  reg_TXD_14_reg ni_nires__reg_data0neg_6_ reg_TXD_13_reg ni_nires__reg_data1neg_6_ \
#  reg_TXD_12_reg ni_nires__reg_data3neg_6_ reg_TXD_11_reg j2c__reg_creg1hm_2_ \
#  reg_TXD_10_reg reg_TXD_9_reg j2c__reg_shreg_4_ reg_TXD_8_reg reg_TXD_7_reg j2c__nx0 \
#  reg_TXD_6_reg j2c__reg_cmdreg_0_ ni_nires__reg_data2neg_7_ reg_TXD_5_reg \
#  j2c__reg_shreg_5_ ni_nires__reg_data0neg_7_ reg_TXD_4_reg j2c__reg_shreg_6_ \
#  ni_nires__reg_data1neg_7_ reg_TXD_3_reg j2c__reg_shreg_7_ \
#  ni_nires__reg_data3neg_7_ reg_TXD_2_reg reg_TXD_1_reg j2c__reg_cmdreg_3_ \
#  reg_TXD_0_reg j2c__ix59 j2c__ix71 j2c__reg_creg1hm_6_ ni_nires__reg_data2neg_8_ \
#  j2c__reg_creg1hm_5_ ni_nires__reg_data0neg_8_ j2c__reg_creg1hm_4_ \
#  ni_nires__reg_data1neg_8_ ni_nires__reg_data3neg_8_ j2c__reg_creg1hm_3_ \
#  j2c__reg_creg1hm_1_ j2c__ix77 ni_nires__reg_data2neg_9_ j2c__ix99 \
#  ni_nires__reg_data0neg_9_ j2c__ix85 ni_nires__reg_data1neg_9_ \
#  ni_nires__reg_data3neg_9_ j2c__reg_creg0hm_3_ j2c__reg_creg1hm_0_ \
#  j2c__reg_creg0hm_2_ j2c__reg_creg0hm_1_ reg_ID_0_7_ j2c__ix45 reg_ID_0_6_ \
#  ni_nires__reg_data2pos_0_ reg_ID_0_5_ reg_ID_0_4_ ni_nires__reg_gray_cnt_1_ \
#  reg_ID_0_3_ ni_nires__reg_gray_cnt_0_ reg_ID_0_2_ reg_ID_0_1_ nx972 \
#  ni_nires__reg_data0pos_0_ reg_ID_0_0_ reg_ID_1_6_ ni_nires__reg_data1pos_0_ \
#  reg_ID_1_5_ j2c__reg_shreg_0_ reg_ID_1_4_ j2c__reg_shreg_1_ \
#  ni_nires__reg_data3pos_0_ reg_ID_1_3_ j2c__reg_shreg_2_ reg_ID_1_2_ \
#  j2c__reg_shreg_3_ reg_ID_1_1_ j2c__reg_rstout_n_i reg_ID_1_0_ nx988 reg_ID_2_6_ \
#  nx990 reg_ID_2_5_ reg_ID_2_4_ ni_nires__reg_data2pos_1_ reg_ID_2_3_ \
#  ni_nires__reg_data0pos_1_ reg_ID_2_2_ j2c__bitcnt_0_ ni_nires__reg_data1pos_1_ \
#  reg_ID_2_1_ ni_nires__reg_data3pos_1_ reg_ID_2_0_ j2c__bitcnt_1_ reg_ID_3_6_ \
#  reg_ID_3_5_ j2c__bitcnt_2_ reg_ID_3_4_ reg_ID_3_3_ ni_nires__reg_data2pos_2_ \
#  reg_ID_3_2_ ni_nires__reg_data0pos_2_ reg_ID_3_1_ ni_nires__reg_data1pos_2_ \
#  reg_ID_3_0_ j2c__reg_cmdreg_2_ ni_nires__reg_data3pos_2_ testpatt \
#  j2c__reg_cmdreg_1_ nx12 nx1039 j2c__nx414 nx20 ni_nires__reg_data2pos_3_ \
#  ni_nires__reg_data0pos_3_ nx197 ni_nires__reg_data1pos_3_ \
#  ni_nires__reg_data3pos_3_ nx1052 nx1059 ni_nires__reg_data2pos_4_ \
#  ni_nires__reg_data0pos_4_ ni_nires__reg_data1pos_4_ ni_nires__reg_data3pos_4_ \
#  nx1076 ni_nires__reg_data2pos_5_ ni_nires__reg_data0pos_5_ \
#  ni_nires__reg_data1pos_5_ ni_nires__reg_data3pos_5_ ni_nires__reg_valid \
#  j2c__ix107 j2c__reg_creg0hm_0_ nx1099 ni_nires__reg_data2pos_6_ \
#  reg_ni_pattcount_2_ ni_nires__reg_data0pos_6_ reg_ni_pattcount_1_ \
#  ni_nires__reg_data1pos_6_ reg_ni_pattcount_0_ j2c__nx330 \
#  ni_nires__reg_data3pos_6_ reg_ni_pattcount_4_ reg_ni_pattcount_3_ \
#  ni_nires__reg_data2pos_7_ ni_nires__reg_data0pos_7_ ni_nires__reg_data1pos_7_ \
#  ni_nires__reg_data3pos_7_ j2c__nx365 ni_nires__reg_data2pos_8_ \
#  ni_nires__reg_data0pos_8_ ni_nires__reg_data1pos_8_ ni_nires__reg_data3pos_8_ \
#  ni_nires__reg_data2pos_9_ ni_nires__reg_data0pos_9_ ni_nires__reg_data1pos_9_ \
#  nx96 ni_nires__reg_data3pos_9_ ni_reg_ce_prty_bit_neg nx148 nx1255 \
#  ni_reg_prty_bit_neg_r nx1263 nx1265 ni_nires__reg_data_out_19_ \
#  ni_nires__reg_data_out_18_ ni_nires__reg_data_out_17_ ni_nires__reg_data_out_16_ \
#  ni_nires__reg_data_out_15_ ni_nires__reg_data_out_14_ ni_nires__reg_data_out_13_ \
#  ni_nires__reg_data_out_12_ ni_nires__reg_data_out_11_ ni_nires__reg_data_out_10_ \
#  ni_nires__reg_data_out_9_ ni_nires__reg_data_out_8_ ni_nires__reg_data_out_7_ \
#  ix449 ni_nires__reg_data_out_6_ nx1309 ni_nires__reg_data_out_5_ \
#  ni_nires__reg_data_out_4_ ni_nires__reg_data_out_3_ ni_nires__reg_data_out_2_ \
#  ni_nires__reg_data_out_1_ ix521 ni_nires__reg_data_out_0_ ix523 nx1325 \
#  ni_nires__reg_data2neg_0_ nx1333 ni_nires__reg_old_cnt_1_ \
#  ni_nires__reg_old_cnt_0_ nx1341 ni_nires__reg_gray_cntf_1_ \
#  ni_nires__reg_gray_cntf_0_ ni_nires__reg_clear_n_i ni_nires__nx1078 \
#  ni_nires__reg_new_cnt_1_ ni_nires__reg_new_cnt_0_ ni_reg_ce_prty_bit_pos \
#  ni_nires__reg_data0neg_0_ ni_reg_prty_bit_pos_r ni_nires__reg_data1neg_0_ \
#  ni_nires__reg_data3neg_0_ ix793 ni_nires__reg_data2neg_1_ \
#  ni_nires__reg_data0neg_1_ ni_nires__reg_data1neg_1_ ni_nires__reg_data3neg_1_ \
#  ix865 ix867 ni_nires__reg_data2neg_2_ ni_nires__reg_data0neg_2_ \
#  ni_nires__reg_data1neg_2_ ni_nires__reg_data3neg_2_ ni_nires__reg_data2neg_3_ \
#  ni_nires__reg_data0neg_3_ ni_nires__reg_data1neg_3_ ni_nires__reg_data3neg_3_
.model top_ni
.inputs NI_D_9_.BLIF NI_STR.BLIF reset_n.BLIF clk.BLIF DIS_JTG.BLIF FAULT.BLIF \
jTCK.BLIF jTDI.BLIF jTMS.BLIF NI_D_8_.BLIF NI_D_7_.BLIF NI_D_6_.BLIF \
NI_D_5_.BLIF NI_D_4_.BLIF NI_D_3_.BLIF NI_D_2_.BLIF NI_D_1_.BLIF NI_D_0_.BLIF \
ni_nires__reg_data2neg_4_.BLIF ni_nires__reg_data0neg_4_.BLIF \
ni_nires__reg_data1neg_4_.BLIF ni_nires__reg_data3neg_4_.BLIF \
ni_nires__reg_data2neg_5_.BLIF ni_nires__reg_data0neg_5_.BLIF \
ni_nires__reg_data1neg_5_.BLIF ni_nires__reg_data3neg_5_.BLIF int_SD2ANL.BLIF \
ni_reg_valid2reg.BLIF reg_TXD_15_reg.BLIF ni_nires__reg_data2neg_6_.BLIF \
reg_TXD_14_reg.BLIF ni_nires__reg_data0neg_6_.BLIF reg_TXD_13_reg.BLIF \
ni_nires__reg_data1neg_6_.BLIF reg_TXD_12_reg.BLIF \
ni_nires__reg_data3neg_6_.BLIF reg_TXD_11_reg.BLIF j2c__reg_creg1hm_2_.BLIF \
reg_TXD_10_reg.BLIF reg_TXD_9_reg.BLIF j2c__reg_shreg_4_.BLIF \
reg_TXD_8_reg.BLIF reg_TXD_7_reg.BLIF j2c__nx0.BLIF reg_TXD_6_reg.BLIF \
j2c__reg_cmdreg_0_.BLIF ni_nires__reg_data2neg_7_.BLIF reg_TXD_5_reg.BLIF \
j2c__reg_shreg_5_.BLIF ni_nires__reg_data0neg_7_.BLIF reg_TXD_4_reg.BLIF \
j2c__reg_shreg_6_.BLIF ni_nires__reg_data1neg_7_.BLIF reg_TXD_3_reg.BLIF \
j2c__reg_shreg_7_.BLIF ni_nires__reg_data3neg_7_.BLIF reg_TXD_2_reg.BLIF \
reg_TXD_1_reg.BLIF j2c__reg_cmdreg_3_.BLIF reg_TXD_0_reg.BLIF j2c__ix59.BLIF \
j2c__ix71.BLIF j2c__reg_creg1hm_6_.BLIF ni_nires__reg_data2neg_8_.BLIF \
j2c__reg_creg1hm_5_.BLIF ni_nires__reg_data0neg_8_.BLIF \
j2c__reg_creg1hm_4_.BLIF ni_nires__reg_data1neg_8_.BLIF \
ni_nires__reg_data3neg_8_.BLIF j2c__reg_creg1hm_3_.BLIF \
j2c__reg_creg1hm_1_.BLIF j2c__ix77.BLIF ni_nires__reg_data2neg_9_.BLIF \
j2c__ix99.BLIF ni_nires__reg_data0neg_9_.BLIF j2c__ix85.BLIF \
ni_nires__reg_data1neg_9_.BLIF ni_nires__reg_data3neg_9_.BLIF \
j2c__reg_creg0hm_3_.BLIF j2c__reg_creg1hm_0_.BLIF j2c__reg_creg0hm_2_.BLIF \
j2c__reg_creg0hm_1_.BLIF reg_ID_0_7_.BLIF j2c__ix45.BLIF reg_ID_0_6_.BLIF \
ni_nires__reg_data2pos_0_.BLIF reg_ID_0_5_.BLIF reg_ID_0_4_.BLIF \
ni_nires__reg_gray_cnt_1_.BLIF reg_ID_0_3_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
reg_ID_0_2_.BLIF reg_ID_0_1_.BLIF nx972.BLIF ni_nires__reg_data0pos_0_.BLIF \
reg_ID_0_0_.BLIF reg_ID_1_6_.BLIF ni_nires__reg_data1pos_0_.BLIF \
reg_ID_1_5_.BLIF j2c__reg_shreg_0_.BLIF reg_ID_1_4_.BLIF \
j2c__reg_shreg_1_.BLIF ni_nires__reg_data3pos_0_.BLIF reg_ID_1_3_.BLIF \
j2c__reg_shreg_2_.BLIF reg_ID_1_2_.BLIF j2c__reg_shreg_3_.BLIF \
reg_ID_1_1_.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_1_0_.BLIF nx988.BLIF \
reg_ID_2_6_.BLIF nx990.BLIF reg_ID_2_5_.BLIF reg_ID_2_4_.BLIF \
ni_nires__reg_data2pos_1_.BLIF reg_ID_2_3_.BLIF ni_nires__reg_data0pos_1_.BLIF \
reg_ID_2_2_.BLIF j2c__bitcnt_0_.BLIF ni_nires__reg_data1pos_1_.BLIF \
reg_ID_2_1_.BLIF ni_nires__reg_data3pos_1_.BLIF reg_ID_2_0_.BLIF \
j2c__bitcnt_1_.BLIF reg_ID_3_6_.BLIF reg_ID_3_5_.BLIF j2c__bitcnt_2_.BLIF \
reg_ID_3_4_.BLIF reg_ID_3_3_.BLIF ni_nires__reg_data2pos_2_.BLIF \
reg_ID_3_2_.BLIF ni_nires__reg_data0pos_2_.BLIF reg_ID_3_1_.BLIF \
ni_nires__reg_data1pos_2_.BLIF reg_ID_3_0_.BLIF j2c__reg_cmdreg_2_.BLIF \
ni_nires__reg_data3pos_2_.BLIF testpatt.BLIF j2c__reg_cmdreg_1_.BLIF nx12.BLIF \
nx1039.BLIF j2c__nx414.BLIF nx20.BLIF ni_nires__reg_data2pos_3_.BLIF \
ni_nires__reg_data0pos_3_.BLIF nx197.BLIF ni_nires__reg_data1pos_3_.BLIF \
ni_nires__reg_data3pos_3_.BLIF nx1052.BLIF nx1059.BLIF \
ni_nires__reg_data2pos_4_.BLIF ni_nires__reg_data0pos_4_.BLIF \
ni_nires__reg_data1pos_4_.BLIF ni_nires__reg_data3pos_4_.BLIF nx1076.BLIF \
ni_nires__reg_data2pos_5_.BLIF ni_nires__reg_data0pos_5_.BLIF \
ni_nires__reg_data1pos_5_.BLIF ni_nires__reg_data3pos_5_.BLIF \
ni_nires__reg_valid.BLIF j2c__ix107.BLIF j2c__reg_creg0hm_0_.BLIF nx1099.BLIF \
ni_nires__reg_data2pos_6_.BLIF reg_ni_pattcount_2_.BLIF \
ni_nires__reg_data0pos_6_.BLIF reg_ni_pattcount_1_.BLIF \
ni_nires__reg_data1pos_6_.BLIF reg_ni_pattcount_0_.BLIF j2c__nx330.BLIF \
ni_nires__reg_data3pos_6_.BLIF reg_ni_pattcount_4_.BLIF \
reg_ni_pattcount_3_.BLIF ni_nires__reg_data2pos_7_.BLIF \
ni_nires__reg_data0pos_7_.BLIF ni_nires__reg_data1pos_7_.BLIF \
ni_nires__reg_data3pos_7_.BLIF j2c__nx365.BLIF ni_nires__reg_data2pos_8_.BLIF \
ni_nires__reg_data0pos_8_.BLIF ni_nires__reg_data1pos_8_.BLIF \
ni_nires__reg_data3pos_8_.BLIF ni_nires__reg_data2pos_9_.BLIF \
ni_nires__reg_data0pos_9_.BLIF ni_nires__reg_data1pos_9_.BLIF nx96.BLIF \
ni_nires__reg_data3pos_9_.BLIF ni_reg_ce_prty_bit_neg.BLIF nx148.BLIF \
nx1255.BLIF ni_reg_prty_bit_neg_r.BLIF nx1263.BLIF nx1265.BLIF \
ni_nires__reg_data_out_19_.BLIF ni_nires__reg_data_out_18_.BLIF \
ni_nires__reg_data_out_17_.BLIF ni_nires__reg_data_out_16_.BLIF \
ni_nires__reg_data_out_15_.BLIF ni_nires__reg_data_out_14_.BLIF \
ni_nires__reg_data_out_13_.BLIF ni_nires__reg_data_out_12_.BLIF \
ni_nires__reg_data_out_11_.BLIF ni_nires__reg_data_out_10_.BLIF \
ni_nires__reg_data_out_9_.BLIF ni_nires__reg_data_out_8_.BLIF \
ni_nires__reg_data_out_7_.BLIF ix449.BLIF ni_nires__reg_data_out_6_.BLIF \
nx1309.BLIF ni_nires__reg_data_out_5_.BLIF ni_nires__reg_data_out_4_.BLIF \
ni_nires__reg_data_out_3_.BLIF ni_nires__reg_data_out_2_.BLIF \
ni_nires__reg_data_out_1_.BLIF ix521.BLIF ni_nires__reg_data_out_0_.BLIF \
ix523.BLIF nx1325.BLIF ni_nires__reg_data2neg_0_.BLIF nx1333.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF nx1341.BLIF \
ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_clear_n_i.BLIF ni_nires__nx1078.BLIF \
ni_nires__reg_new_cnt_1_.BLIF ni_nires__reg_new_cnt_0_.BLIF \
ni_reg_ce_prty_bit_pos.BLIF ni_nires__reg_data0neg_0_.BLIF \
ni_reg_prty_bit_pos_r.BLIF ni_nires__reg_data1neg_0_.BLIF \
ni_nires__reg_data3neg_0_.BLIF ix793.BLIF ni_nires__reg_data2neg_1_.BLIF \
ni_nires__reg_data0neg_1_.BLIF ni_nires__reg_data1neg_1_.BLIF \
ni_nires__reg_data3neg_1_.BLIF ix865.BLIF ix867.BLIF \
ni_nires__reg_data2neg_2_.BLIF ni_nires__reg_data0neg_2_.BLIF \
ni_nires__reg_data1neg_2_.BLIF ni_nires__reg_data3neg_2_.BLIF \
ni_nires__reg_data2neg_3_.BLIF ni_nires__reg_data0neg_3_.BLIF \
ni_nires__reg_data1neg_3_.BLIF ni_nires__reg_data3neg_3_.BLIF SDA.PIN.BLIF
.outputs TESTEN PRBSEN LCKREFN ENABLE LOOPEN TX_ER TX_EN TXD_15_ EN SD2ANL \
WP_EEP SCL TXD_14_ TXD_13_ TXD_12_ TXD_11_ TXD_10_ TXD_9_ TXD_8_ TXD_7_ TXD_6_ \
TXD_5_ TXD_4_ TXD_3_ TXD_2_ TXD_1_ TXD_0_ ni_nires__reg_data3pos_0_.D \
ni_nires__reg_data3pos_0_.CE ni_nires__reg_data3pos_0_.C j2c__reg_creg0hm_0_.D \
j2c__reg_creg0hm_0_.CE j2c__reg_creg0hm_0_.C j2c__reg_creg0hm_0_.AR \
reg_ID_3_6_.CE reg_ID_3_6_.C reg_ID_3_6_.AR j2c__reg_shreg_0_.D \
j2c__reg_shreg_0_.C ni_nires__reg_data_out_11_.D ni_nires__reg_data_out_11_.C \
j2c__reg_shreg_1_.D j2c__reg_shreg_1_.C j2c__reg_shreg_2_.D \
j2c__reg_shreg_2_.C reg_ID_3_1_.D reg_ID_3_1_.CE reg_ID_3_1_.C reg_ID_3_1_.AR \
j2c__reg_shreg_3_.D j2c__reg_shreg_3_.C ni_nires__reg_data2pos_1_.D \
ni_nires__reg_data2pos_1_.CE ni_nires__reg_data2pos_1_.C j2c__reg_creg0hm_1_.D \
j2c__reg_creg0hm_1_.CE j2c__reg_creg0hm_1_.C j2c__reg_creg0hm_1_.AR \
reg_ID_3_2_.D reg_ID_3_2_.CE reg_ID_3_2_.C reg_ID_3_2_.AR \
j2c__reg_creg0hm_2_.D j2c__reg_creg0hm_2_.CE j2c__reg_creg0hm_2_.C \
j2c__reg_creg0hm_2_.AR ni_nires__reg_data0pos_1_.D \
ni_nires__reg_data0pos_1_.CE ni_nires__reg_data0pos_1_.C j2c__reg_creg0hm_3_.D \
j2c__reg_creg0hm_3_.CE j2c__reg_creg0hm_3_.C j2c__reg_creg0hm_3_.AP \
ni_nires__reg_data1pos_1_.D ni_nires__reg_data1pos_1_.CE \
ni_nires__reg_data1pos_1_.C reg_ID_3_3_.D reg_ID_3_3_.CE reg_ID_3_3_.C \
reg_ID_3_3_.AR j2c__reg_rstout_n_i.D j2c__reg_rstout_n_i.CE \
j2c__reg_rstout_n_i.C j2c__reg_rstout_n_i.AP ni_nires__reg_data3pos_1_.D \
ni_nires__reg_data3pos_1_.CE ni_nires__reg_data3pos_1_.C \
ni_nires__reg_data_out_12_.D ni_nires__reg_data_out_12_.C reg_ID_3_4_.CE \
reg_ID_3_4_.C reg_ID_3_4_.AR j2c__bitcnt_1_.D j2c__bitcnt_1_.C \
j2c__bitcnt_1_.AR ni_nires__reg_data2pos_2_.D ni_nires__reg_data2pos_2_.CE \
ni_nires__reg_data2pos_2_.C reg_ID_3_5_.CE reg_ID_3_5_.C reg_ID_3_5_.AR \
j2c__bitcnt_0_.D j2c__bitcnt_0_.C j2c__bitcnt_0_.AR \
ni_nires__reg_data0pos_2_.D ni_nires__reg_data0pos_2_.CE \
ni_nires__reg_data0pos_2_.C ni_nires__reg_data1pos_2_.D \
ni_nires__reg_data1pos_2_.CE ni_nires__reg_data1pos_2_.C reg_ID_2_0_.D \
reg_ID_2_0_.CE reg_ID_2_0_.C reg_ID_2_0_.AR j2c__bitcnt_2_.D j2c__bitcnt_2_.C \
j2c__bitcnt_2_.AR ni_nires__reg_data3pos_2_.D ni_nires__reg_data3pos_2_.CE \
ni_nires__reg_data3pos_2_.C ni_reg_ce_prty_bit_neg.C \
ni_nires__reg_data_out_13_.D ni_nires__reg_data_out_13_.C reg_TXD_8_reg.D \
reg_TXD_8_reg.CE reg_TXD_8_reg.C reg_TXD_8_reg.AP ni_nires__reg_data2pos_3_.D \
ni_nires__reg_data2pos_3_.CE ni_nires__reg_data2pos_3_.C j2c__reg_cmdreg_2_.D \
j2c__reg_cmdreg_2_.CE j2c__reg_cmdreg_2_.C j2c__reg_cmdreg_2_.AP \
ni_nires__reg_data0pos_3_.D ni_nires__reg_data0pos_3_.CE \
ni_nires__reg_data0pos_3_.C ni_nires__reg_data1pos_3_.D \
ni_nires__reg_data1pos_3_.CE ni_nires__reg_data1pos_3_.C j2c__reg_cmdreg_1_.D \
j2c__reg_cmdreg_1_.CE j2c__reg_cmdreg_1_.C j2c__reg_cmdreg_1_.AP \
ni_nires__reg_data3pos_3_.D ni_nires__reg_data3pos_3_.CE \
ni_nires__reg_data3pos_3_.C ni_nires__reg_data_out_14_.D \
ni_nires__reg_data_out_14_.C ni_nires__reg_data2pos_4_.D \
ni_nires__reg_data2pos_4_.CE ni_nires__reg_data2pos_4_.C \
ni_nires__reg_data0pos_4_.D ni_nires__reg_data0pos_4_.CE \
ni_nires__reg_data0pos_4_.C ni_nires__reg_data1pos_4_.D \
ni_nires__reg_data1pos_4_.CE ni_nires__reg_data1pos_4_.C \
ni_nires__reg_data3pos_4_.D ni_nires__reg_data3pos_4_.CE \
ni_nires__reg_data3pos_4_.C ni_nires__reg_data_out_15_.D \
ni_nires__reg_data_out_15_.C ni_reg_prty_bit_neg_r.D ni_reg_prty_bit_neg_r.C \
ni_nires__reg_data2pos_5_.D ni_nires__reg_data2pos_5_.CE \
ni_nires__reg_data2pos_5_.C ni_nires__reg_data0pos_5_.D \
ni_nires__reg_data0pos_5_.CE ni_nires__reg_data0pos_5_.C \
ni_nires__reg_data1pos_5_.D ni_nires__reg_data1pos_5_.CE \
ni_nires__reg_data1pos_5_.C ni_nires__reg_data3pos_5_.D \
ni_nires__reg_data3pos_5_.CE ni_nires__reg_data3pos_5_.C \
ni_nires__reg_data_out_16_.D ni_nires__reg_data_out_16_.C \
ni_nires__reg_data2pos_6_.D ni_nires__reg_data2pos_6_.CE \
ni_nires__reg_data2pos_6_.C ni_nires__reg_data0pos_6_.D \
ni_nires__reg_data0pos_6_.CE ni_nires__reg_data0pos_6_.C \
ni_nires__reg_data1pos_6_.D ni_nires__reg_data1pos_6_.CE \
ni_nires__reg_data1pos_6_.C ni_nires__reg_data3pos_6_.D \
ni_nires__reg_data3pos_6_.CE ni_nires__reg_data3pos_6_.C \
ni_nires__reg_data_out_17_.D ni_nires__reg_data_out_17_.C \
ni_nires__reg_data2pos_7_.D ni_nires__reg_data2pos_7_.CE \
ni_nires__reg_data2pos_7_.C ni_nires__reg_data0pos_7_.D \
ni_nires__reg_data0pos_7_.CE ni_nires__reg_data0pos_7_.C \
ni_nires__reg_data1pos_7_.D ni_nires__reg_data1pos_7_.CE \
ni_nires__reg_data1pos_7_.C ni_nires__reg_data3pos_7_.D \
ni_nires__reg_data3pos_7_.CE ni_nires__reg_data3pos_7_.C \
ni_nires__reg_data_out_18_.D ni_nires__reg_data_out_18_.C \
ni_nires__reg_data2pos_8_.D ni_nires__reg_data2pos_8_.CE \
ni_nires__reg_data2pos_8_.C ni_nires__reg_data0pos_8_.D \
ni_nires__reg_data0pos_8_.CE ni_nires__reg_data0pos_8_.C reg_TXD_15_reg.CE \
reg_TXD_15_reg.C reg_TXD_15_reg.AR ni_nires__reg_data1pos_8_.D \
ni_nires__reg_data1pos_8_.CE ni_nires__reg_data1pos_8_.C \
ni_nires__reg_data3pos_8_.D ni_nires__reg_data3pos_8_.CE \
ni_nires__reg_data3pos_8_.C ni_nires__reg_data_out_19_.D \
ni_nires__reg_data_out_19_.C reg_ID_3_0_.D reg_ID_3_0_.CE reg_ID_3_0_.C \
reg_ID_3_0_.AR ni_nires__reg_data2pos_9_.D ni_nires__reg_data2pos_9_.CE \
ni_nires__reg_data2pos_9_.C reg_TXD_12_reg.D reg_TXD_12_reg.CE \
reg_TXD_12_reg.C reg_TXD_12_reg.AR ni_reg_ce_prty_bit_pos.D \
ni_reg_ce_prty_bit_pos.C ni_nires__reg_data0pos_9_.D \
ni_nires__reg_data0pos_9_.CE ni_nires__reg_data0pos_9_.C \
ni_nires__reg_data1pos_9_.D ni_nires__reg_data1pos_9_.CE \
ni_nires__reg_data1pos_9_.C reg_TXD_0_reg.D reg_TXD_0_reg.CE reg_TXD_0_reg.C \
reg_TXD_0_reg.AR reg_TXD_13_reg.D reg_TXD_13_reg.CE reg_TXD_13_reg.C \
reg_TXD_13_reg.AR ni_nires__reg_data3pos_9_.D ni_nires__reg_data3pos_9_.CE \
ni_nires__reg_data3pos_9_.C ni_nires__reg_valid.D ni_nires__reg_valid.C \
ni_reg_valid2reg.D ni_reg_valid2reg.C reg_TXD_14_reg.D reg_TXD_14_reg.CE \
reg_TXD_14_reg.C reg_TXD_14_reg.AR reg_ni_pattcount_0_.D reg_ni_pattcount_0_.C \
reg_ni_pattcount_1_.D reg_ni_pattcount_1_.C reg_ni_pattcount_3_.D \
reg_ni_pattcount_3_.C reg_ni_pattcount_2_.D reg_ni_pattcount_2_.C \
reg_TXD_11_reg.CE reg_TXD_11_reg.C reg_TXD_11_reg.AP reg_ni_pattcount_4_.C \
reg_TXD_10_reg.CE reg_TXD_10_reg.C reg_TXD_10_reg.AP \
ni_nires__reg_data_out_0_.D ni_nires__reg_data_out_0_.C reg_TXD_9_reg.D \
reg_TXD_9_reg.CE reg_TXD_9_reg.C reg_TXD_9_reg.AP ni_nires__reg_data2neg_0_.D \
ni_nires__reg_data2neg_0_.CE ni_nires__reg_data2neg_0_.C \
ni_nires__reg_gray_cntf_1_.D ni_nires__reg_gray_cntf_1_.C \
ni_nires__reg_gray_cntf_1_.AR ni_nires__reg_gray_cntf_0_.D \
ni_nires__reg_gray_cntf_0_.C ni_nires__reg_gray_cntf_0_.AR \
ni_nires__reg_clear_n_i.D ni_nires__reg_clear_n_i.C ni_nires__reg_old_cnt_1_.D \
ni_nires__reg_old_cnt_1_.CE ni_nires__reg_old_cnt_1_.C \
ni_nires__reg_old_cnt_1_.AR reg_ID_2_6_.CE reg_ID_2_6_.C reg_ID_2_6_.AR \
ni_nires__reg_new_cnt_1_.D ni_nires__reg_new_cnt_1_.C \
ni_nires__reg_new_cnt_1_.AR reg_ID_2_1_.D reg_ID_2_1_.CE reg_ID_2_1_.C \
reg_ID_2_1_.AR ni_nires__reg_old_cnt_0_.D ni_nires__reg_old_cnt_0_.CE \
ni_nires__reg_old_cnt_0_.C ni_nires__reg_old_cnt_0_.AR ni_reg_prty_bit_pos_r.D \
ni_reg_prty_bit_pos_r.C reg_ID_2_2_.D reg_ID_2_2_.CE reg_ID_2_2_.C \
reg_ID_2_2_.AR ni_nires__reg_new_cnt_0_.D ni_nires__reg_new_cnt_0_.C \
ni_nires__reg_new_cnt_0_.AR ni_nires__reg_data0neg_0_.D \
ni_nires__reg_data0neg_0_.CE ni_nires__reg_data0neg_0_.C reg_ID_2_3_.D \
reg_ID_2_3_.CE reg_ID_2_3_.C reg_ID_2_3_.AR reg_ID_2_4_.CE reg_ID_2_4_.C \
reg_ID_2_4_.AR ni_nires__reg_data1neg_0_.D ni_nires__reg_data1neg_0_.CE \
ni_nires__reg_data1neg_0_.C reg_ID_2_5_.CE reg_ID_2_5_.C reg_ID_2_5_.AR \
ni_nires__reg_data3neg_0_.D ni_nires__reg_data3neg_0_.CE \
ni_nires__reg_data3neg_0_.C ni_nires__reg_data_out_1_.D \
ni_nires__reg_data_out_1_.C reg_ID_1_0_.D reg_ID_1_0_.CE reg_ID_1_0_.C \
reg_ID_1_0_.AR ni_nires__reg_data2neg_1_.D ni_nires__reg_data2neg_1_.CE \
ni_nires__reg_data2neg_1_.C reg_ID_0_0_.D reg_ID_0_0_.CE reg_ID_0_0_.C \
reg_ID_0_0_.AR ni_nires__reg_data0neg_1_.D ni_nires__reg_data0neg_1_.CE \
ni_nires__reg_data0neg_1_.C reg_ID_0_1_.D reg_ID_0_1_.CE reg_ID_0_1_.C \
reg_ID_0_1_.AR ni_nires__reg_data1neg_1_.D ni_nires__reg_data1neg_1_.CE \
ni_nires__reg_data1neg_1_.C reg_ID_0_2_.D reg_ID_0_2_.CE reg_ID_0_2_.C \
reg_ID_0_2_.AR ni_nires__reg_data3neg_1_.D ni_nires__reg_data3neg_1_.CE \
ni_nires__reg_data3neg_1_.C ni_nires__reg_data_out_2_.D \
ni_nires__reg_data_out_2_.C reg_ID_0_3_.D reg_ID_0_3_.CE reg_ID_0_3_.C \
reg_ID_0_3_.AR ni_nires__reg_data2neg_2_.D ni_nires__reg_data2neg_2_.CE \
ni_nires__reg_data2neg_2_.C reg_ID_0_4_.CE reg_ID_0_4_.C reg_ID_0_4_.AR \
ni_nires__reg_data0neg_2_.D ni_nires__reg_data0neg_2_.CE \
ni_nires__reg_data0neg_2_.C reg_ID_0_5_.CE reg_ID_0_5_.C reg_ID_0_5_.AR \
ni_nires__reg_data1neg_2_.D ni_nires__reg_data1neg_2_.CE \
ni_nires__reg_data1neg_2_.C ni_nires__reg_data3neg_2_.D \
ni_nires__reg_data3neg_2_.CE ni_nires__reg_data3neg_2_.C reg_ID_0_6_.CE \
reg_ID_0_6_.C reg_ID_0_6_.AR ni_nires__reg_data_out_3_.D \
ni_nires__reg_data_out_3_.C reg_ID_0_7_.CE reg_ID_0_7_.C reg_ID_0_7_.AR \
ni_nires__reg_data2neg_3_.D ni_nires__reg_data2neg_3_.CE \
ni_nires__reg_data2neg_3_.C ni_nires__reg_data0neg_3_.D \
ni_nires__reg_data0neg_3_.CE ni_nires__reg_data0neg_3_.C reg_ID_1_1_.D \
reg_ID_1_1_.CE reg_ID_1_1_.C reg_ID_1_1_.AR ni_nires__reg_data1neg_3_.D \
ni_nires__reg_data1neg_3_.CE ni_nires__reg_data1neg_3_.C reg_ID_1_2_.D \
reg_ID_1_2_.CE reg_ID_1_2_.C reg_ID_1_2_.AR ni_nires__reg_data3neg_3_.D \
ni_nires__reg_data3neg_3_.CE ni_nires__reg_data3neg_3_.C \
ni_nires__reg_data_out_4_.D ni_nires__reg_data_out_4_.C reg_ID_1_3_.CE \
reg_ID_1_3_.C reg_ID_1_3_.AR ni_nires__reg_data2neg_4_.D \
ni_nires__reg_data2neg_4_.CE ni_nires__reg_data2neg_4_.C reg_ID_1_4_.CE \
reg_ID_1_4_.C reg_ID_1_4_.AR ni_nires__reg_data0neg_4_.D \
ni_nires__reg_data0neg_4_.CE ni_nires__reg_data0neg_4_.C \
ni_nires__reg_data1neg_4_.D ni_nires__reg_data1neg_4_.CE \
ni_nires__reg_data1neg_4_.C reg_ID_1_5_.CE reg_ID_1_5_.C reg_ID_1_5_.AR \
ni_nires__reg_data3neg_4_.D ni_nires__reg_data3neg_4_.CE \
ni_nires__reg_data3neg_4_.C reg_TXD_7_reg.CE reg_TXD_7_reg.C reg_TXD_7_reg.AP \
ni_nires__reg_data_out_5_.D ni_nires__reg_data_out_5_.C reg_ID_1_6_.CE \
reg_ID_1_6_.C reg_ID_1_6_.AR ni_nires__reg_data2neg_5_.D \
ni_nires__reg_data2neg_5_.CE ni_nires__reg_data2neg_5_.C \
ni_nires__reg_data0neg_5_.D ni_nires__reg_data0neg_5_.CE \
ni_nires__reg_data0neg_5_.C reg_TXD_6_reg.D reg_TXD_6_reg.CE reg_TXD_6_reg.C \
reg_TXD_6_reg.AP ni_nires__reg_data1neg_5_.D ni_nires__reg_data1neg_5_.CE \
ni_nires__reg_data1neg_5_.C ni_nires__reg_data3neg_5_.D \
ni_nires__reg_data3neg_5_.CE ni_nires__reg_data3neg_5_.C \
ni_nires__reg_data_out_6_.D ni_nires__reg_data_out_6_.C \
ni_nires__reg_data2neg_6_.D ni_nires__reg_data2neg_6_.CE \
ni_nires__reg_data2neg_6_.C ni_nires__reg_data0neg_6_.D \
ni_nires__reg_data0neg_6_.CE ni_nires__reg_data0neg_6_.C reg_TXD_5_reg.D \
reg_TXD_5_reg.CE reg_TXD_5_reg.C reg_TXD_5_reg.AP ni_nires__reg_data1neg_6_.D \
ni_nires__reg_data1neg_6_.CE ni_nires__reg_data1neg_6_.C \
ni_nires__reg_data3neg_6_.D ni_nires__reg_data3neg_6_.CE \
ni_nires__reg_data3neg_6_.C ni_nires__reg_data_out_7_.D \
ni_nires__reg_data_out_7_.C reg_TXD_4_reg.D reg_TXD_4_reg.CE reg_TXD_4_reg.C \
reg_TXD_4_reg.AP ni_nires__reg_data2neg_7_.D ni_nires__reg_data2neg_7_.CE \
ni_nires__reg_data2neg_7_.C ni_nires__reg_data0neg_7_.D \
ni_nires__reg_data0neg_7_.CE ni_nires__reg_data0neg_7_.C j2c__reg_creg1hm_2_.D \
j2c__reg_creg1hm_2_.CE j2c__reg_creg1hm_2_.C j2c__reg_creg1hm_2_.AP \
ni_nires__reg_data1neg_7_.D ni_nires__reg_data1neg_7_.CE \
ni_nires__reg_data1neg_7_.C j2c__reg_cmdreg_0_.D j2c__reg_cmdreg_0_.CE \
j2c__reg_cmdreg_0_.C j2c__reg_cmdreg_0_.AP j2c__reg_shreg_4_.D \
j2c__reg_shreg_4_.C ni_nires__reg_data3neg_7_.D ni_nires__reg_data3neg_7_.CE \
ni_nires__reg_data3neg_7_.C j2c__reg_shreg_5_.D j2c__reg_shreg_5_.C \
ni_nires__reg_data_out_8_.D ni_nires__reg_data_out_8_.C j2c__reg_shreg_6_.D \
j2c__reg_shreg_6_.C j2c__reg_shreg_7_.D j2c__reg_shreg_7_.C \
ni_nires__reg_data2neg_8_.D ni_nires__reg_data2neg_8_.CE \
ni_nires__reg_data2neg_8_.C j2c__reg_cmdreg_3_.D j2c__reg_cmdreg_3_.C \
j2c__reg_cmdreg_3_.AR ni_nires__reg_data0neg_8_.D ni_nires__reg_data0neg_8_.CE \
ni_nires__reg_data0neg_8_.C j2c__reg_creg1hm_6_.D j2c__reg_creg1hm_6_.CE \
j2c__reg_creg1hm_6_.C j2c__reg_creg1hm_6_.AP ni_nires__reg_data1neg_8_.D \
ni_nires__reg_data1neg_8_.CE ni_nires__reg_data1neg_8_.C j2c__reg_creg1hm_5_.D \
j2c__reg_creg1hm_5_.CE j2c__reg_creg1hm_5_.C j2c__reg_creg1hm_5_.AR \
j2c__reg_creg1hm_4_.D j2c__reg_creg1hm_4_.CE j2c__reg_creg1hm_4_.C \
j2c__reg_creg1hm_4_.AR ni_nires__reg_data3neg_8_.D \
ni_nires__reg_data3neg_8_.CE ni_nires__reg_data3neg_8_.C j2c__reg_creg1hm_3_.D \
j2c__reg_creg1hm_3_.CE j2c__reg_creg1hm_3_.C j2c__reg_creg1hm_3_.AP \
ni_nires__reg_data_out_9_.D ni_nires__reg_data_out_9_.C reg_TXD_3_reg.CE \
reg_TXD_3_reg.C reg_TXD_3_reg.AR ni_nires__reg_data2neg_9_.D \
ni_nires__reg_data2neg_9_.CE ni_nires__reg_data2neg_9_.C \
ni_nires__reg_data0neg_9_.D ni_nires__reg_data0neg_9_.CE \
ni_nires__reg_data0neg_9_.C j2c__reg_creg1hm_1_.D j2c__reg_creg1hm_1_.CE \
j2c__reg_creg1hm_1_.C j2c__reg_creg1hm_1_.AR ni_nires__reg_data1neg_9_.D \
ni_nires__reg_data1neg_9_.CE ni_nires__reg_data1neg_9_.C reg_TXD_1_reg.D \
reg_TXD_1_reg.CE reg_TXD_1_reg.C reg_TXD_1_reg.AR ni_nires__reg_data3neg_9_.D \
ni_nires__reg_data3neg_9_.CE ni_nires__reg_data3neg_9_.C \
ni_nires__reg_data_out_10_.D ni_nires__reg_data_out_10_.C \
j2c__reg_creg1hm_0_.D j2c__reg_creg1hm_0_.CE j2c__reg_creg1hm_0_.C \
j2c__reg_creg1hm_0_.AR ni_nires__reg_data2pos_0_.D \
ni_nires__reg_data2pos_0_.CE ni_nires__reg_data2pos_0_.C \
ni_nires__reg_gray_cnt_1_.D ni_nires__reg_gray_cnt_1_.C \
ni_nires__reg_gray_cnt_1_.AR ni_nires__reg_gray_cnt_0_.D \
ni_nires__reg_gray_cnt_0_.C ni_nires__reg_gray_cnt_0_.AR reg_TXD_2_reg.CE \
reg_TXD_2_reg.C reg_TXD_2_reg.AR ni_nires__reg_data0pos_0_.D \
ni_nires__reg_data0pos_0_.CE ni_nires__reg_data0pos_0_.C \
ni_nires__reg_data1pos_0_.D ni_nires__reg_data1pos_0_.CE \
ni_nires__reg_data1pos_0_.C SDA int_SD2ANL j2c__nx0 nx972 nx988 nx990 testpatt \
nx12 nx1039 j2c__nx414 nx20 nx197 nx1052 nx1059 nx1076 nx1099 j2c__nx330 \
j2c__nx365 nx96 nx148 nx1255 nx1263 nx1265 nx1309 nx1325 nx1333 nx1341 \
ni_nires__nx1078 SDA.OE SCL.OE jTDO.OE j2c__ix77 j2c__ix99 j2c__ix85 \
j2c__ix107 ix521 ix523 ix793 jTDO.X1 jTDO.X2 reg_TXD_15_reg.D.X1 \
reg_TXD_15_reg.D.X2 reg_TXD_11_reg.D.X1 reg_TXD_11_reg.D.X2 \
reg_TXD_10_reg.D.X1 reg_TXD_10_reg.D.X2 reg_TXD_7_reg.D.X1 reg_TXD_7_reg.D.X2 \
reg_TXD_3_reg.D.X1 reg_TXD_3_reg.D.X2 reg_TXD_2_reg.D.X1 reg_TXD_2_reg.D.X2 \
j2c__ix59.X1 j2c__ix59.X2 j2c__ix71.X1 j2c__ix71.X2 reg_ID_0_7_.D.X1 \
reg_ID_0_7_.D.X2 j2c__ix45.X1 j2c__ix45.X2 reg_ID_0_6_.D.X1 reg_ID_0_6_.D.X2 \
reg_ID_0_5_.D.X1 reg_ID_0_5_.D.X2 reg_ID_0_4_.D.X1 reg_ID_0_4_.D.X2 \
reg_ID_1_6_.D.X1 reg_ID_1_6_.D.X2 reg_ID_1_5_.D.X1 reg_ID_1_5_.D.X2 \
reg_ID_1_4_.D.X1 reg_ID_1_4_.D.X2 reg_ID_1_3_.D.X1 reg_ID_1_3_.D.X2 \
reg_ID_2_6_.D.X1 reg_ID_2_6_.D.X2 reg_ID_2_5_.D.X1 reg_ID_2_5_.D.X2 \
reg_ID_2_4_.D.X1 reg_ID_2_4_.D.X2 reg_ID_3_6_.D.X1 reg_ID_3_6_.D.X2 \
reg_ID_3_5_.D.X1 reg_ID_3_5_.D.X2 reg_ID_3_4_.D.X1 reg_ID_3_4_.D.X2 \
reg_ni_pattcount_4_.D.X1 reg_ni_pattcount_4_.D.X2 ni_reg_ce_prty_bit_neg.D.X1 \
ni_reg_ce_prty_bit_neg.D.X2 ix449.X1 ix449.X2 ix865.X1 ix865.X2 ix867.X1 \
ix867.X2
.names reset_n.BLIF j2c__reg_creg0hm_0_.AR
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.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_3_6_.AR
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.names ni_nires__reg_data2pos_1_.BLIF ni_nires__reg_data0pos_1_.BLIF \
ni_nires__reg_data1pos_1_.BLIF ni_nires__reg_data3pos_1_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_11_.D
-1--00 1
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--1-01 1
1---11 1
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---010 0
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.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_3_1_.AR
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.names reset_n.BLIF j2c__reg_creg0hm_1_.AR
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.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_3_2_.AR
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.names reset_n.BLIF j2c__reg_creg0hm_2_.AR
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.names reset_n.BLIF j2c__reg_creg0hm_3_.AP
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.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_3_3_.AR
0- 1
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.names j2c__bitcnt_2_.BLIF j2c__bitcnt_1_.BLIF j2c__bitcnt_0_.BLIF \
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111 1
-0- 0
0-- 0
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.names j2c__reg_cmdreg_3_.BLIF j2c__bitcnt_0_.BLIF j2c__bitcnt_1_.BLIF \
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1100 1
-111 1
0-0- 0
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.names j2c__nx0.BLIF j2c__reg_rstout_n_i.AP
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.names ni_nires__reg_data2pos_2_.BLIF ni_nires__reg_data0pos_2_.BLIF \
ni_nires__reg_data1pos_2_.BLIF ni_nires__reg_data3pos_2_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_12_.D
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---110 1
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1---11 1
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.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_3_4_.AR
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.names j2c__nx0.BLIF j2c__bitcnt_1_.AR
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.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_3_5_.AR
0- 1
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.names j2c__nx0.BLIF j2c__bitcnt_0_.AR
0 1
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.names reg_ID_2_0_.BLIF reg_ID_2_0_.D
0 1
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.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_2_0_.AR
0- 1
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.names j2c__nx0.BLIF j2c__bitcnt_2_.AR
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.names ni_nires__reg_data2pos_3_.BLIF ni_nires__reg_data0pos_3_.BLIF \
ni_nires__reg_data1pos_3_.BLIF ni_nires__reg_data3pos_3_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_13_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names int_SD2ANL.BLIF reg_TXD_8_reg.BLIF j2c__ix77.BLIF j2c__ix99.BLIF \
j2c__ix85.BLIF j2c__reg_creg0hm_3_.BLIF j2c__reg_creg0hm_2_.BLIF \
j2c__reg_creg0hm_1_.BLIF testpatt.BLIF j2c__ix107.BLIF \
j2c__reg_creg0hm_0_.BLIF nx1255.BLIF nx1263.BLIF \
ni_nires__reg_data_out_10_.BLIF reg_TXD_8_reg.D
10------1----- 1
1-------0-10-- 1
1------10--0-- 1
1-----1-0--0-- 1
1----1--0--0-- 1
1-------011--1 1
1---1---0-1--1 1
1--1----0-1--1 1
1-1-----0-1--1 1
1------101---1 1
1-----1-01---1 1
1----1--01---1 1
1---1--10----1 1
1--1---10----1 1
1-1----10----1 1
1---1-1-0----1 1
1--1--1-0----1 1
1-1---1-0----1 1
1---11--0----1 1
1--1-1--0----1 1
1-1--1--0----1 1
------------0- 1
--000---00-11- 0
-----0000-0-1- 0
-1------1---1- 0
--------0--110 0
0-----------1- 0
.names reset_n.BLIF reg_TXD_8_reg.AP
0 1
1 0
.names reset_n.BLIF j2c__reg_cmdreg_2_.AP
0 1
1 0
.names reset_n.BLIF j2c__reg_cmdreg_1_.AP
0 1
1 0
.names ni_nires__reg_data2pos_4_.BLIF ni_nires__reg_data0pos_4_.BLIF \
ni_nires__reg_data1pos_4_.BLIF ni_nires__reg_data3pos_4_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_14_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names ni_nires__reg_data2pos_5_.BLIF ni_nires__reg_data0pos_5_.BLIF \
ni_nires__reg_data1pos_5_.BLIF ni_nires__reg_data3pos_5_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_15_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__reg_creg0hm_3_.BLIF \
j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF nx1039.BLIF j2c__ix107.BLIF \
j2c__reg_creg0hm_0_.BLIF nx1255.BLIF nx1265.BLIF \
ni_nires__reg_data_out_18_.BLIF ni_nires__reg_data_out_17_.BLIF \
ni_nires__reg_data_out_14_.BLIF ni_nires__reg_data_out_13_.BLIF \
ni_nires__reg_data_out_12_.BLIF ni_nires__reg_data_out_10_.BLIF nx1309.BLIF \
nx1325.BLIF nx1333.BLIF nx1341.BLIF ni_reg_prty_bit_neg_r.D
00-001--1----1------- 1
0--011--1--1--------- 1
1--011--1---1-------- 1
---0010-0------1----- 1
-1-001--1-----1------ 1
---0011-0-----1------ 1
1--001--1-----1------ 1
---000-10-------1---- 1
--1000--0-------1---- 1
-1-000--0-------1---- 1
1--000--0-------1---- 1
---010--1----------0- 1
---011--0---------0-- 1
---010--0--------0--- 1
---000--1-0---------- 1
---000--00----------- 1
---1----------------0 1
000000-001----------- 0
00-001--1----0------- 0
---000--01------0---- 0
1--011--1---0-------- 0
---0010-0------0----- 0
0--011--1--0--------- 0
---0011-0-----0------ 0
-1-001--1-----0------ 0
1--001--1-----0------ 0
---010--0--------1--- 0
---010--1----------1- 0
---011--0---------1-- 0
---000--1-1---------- 0
---1----------------1 0
.names ni_nires__reg_data2pos_6_.BLIF ni_nires__reg_data0pos_6_.BLIF \
ni_nires__reg_data1pos_6_.BLIF ni_nires__reg_data3pos_6_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_16_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names ni_nires__reg_data2pos_7_.BLIF ni_nires__reg_data0pos_7_.BLIF \
ni_nires__reg_data1pos_7_.BLIF ni_nires__reg_data3pos_7_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_17_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names ni_nires__reg_data2pos_8_.BLIF ni_nires__reg_data0pos_8_.BLIF \
ni_nires__reg_data1pos_8_.BLIF ni_nires__reg_data3pos_8_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_18_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names reset_n.BLIF reg_TXD_15_reg.AR
0 1
1 0
.names ni_nires__reg_data2pos_9_.BLIF ni_nires__reg_data0pos_9_.BLIF \
ni_nires__reg_data1pos_9_.BLIF ni_nires__reg_data3pos_9_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_19_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names reg_ID_3_0_.BLIF reg_ID_3_0_.D
0 1
1 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_3_0_.AR
0- 1
-0 1
11 0
.names int_SD2ANL.BLIF reg_TXD_12_reg.BLIF j2c__reg_creg0hm_3_.BLIF \
j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF testpatt.BLIF \
j2c__reg_creg0hm_0_.BLIF nx1309.BLIF nx1333.BLIF reg_TXD_12_reg.D
1-0-000-0 1
1--1-010- 1
1--110-0- 1
1-00-0--0 1
10---1--- 1
1-1--0-0- 1
--0-000-1 0
---1-011- 0
---110-1- 0
--00-0--1 0
--1--0-1- 0
-1---1--- 0
0-------- 0
.names reset_n.BLIF reg_TXD_12_reg.AR
0 1
1 0
.names ni_reg_valid2reg.BLIF reg_TXD_0_reg.BLIF ix867.BLIF \
ni_reg_ce_prty_bit_pos.D
110 1
101 1
-00 0
-11 0
0-- 0
.names int_SD2ANL.BLIF reg_TXD_0_reg.BLIF j2c__ix77.BLIF j2c__ix99.BLIF \
j2c__ix85.BLIF j2c__reg_creg0hm_3_.BLIF j2c__reg_creg0hm_2_.BLIF \
j2c__reg_creg0hm_1_.BLIF nx972.BLIF nx988.BLIF testpatt.BLIF j2c__ix107.BLIF \
j2c__reg_creg0hm_0_.BLIF ni_nires__reg_data_out_0_.BLIF reg_TXD_0_reg.D
10--------1--- 1
1-------0-0-1- 1
1------10-0--- 1
1-----1-0-0--- 1
1----1--0-0--- 1
1---------0111 1
1---1-----0-11 1
1--1------0-11 1
1-1-------0-11 1
1------1--01-1 1
1-----1---01-1 1
1----1----01-1 1
1---1--1--0--1 1
1--1---1--0--1 1
1-1----1--0--1 1
1---1-1---0--1 1
1--1--1---0--1 1
1-1---1---0--1 1
1---11----0--1 1
1--1-1----0--1 1
1-1--1----0--1 1
---------0---- 1
--000---1100-- 0
-----000-10-0- 0
-1-------11--- 0
--------110--0 0
0--------1---- 0
.names reset_n.BLIF reg_TXD_0_reg.AR
0 1
1 0
.names int_SD2ANL.BLIF reg_TXD_13_reg.BLIF reg_TXD_12_reg.BLIF \
j2c__reg_creg0hm_3_.BLIF j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF \
testpatt.BLIF nx1325.BLIF nx1333.BLIF reg_TXD_13_reg.D
1--0-000- 1
1--00-00- 1
110---1-- 1
101---1-- 1
1---110-0 1
1--1--0-0 1
---0-001- 0
---00-01- 0
-00---1-- 0
-11---1-- 0
----110-1 0
---1--0-1 0
0-------- 0
.names reset_n.BLIF reg_TXD_13_reg.AR
0 1
1 0
.names int_SD2ANL.BLIF testpatt.BLIF ni_nires__reg_valid.BLIF \
reg_ni_pattcount_2_.BLIF reg_ni_pattcount_1_.BLIF reg_ni_pattcount_0_.BLIF \
reg_ni_pattcount_4_.BLIF reg_ni_pattcount_3_.BLIF ni_reg_valid2reg.D
101----- 1
11----1- 1
11---1-- 1
11--1--- 1
11-1---- 1
11-----1 1
-1-00000 0
-00----- 0
0------- 0
.names int_SD2ANL.BLIF reg_TXD_14_reg.BLIF reg_TXD_13_reg.BLIF \
reg_TXD_12_reg.BLIF j2c__ix77.BLIF j2c__reg_creg0hm_3_.BLIF \
j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF testpatt.BLIF \
j2c__reg_creg0hm_0_.BLIF ni_nires__reg_data_out_18_.BLIF \
ni_nires__reg_data_out_17_.BLIF nx1325.BLIF reg_TXD_14_reg.D
1011----1---- 1
1-----1101--0 1
1---10--00-1- 1
1---10-00--1- 1
1---100-0--1- 1
1---00--001-- 1
1---00-00-1-- 1
1---000-0-1-- 1
11-0----1---- 1
110-----1---- 1
1----1--0---0 1
-111----1---- 0
------1101--1 0
----10--00-0- 0
----10-00--0- 0
----100-0--0- 0
----00--000-- 0
----00-00-0-- 0
----000-0-0-- 0
-0-0----1---- 0
-00-----1---- 0
-----1--0---1 0
0------------ 0
.names reset_n.BLIF reg_TXD_14_reg.AR
0 1
1 0
.names reg_ni_pattcount_0_.BLIF reg_ni_pattcount_0_.D
0 1
1 0
.names reset_n.BLIF reg_TXD_11_reg.AP
0 1
1 0
.names reset_n.BLIF reg_TXD_10_reg.AP
0 1
1 0
.names ni_nires__reg_data2neg_0_.BLIF ni_nires__reg_old_cnt_1_.BLIF \
ni_nires__reg_old_cnt_0_.BLIF ni_nires__reg_data0neg_0_.BLIF \
ni_nires__reg_data1neg_0_.BLIF ni_nires__reg_data3neg_0_.BLIF \
ni_nires__reg_data_out_0_.D
-001-- 1
111--- 1
-01-1- 1
-10--1 1
-000-- 0
011--- 0
-01-0- 0
-10--0 0
.names int_SD2ANL.BLIF reg_TXD_9_reg.BLIF reg_TXD_8_reg.BLIF \
j2c__reg_creg0hm_3_.BLIF j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF \
testpatt.BLIF nx1039.BLIF nx1265.BLIF ni_nires__reg_data_out_13_.BLIF \
ni_nires__reg_data_out_12_.BLIF reg_TXD_9_reg.D
1--00001-1- 1
1--00000--1 1
100---1---- 1
111---1---- 1
1----10-0-- 1
1---1-0-0-- 1
1--1--0-0-- 1
---00001-0- 0
---00000--0 0
-10---1---- 0
-01---1---- 0
-----10-1-- 0
----1-0-1-- 0
---1--0-1-- 0
0---------- 0
.names reset_n.BLIF reg_TXD_9_reg.AP
0 1
1 0
.names ni_nires__reg_clear_n_i.BLIF ni_nires__reg_gray_cntf_1_.AR
0 1
1 0
.names ni_nires__reg_clear_n_i.BLIF ni_nires__reg_gray_cntf_0_.AR
0 1
1 0
.names ni_nires__reg_clear_n_i.BLIF ni_nires__reg_old_cnt_1_.AR
0 1
1 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_2_6_.AR
0- 1
-0 1
11 0
.names ni_nires__reg_clear_n_i.BLIF ni_nires__reg_new_cnt_1_.AR
0 1
1 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_2_1_.AR
0- 1
-0 1
11 0
.names ni_nires__reg_clear_n_i.BLIF ni_nires__reg_old_cnt_0_.AR
0 1
1 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__reg_creg0hm_3_.BLIF \
j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF nx972.BLIF nx990.BLIF \
nx1039.BLIF nx1052.BLIF nx1059.BLIF nx1076.BLIF j2c__ix107.BLIF \
j2c__reg_creg0hm_0_.BLIF nx1099.BLIF ni_nires__reg_data_out_8_.BLIF \
ni_nires__reg_data_out_7_.BLIF ni_nires__reg_data_out_6_.BLIF \
ni_nires__reg_data_out_5_.BLIF ni_nires__reg_data_out_4_.BLIF \
ni_nires__reg_data_out_3_.BLIF ni_nires__reg_data_out_2_.BLIF \
ni_nires__reg_data_out_0_.BLIF ni_reg_prty_bit_pos_r.D
00-001-------1-----1--- 1
---010----0--1----1---- 1
---010----1--1---1----- 1
0--011-------1-1------- 1
1--011-------1--1------ 1
---001--0----0-------1- 1
---001--1----0------1-- 1
-1-001-------1------1-- 1
1--001-------1------1-- 1
---010---0---0--------- 1
---011-----0-0--------- 1
---0000------0--------- 1
---000-0-----1--------- 1
---000------10--------1 1
--1000-------0--------1 1
-1-000-------0--------1 1
1--000-------0--------1 1
---1----------0-------- 1
0000001-----00--------- 0
00-001-------1-----0--- 0
---010----0--1----0---- 0
---010----1--1---0----- 0
---001--0----0-------0- 0
---001--1----0------0-- 0
1--011-------1--0------ 0
0--011-------1-0------- 0
-1-001-------1------0-- 0
1--001-------1------0-- 0
---010---1---0--------- 0
---0001------0--------0 0
---011-----1-0--------- 0
---000-1-----1--------- 0
---1----------1-------- 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_2_2_.AR
0- 1
-0 1
11 0
.names ni_nires__reg_clear_n_i.BLIF ni_nires__reg_new_cnt_0_.AR
0 1
1 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_2_3_.AR
0- 1
-0 1
11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_2_4_.AR
0- 1
-0 1
11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_2_5_.AR
0- 1
-0 1
11 0
.names ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data2neg_1_.BLIF ni_nires__reg_data0neg_1_.BLIF \
ni_nires__reg_data1neg_1_.BLIF ni_nires__reg_data3neg_1_.BLIF \
ni_nires__reg_data_out_1_.D
00-1-- 1
111--- 1
01--1- 1
10---1 1
00-0-- 0
110--- 0
01--0- 0
10---0 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_1_0_.AR
0- 1
-0 1
11 0
.names reg_ID_0_0_.BLIF reg_ID_0_0_.D
0 1
1 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_0_0_.AR
0- 1
-0 1
11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_0_1_.AR
0- 1
-0 1
11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_0_2_.AR
0- 1
-0 1
11 0
.names ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data2neg_2_.BLIF ni_nires__reg_data0neg_2_.BLIF \
ni_nires__reg_data1neg_2_.BLIF ni_nires__reg_data3neg_2_.BLIF \
ni_nires__reg_data_out_2_.D
00-1-- 1
111--- 1
01--1- 1
10---1 1
00-0-- 0
110--- 0
01--0- 0
10---0 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_0_3_.AR
0- 1
-0 1
11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_0_4_.AR
0- 1
-0 1
11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_0_5_.AR
0- 1
-0 1
11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_0_6_.AR
0- 1
-0 1
11 0
.names ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data2neg_3_.BLIF ni_nires__reg_data0neg_3_.BLIF \
ni_nires__reg_data1neg_3_.BLIF ni_nires__reg_data3neg_3_.BLIF \
ni_nires__reg_data_out_3_.D
00-1-- 1
111--- 1
01--1- 1
10---1 1
00-0-- 0
110--- 0
01--0- 0
10---0 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_0_7_.AR
0- 1
-0 1
11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_1_1_.AR
0- 1
-0 1
11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_1_2_.AR
0- 1
-0 1
11 0
.names ni_nires__reg_data2neg_4_.BLIF ni_nires__reg_data0neg_4_.BLIF \
ni_nires__reg_data1neg_4_.BLIF ni_nires__reg_data3neg_4_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_4_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_1_3_.AR
0- 1
-0 1
11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_1_4_.AR
0- 1
-0 1
11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_1_5_.AR
0- 1
-0 1
11 0
.names reset_n.BLIF reg_TXD_7_reg.AP
0 1
1 0
.names ni_nires__reg_data2neg_5_.BLIF ni_nires__reg_data0neg_5_.BLIF \
ni_nires__reg_data1neg_5_.BLIF ni_nires__reg_data3neg_5_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_5_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF reg_ID_1_6_.AR
0- 1
-0 1
11 0
.names int_SD2ANL.BLIF reg_TXD_6_reg.BLIF reg_TXD_5_reg.BLIF \
reg_TXD_4_reg.BLIF j2c__ix77.BLIF j2c__reg_creg0hm_3_.BLIF \
j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF testpatt.BLIF nx1076.BLIF \
j2c__reg_creg0hm_0_.BLIF ni_nires__reg_data_out_8_.BLIF \
ni_nires__reg_data_out_7_.BLIF reg_TXD_6_reg.D
1-----11001-- 1
1000----1---- 1
1---00--0-01- 1
1---00-00--1- 1
1---000-0--1- 1
11-1----1---- 1
111-----1---- 1
1---10--0-0-1 1
1---10-00---1 1
1---100-0---1 1
1----1--00--- 1
------11011-- 0
-100----1---- 0
----00--0-00- 0
----00-00--0- 0
----000-0--0- 0
----10--0-0-0 0
----10-00---0 0
----100-0---0 0
-0-1----1---- 0
-01-----1---- 0
-----1--01--- 0
0------------ 0
.names reset_n.BLIF reg_TXD_6_reg.AP
0 1
1 0
.names ni_nires__reg_data2neg_6_.BLIF ni_nires__reg_data0neg_6_.BLIF \
ni_nires__reg_data1neg_6_.BLIF ni_nires__reg_data3neg_6_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_6_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names int_SD2ANL.BLIF reg_TXD_5_reg.BLIF reg_TXD_4_reg.BLIF \
j2c__reg_creg0hm_3_.BLIF j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF \
testpatt.BLIF nx1059.BLIF nx1076.BLIF ni_nires__reg_data_out_6_.BLIF \
ni_nires__reg_data_out_5_.BLIF reg_TXD_5_reg.D
1---1101-1- 1
1--0-00-0-- 1
1--00-0-0-- 1
1---1100--1 1
1--1--01-1- 1
100---1---- 1
111---1---- 1
1--1--00--1 1
----1101-0- 0
----1100--0 0
---0-00-1-- 0
---00-0-1-- 0
---1--01-0- 0
-10---1---- 0
-01---1---- 0
---1--00--0 0
0---------- 0
.names reset_n.BLIF reg_TXD_5_reg.AP
0 1
1 0
.names ni_nires__reg_data2neg_7_.BLIF ni_nires__reg_data0neg_7_.BLIF \
ni_nires__reg_data1neg_7_.BLIF ni_nires__reg_data3neg_7_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_7_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names int_SD2ANL.BLIF reg_TXD_4_reg.BLIF j2c__reg_creg0hm_3_.BLIF \
j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF testpatt.BLIF nx1052.BLIF \
nx1059.BLIF j2c__reg_creg0hm_0_.BLIF ni_nires__reg_data_out_6_.BLIF \
ni_nires__reg_data_out_5_.BLIF reg_TXD_4_reg.D
1-0-00-101- 1
1-0-00-00-1 1
1-00-0-1-1- 1
1--1-00-1-- 1
1--1100---- 1
1-00-0-0--1 1
10---1----- 1
1-1--00---- 1
--0-00-100- 0
--0-00-00-0 0
--00-0-1-0- 0
---1-01-1-- 0
---1101---- 0
--00-0-0--0 0
--1--01---- 0
-1---1----- 0
0---------- 0
.names reset_n.BLIF reg_TXD_4_reg.AP
0 1
1 0
.names reset_n.BLIF j2c__reg_creg1hm_2_.AP
0 1
1 0
.names reset_n.BLIF j2c__reg_cmdreg_0_.AP
0 1
1 0
.names ni_nires__reg_data2neg_8_.BLIF ni_nires__reg_data0neg_8_.BLIF \
ni_nires__reg_data1neg_8_.BLIF ni_nires__reg_data3neg_8_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_8_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names jTDI.BLIF j2c__reg_shreg_7_.BLIF j2c__reg_cmdreg_3_.D
11 1
0- 0
-0 0
.names reset_n.BLIF j2c__reg_cmdreg_3_.AR
0 1
1 0
.names reset_n.BLIF j2c__reg_creg1hm_6_.AP
0 1
1 0
.names reset_n.BLIF j2c__reg_creg1hm_5_.AR
0 1
1 0
.names reset_n.BLIF j2c__reg_creg1hm_4_.AR
0 1
1 0
.names reset_n.BLIF j2c__reg_creg1hm_3_.AP
0 1
1 0
.names ni_nires__reg_data2neg_9_.BLIF ni_nires__reg_data0neg_9_.BLIF \
ni_nires__reg_data1neg_9_.BLIF ni_nires__reg_data3neg_9_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_9_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names reset_n.BLIF reg_TXD_3_reg.AR
0 1
1 0
.names reset_n.BLIF j2c__reg_creg1hm_1_.AR
0 1
1 0
.names int_SD2ANL.BLIF reg_TXD_1_reg.BLIF reg_TXD_0_reg.BLIF \
j2c__reg_creg0hm_3_.BLIF j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF \
nx990.BLIF testpatt.BLIF nx1039.BLIF ni_nires__reg_data_out_3_.BLIF \
ni_nires__reg_data_out_2_.BLIF reg_TXD_1_reg.D
1--000-011- 1
1--000-00-1 1
110----1--- 1
101----1--- 1
1----100--- 1
1---1-00--- 1
1--1--00--- 1
---000-010- 0
---000-00-0 0
-00----1--- 0
-11----1--- 0
-----110--- 0
----1-10--- 0
---1--10--- 0
0---------- 0
.names reset_n.BLIF reg_TXD_1_reg.AR
0 1
1 0
.names ni_nires__reg_data2pos_0_.BLIF ni_nires__reg_data0pos_0_.BLIF \
ni_nires__reg_data1pos_0_.BLIF ni_nires__reg_data3pos_0_.BLIF \
ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_data_out_10_.D
-1--00 1
---110 1
--1-01 1
1---11 1
-0--00 0
---010 0
--0-01 0
0---11 0
.names reset_n.BLIF j2c__reg_creg1hm_0_.AR
0 1
1 0
.names ni_nires__reg_clear_n_i.BLIF ni_nires__reg_gray_cnt_1_.AR
0 1
1 0
.names ni_nires__reg_clear_n_i.BLIF ni_nires__reg_gray_cnt_0_.AR
0 1
1 0
.names reset_n.BLIF reg_TXD_2_reg.AR
0 1
1 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__ix107.BLIF int_SD2ANL
--0- 1
-0-- 1
0--- 1
---1 1
1110 0
.names DIS_JTG.BLIF jTMS.BLIF j2c__nx0
1- 1
-1 1
00 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__ix107.BLIF \
ni_nires__reg_data_out_1_.BLIF nx972
---1- 1
--1-- 1
-1--- 1
1---- 1
----0 1
00001 0
.names int_SD2ANL.BLIF j2c__reg_creg0hm_3_.BLIF j2c__reg_creg0hm_2_.BLIF \
j2c__reg_creg0hm_1_.BLIF nx990.BLIF testpatt.BLIF j2c__reg_creg0hm_0_.BLIF \
nx988
-----1- 1
----1-- 1
---1--- 1
--1---- 1
-1----- 1
0------ 1
------1 1
1000000 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF \
ni_nires__reg_data_out_2_.BLIF ni_nires__reg_data_out_1_.BLIF nx990
0000- 1
--1-0 1
-1--0 1
1---0 1
0001- 0
--1-1 0
-1--1 0
1---1 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__ix107.BLIF testpatt
1100 1
--1- 0
-0-- 0
0--- 0
---1 0
.names DIS_JTG.BLIF jTCK.BLIF int_SD2ANL.BLIF nx12
10- 1
--0 1
-11 0
0-1 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__ix107.BLIF nx1039
000- 1
00-0 1
-1-- 0
1--- 0
--11 0
.names FAULT.BLIF j2c__reg_cmdreg_0_.BLIF reg_ID_2_6_.BLIF reg_ID_2_5_.BLIF \
reg_ID_2_4_.BLIF reg_ID_2_3_.BLIF reg_ID_2_2_.BLIF j2c__bitcnt_0_.BLIF \
reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF j2c__bitcnt_1_.BLIF reg_ID_3_6_.BLIF \
reg_ID_3_5_.BLIF j2c__bitcnt_2_.BLIF reg_ID_3_4_.BLIF reg_ID_3_3_.BLIF \
reg_ID_3_2_.BLIF reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF j2c__nx414
-1-----1--1--0-1--- 1
-1-----1--0-11----- 1
-1-----0--11-1----- 1
-1-----1--0--0---1- 1
-1-----0--1--0--1-- 1
-1-----0--0--11---- 1
-0---1-1--1--0----- 1
-0-1---1--0--1----- 1
-01----0--1--1----- 1
-0-----11-0--0----- 1
-0----10--1--0----- 1
-0--1--0--0--1----- 1
-0-----0-10--0----- 1
1------1--1--1----- 1
-1-----0--0--0----1 1
-1-----1--1--0-0--- 0
-1-----1--0-01----- 0
-1-----0--10-1----- 0
-1-----1--0--0---0- 0
-1-----0--1--0--0-- 0
-1-----0--0--10---- 0
-0---0-1--1--0----- 0
-0-0---1--0--1----- 0
-00----0--1--1----- 0
-0-----10-0--0----- 0
-0----00--1--0----- 0
-0--0--0--0--1----- 0
-0-----0-00--0----- 0
0------1--1--1----- 0
-1-----0--0--0----0 0
.names DIS_JTG.BLIF jTMS.BLIF int_SD2ANL.BLIF nx20
10- 1
--0 1
-11 0
0-1 0
.names DIS_JTG.BLIF jTCK.BLIF j2c__nx0.BLIF nx197
1-- 1
-11 1
00- 0
0-0 0
.names j2c__ix99.BLIF nx1059.BLIF j2c__ix107.BLIF \
ni_nires__reg_data_out_5_.BLIF ni_nires__reg_data_out_4_.BLIF nx1052
-100- 1
01-0- 1
1-1-0 1
-0--0 1
-101- 0
01-1- 0
1-1-1 0
-0--1 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF nx1059
00- 1
0-0 1
1-- 0
-11 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__ix107.BLIF \
ni_nires__reg_data_out_7_.BLIF ni_nires__reg_data_out_6_.BLIF nx1076
-111-0 1
0--00- 1
0-0-0- 1
00--0- 1
1----0 1
-111-1 0
0--01- 0
0-0-1- 0
00--1- 0
1----1 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__ix107.BLIF \
ni_nires__reg_data_out_9_.BLIF ni_nires__reg_data_out_8_.BLIF nx1099
-0000- 1
0---0- 1
1--1-0 1
1-1--0 1
11---0 1
-0001- 0
0---1- 0
1--1-1 0
1-1--1 0
11---1 0
.names FAULT.BLIF reg_ID_1_6_.BLIF reg_ID_1_5_.BLIF reg_ID_1_4_.BLIF \
reg_ID_1_3_.BLIF reg_ID_1_2_.BLIF reg_ID_1_1_.BLIF reg_ID_1_0_.BLIF \
j2c__bitcnt_0_.BLIF j2c__bitcnt_1_.BLIF j2c__bitcnt_2_.BLIF j2c__nx330
-------1000 1
------1-100 1
-----1--010 1
----1---110 1
---1----001 1
--1-----101 1
-1------011 1
1-------111 1
-------0000 0
------0-100 0
-----0--010 0
----0---110 0
---0----001 0
--0-----101 0
-0------011 0
0-------111 0
.names reg_ID_0_7_.BLIF reg_ID_0_6_.BLIF reg_ID_0_5_.BLIF reg_ID_0_4_.BLIF \
reg_ID_0_3_.BLIF reg_ID_0_2_.BLIF reg_ID_0_1_.BLIF reg_ID_0_0_.BLIF \
j2c__bitcnt_0_.BLIF j2c__bitcnt_1_.BLIF j2c__bitcnt_2_.BLIF j2c__nx365
---0----001 1
--0-----101 1
-0------011 1
0-------111 1
-------0000 1
------0-100 1
-----0--010 1
----0---110 1
-------1000 0
------1-100 0
-----1--010 0
----1---110 0
---1----001 0
--1-----101 0
-1------011 0
1-------111 0
.names reg_ID_0_0_.BLIF reg_ID_0_1_.BLIF reg_ID_0_2_.BLIF reg_ID_0_3_.BLIF \
reg_ID_0_4_.BLIF reg_ID_0_5_.BLIF reg_ID_0_6_.BLIF reg_ID_0_7_.BLIF nx96
11111111 1
------0- 0
-----0-- 0
----0--- 0
---0---- 0
--0----- 0
-0------ 0
0------- 0
-------0 0
.names int_SD2ANL.BLIF ni_reg_valid2reg.BLIF testpatt.BLIF \
ni_nires__reg_valid.BLIF nx148
-11- 1
0--- 1
--01 1
101- 0
1-00 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__ix107.BLIF \
ni_nires__reg_data_out_11_.BLIF nx1255
---1- 1
--1-- 1
-1--- 1
1---- 1
----0 1
00001 0
.names int_SD2ANL.BLIF j2c__reg_creg0hm_3_.BLIF j2c__reg_creg0hm_2_.BLIF \
j2c__reg_creg0hm_1_.BLIF testpatt.BLIF j2c__reg_creg0hm_0_.BLIF nx1265.BLIF \
nx1263
-----1- 1
----1-- 1
---1--- 1
--1---- 1
-1----- 1
0------ 1
------1 1
1000000 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF \
ni_nires__reg_data_out_12_.BLIF ni_nires__reg_data_out_11_.BLIF nx1265
0000- 1
--1-0 1
-1--0 1
1---0 1
0001- 0
--1-1 0
-1--1 0
1---1 0
.names j2c__ix99.BLIF nx1059.BLIF j2c__ix107.BLIF \
ni_nires__reg_data_out_15_.BLIF ni_nires__reg_data_out_14_.BLIF nx1309
-100- 1
01-0- 1
1-1-0 1
-0--0 1
-101- 0
01-1- 0
1-1-1 0
-0--1 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__ix107.BLIF \
ni_nires__reg_data_out_17_.BLIF ni_nires__reg_data_out_16_.BLIF nx1325
-111-0 1
0--00- 1
0-0-0- 1
00--0- 1
1----0 1
-111-1 0
0--01- 0
0-0-1- 0
00--1- 0
1----1 0
.names nx1059.BLIF ni_nires__reg_data_out_16_.BLIF \
ni_nires__reg_data_out_15_.BLIF nx1333
10- 1
0-0 1
11- 0
0-1 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__ix107.BLIF \
ni_nires__reg_data_out_19_.BLIF ni_nires__reg_data_out_18_.BLIF nx1341
-0000- 1
0---0- 1
1--1-0 1
1-1--0 1
11---0 1
-0001- 0
0---1- 0
1--1-1 0
1-1--1 0
11---1 0
.names ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.BLIF \
ni_nires__reg_new_cnt_1_.BLIF ni_nires__reg_new_cnt_0_.BLIF ni_nires__nx1078
1-0- 1
0-1- 1
-1-0 1
-0-1 1
0000 0
1010 0
0101 0
1111 0
.names j2c__ix59.BLIF j2c__ix71.BLIF j2c__reg_creg1hm_6_.BLIF j2c__ix45.BLIF \
j2c__ix77
1101 1
-01- 1
0-1- 1
--10 1
1111 0
-00- 0
0-0- 0
--00 0
.names j2c__ix59.BLIF j2c__ix71.BLIF j2c__reg_creg1hm_5_.BLIF j2c__ix45.BLIF \
j2c__ix99
1001 1
-11- 1
0-1- 1
--10 1
1011 0
-10- 0
0-0- 0
--00 0
.names j2c__ix59.BLIF j2c__ix71.BLIF j2c__reg_creg1hm_4_.BLIF j2c__ix45.BLIF \
j2c__ix85
0101 1
-01- 1
1-1- 1
--10 1
0111 0
-00- 0
1-0- 0
--00 0
.names j2c__reg_creg1hm_2_.BLIF j2c__ix59.BLIF j2c__ix71.BLIF j2c__ix45.BLIF \
j2c__ix107
0110 1
1-0- 1
10-- 1
1--1 1
1110 0
0-0- 0
00-- 0
0--1 0
.names reg_TXD_12_reg.BLIF reg_TXD_11_reg.BLIF ix521
10 1
01 1
00 0
11 0
.names reg_TXD_10_reg.BLIF reg_TXD_9_reg.BLIF ix523
10 1
01 1
00 0
11 0
.names reg_TXD_7_reg.BLIF ni_reg_prty_bit_pos_r.BLIF ix793
10 1
01 1
00 0
11 0
.names TESTEN
 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__ix107.BLIF PRBSEN
1010 1
--0- 0
-1-- 0
0--- 0
---1 0
.names LCKREFN
 0
.names int_SD2ANL.BLIF ENABLE
1 1
0 0
.names LOOPEN
 0
.names TX_ER
 0
.names ni_reg_valid2reg.BLIF TX_EN
1 1
0 0
.names reg_TXD_15_reg.BLIF TXD_15_
1 1
0 0
.names int_SD2ANL.BLIF EN
1 1
0 0
.names int_SD2ANL.BLIF SD2ANL
1 1
0 0
.names j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__ix107.BLIF WP_EEP
--0- 1
-1-- 1
0--- 1
---0 1
1011 0
.names SCL
 0
.names reg_TXD_14_reg.BLIF TXD_14_
1 1
0 0
.names reg_TXD_13_reg.BLIF TXD_13_
1 1
0 0
.names reg_TXD_12_reg.BLIF TXD_12_
1 1
0 0
.names reg_TXD_11_reg.BLIF TXD_11_
1 1
0 0
.names reg_TXD_10_reg.BLIF TXD_10_
1 1
0 0
.names reg_TXD_9_reg.BLIF TXD_9_
1 1
0 0
.names reg_TXD_8_reg.BLIF TXD_8_
1 1
0 0
.names reg_TXD_7_reg.BLIF TXD_7_
1 1
0 0
.names reg_TXD_6_reg.BLIF TXD_6_
1 1
0 0
.names reg_TXD_5_reg.BLIF TXD_5_
1 1
0 0
.names reg_TXD_4_reg.BLIF TXD_4_
1 1
0 0
.names reg_TXD_3_reg.BLIF TXD_3_
1 1
0 0
.names reg_TXD_2_reg.BLIF TXD_2_
1 1
0 0
.names reg_TXD_1_reg.BLIF TXD_1_
1 1
0 0
.names reg_TXD_0_reg.BLIF TXD_0_
1 1
0 0
.names NI_D_0_.BLIF ni_nires__reg_data3pos_0_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data3pos_0_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3pos_0_.C
1 1
0 0
.names j2c__reg_shreg_0_.BLIF j2c__reg_creg0hm_0_.D
1 1
0 0
.names jTDI.BLIF j2c__reg_cmdreg_0_.BLIF j2c__reg_cmdreg_3_.BLIF \
j2c__reg_creg0hm_0_.CE
001 1
-1- 0
1-- 0
--0 0
.names j2c__nx0.BLIF j2c__reg_creg0hm_0_.C
1 1
0 0
.names reg_ID_3_6_.BLIF reg_ID_3_5_.BLIF reg_ID_3_4_.BLIF reg_ID_3_3_.BLIF \
reg_ID_3_2_.BLIF reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF ni_reg_ce_prty_bit_pos.BLIF \
reg_ID_3_6_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_3_6_.C
1 1
0 0
.names j2c__reg_shreg_1_.BLIF j2c__reg_shreg_0_.D
1 1
0 0
.names jTCK.BLIF j2c__reg_shreg_0_.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_11_.C
1 1
0 0
.names j2c__reg_shreg_2_.BLIF j2c__reg_shreg_1_.D
1 1
0 0
.names jTCK.BLIF j2c__reg_shreg_1_.C
1 1
0 0
.names j2c__reg_shreg_3_.BLIF j2c__reg_shreg_2_.D
1 1
0 0
.names jTCK.BLIF j2c__reg_shreg_2_.C
1 1
0 0
.names reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF reg_ID_3_1_.D
10 1
01 1
00 0
11 0
.names reg_ID_3_6_.BLIF reg_ID_3_5_.BLIF reg_ID_3_4_.BLIF reg_ID_3_3_.BLIF \
reg_ID_3_2_.BLIF reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF ni_reg_ce_prty_bit_pos.BLIF \
reg_ID_3_1_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_3_1_.C
1 1
0 0
.names j2c__reg_shreg_4_.BLIF j2c__reg_shreg_3_.D
1 1
0 0
.names jTCK.BLIF j2c__reg_shreg_3_.C
1 1
0 0
.names NI_D_1_.BLIF ni_nires__reg_data2pos_1_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data2pos_1_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2pos_1_.C
1 1
0 0
.names j2c__reg_shreg_1_.BLIF j2c__reg_creg0hm_1_.D
1 1
0 0
.names jTDI.BLIF j2c__reg_cmdreg_0_.BLIF j2c__reg_cmdreg_3_.BLIF \
j2c__reg_creg0hm_1_.CE
001 1
-1- 0
1-- 0
--0 0
.names j2c__nx0.BLIF j2c__reg_creg0hm_1_.C
1 1
0 0
.names reg_ID_3_2_.BLIF reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF reg_ID_3_2_.D
011 1
10- 1
1-0 1
111 0
00- 0
0-0 0
.names reg_ID_3_6_.BLIF reg_ID_3_5_.BLIF reg_ID_3_4_.BLIF reg_ID_3_3_.BLIF \
reg_ID_3_2_.BLIF reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF ni_reg_ce_prty_bit_pos.BLIF \
reg_ID_3_2_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_3_2_.C
1 1
0 0
.names j2c__reg_shreg_2_.BLIF j2c__reg_creg0hm_2_.D
1 1
0 0
.names jTDI.BLIF j2c__reg_cmdreg_0_.BLIF j2c__reg_cmdreg_3_.BLIF \
j2c__reg_creg0hm_2_.CE
001 1
-1- 0
1-- 0
--0 0
.names j2c__nx0.BLIF j2c__reg_creg0hm_2_.C
1 1
0 0
.names NI_D_1_.BLIF ni_nires__reg_data0pos_1_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data0pos_1_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0pos_1_.C
1 1
0 0
.names j2c__reg_shreg_3_.BLIF j2c__reg_creg0hm_3_.D
1 1
0 0
.names jTDI.BLIF j2c__reg_cmdreg_0_.BLIF j2c__reg_cmdreg_3_.BLIF \
j2c__reg_creg0hm_3_.CE
001 1
-1- 0
1-- 0
--0 0
.names j2c__nx0.BLIF j2c__reg_creg0hm_3_.C
1 1
0 0
.names NI_D_1_.BLIF ni_nires__reg_data1pos_1_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data1pos_1_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1pos_1_.C
1 1
0 0
.names reg_ID_3_3_.BLIF reg_ID_3_2_.BLIF reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF \
reg_ID_3_3_.D
0111 1
1-0- 1
10-- 1
1--0 1
1111 0
0-0- 0
00-- 0
0--0 0
.names reg_ID_3_6_.BLIF reg_ID_3_5_.BLIF reg_ID_3_4_.BLIF reg_ID_3_3_.BLIF \
reg_ID_3_2_.BLIF reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF ni_reg_ce_prty_bit_pos.BLIF \
reg_ID_3_3_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_3_3_.C
1 1
0 0
.names jTCK.BLIF j2c__reg_rstout_n_i.C
0 1
1 0
.names NI_D_1_.BLIF ni_nires__reg_data3pos_1_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data3pos_1_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3pos_1_.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_12_.C
1 1
0 0
.names reg_ID_3_6_.BLIF reg_ID_3_5_.BLIF reg_ID_3_4_.BLIF reg_ID_3_3_.BLIF \
reg_ID_3_2_.BLIF reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF ni_reg_ce_prty_bit_pos.BLIF \
reg_ID_3_4_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_3_4_.C
1 1
0 0
.names j2c__bitcnt_0_.BLIF j2c__bitcnt_1_.BLIF j2c__bitcnt_1_.D
10 1
01 1
00 0
11 0
.names jTCK.BLIF j2c__bitcnt_1_.C
0 1
1 0
.names NI_D_2_.BLIF ni_nires__reg_data2pos_2_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data2pos_2_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2pos_2_.C
1 1
0 0
.names reg_ID_3_6_.BLIF reg_ID_3_5_.BLIF reg_ID_3_4_.BLIF reg_ID_3_3_.BLIF \
reg_ID_3_2_.BLIF reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF ni_reg_ce_prty_bit_pos.BLIF \
reg_ID_3_5_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_3_5_.C
1 1
0 0
.names j2c__bitcnt_0_.BLIF j2c__bitcnt_0_.D
0 1
1 0
.names jTCK.BLIF j2c__bitcnt_0_.C
0 1
1 0
.names NI_D_2_.BLIF ni_nires__reg_data0pos_2_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data0pos_2_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0pos_2_.C
1 1
0 0
.names NI_D_2_.BLIF ni_nires__reg_data1pos_2_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data1pos_2_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1pos_2_.C
1 1
0 0
.names reg_ID_2_6_.BLIF reg_ID_2_5_.BLIF reg_ID_2_4_.BLIF reg_ID_2_3_.BLIF \
reg_ID_2_2_.BLIF reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF ni_reg_ce_prty_bit_neg.BLIF \
reg_ID_2_0_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_2_0_.C
1 1
0 0
.names j2c__bitcnt_0_.BLIF j2c__bitcnt_1_.BLIF j2c__bitcnt_2_.BLIF \
j2c__bitcnt_2_.D
110 1
-01 1
0-1 1
111 0
-00 0
0-0 0
.names jTCK.BLIF j2c__bitcnt_2_.C
0 1
1 0
.names NI_D_2_.BLIF ni_nires__reg_data3pos_2_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data3pos_2_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3pos_2_.C
1 1
0 0
.names clk.BLIF ni_reg_ce_prty_bit_neg.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_13_.C
1 1
0 0
.names nx148.BLIF reg_TXD_8_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_8_reg.C
1 1
0 0
.names NI_D_3_.BLIF ni_nires__reg_data2pos_3_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data2pos_3_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2pos_3_.C
1 1
0 0
.names j2c__reg_shreg_6_.BLIF j2c__reg_cmdreg_2_.D
1 1
0 0
.names jTDI.BLIF j2c__reg_cmdreg_2_.CE
1 1
0 0
.names j2c__nx0.BLIF j2c__reg_cmdreg_2_.C
1 1
0 0
.names NI_D_3_.BLIF ni_nires__reg_data0pos_3_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data0pos_3_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0pos_3_.C
1 1
0 0
.names NI_D_3_.BLIF ni_nires__reg_data1pos_3_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data1pos_3_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1pos_3_.C
1 1
0 0
.names j2c__reg_shreg_5_.BLIF j2c__reg_cmdreg_1_.D
1 1
0 0
.names jTDI.BLIF j2c__reg_cmdreg_1_.CE
1 1
0 0
.names j2c__nx0.BLIF j2c__reg_cmdreg_1_.C
1 1
0 0
.names NI_D_3_.BLIF ni_nires__reg_data3pos_3_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data3pos_3_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3pos_3_.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_14_.C
1 1
0 0
.names NI_D_4_.BLIF ni_nires__reg_data2pos_4_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data2pos_4_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2pos_4_.C
1 1
0 0
.names NI_D_4_.BLIF ni_nires__reg_data0pos_4_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data0pos_4_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0pos_4_.C
1 1
0 0
.names NI_D_4_.BLIF ni_nires__reg_data1pos_4_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data1pos_4_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1pos_4_.C
1 1
0 0
.names NI_D_4_.BLIF ni_nires__reg_data3pos_4_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data3pos_4_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3pos_4_.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_15_.C
1 1
0 0
.names clk.BLIF ni_reg_prty_bit_neg_r.C
1 1
0 0
.names NI_D_5_.BLIF ni_nires__reg_data2pos_5_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data2pos_5_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2pos_5_.C
1 1
0 0
.names NI_D_5_.BLIF ni_nires__reg_data0pos_5_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data0pos_5_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0pos_5_.C
1 1
0 0
.names NI_D_5_.BLIF ni_nires__reg_data1pos_5_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data1pos_5_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1pos_5_.C
1 1
0 0
.names NI_D_5_.BLIF ni_nires__reg_data3pos_5_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data3pos_5_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3pos_5_.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_16_.C
1 1
0 0
.names NI_D_6_.BLIF ni_nires__reg_data2pos_6_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data2pos_6_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2pos_6_.C
1 1
0 0
.names NI_D_6_.BLIF ni_nires__reg_data0pos_6_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data0pos_6_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0pos_6_.C
1 1
0 0
.names NI_D_6_.BLIF ni_nires__reg_data1pos_6_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data1pos_6_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1pos_6_.C
1 1
0 0
.names NI_D_6_.BLIF ni_nires__reg_data3pos_6_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data3pos_6_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3pos_6_.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_17_.C
1 1
0 0
.names NI_D_7_.BLIF ni_nires__reg_data2pos_7_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data2pos_7_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2pos_7_.C
1 1
0 0
.names NI_D_7_.BLIF ni_nires__reg_data0pos_7_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data0pos_7_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0pos_7_.C
1 1
0 0
.names NI_D_7_.BLIF ni_nires__reg_data1pos_7_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data1pos_7_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1pos_7_.C
1 1
0 0
.names NI_D_7_.BLIF ni_nires__reg_data3pos_7_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data3pos_7_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3pos_7_.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_18_.C
1 1
0 0
.names NI_D_8_.BLIF ni_nires__reg_data2pos_8_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data2pos_8_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2pos_8_.C
1 1
0 0
.names NI_D_8_.BLIF ni_nires__reg_data0pos_8_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data0pos_8_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0pos_8_.C
1 1
0 0
.names nx148.BLIF reg_TXD_15_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_15_reg.C
1 1
0 0
.names NI_D_8_.BLIF ni_nires__reg_data1pos_8_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data1pos_8_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1pos_8_.C
1 1
0 0
.names NI_D_8_.BLIF ni_nires__reg_data3pos_8_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data3pos_8_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3pos_8_.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_19_.C
1 1
0 0
.names reg_ID_3_6_.BLIF reg_ID_3_5_.BLIF reg_ID_3_4_.BLIF reg_ID_3_3_.BLIF \
reg_ID_3_2_.BLIF reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF ni_reg_ce_prty_bit_pos.BLIF \
reg_ID_3_0_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_3_0_.C
1 1
0 0
.names NI_D_9_.BLIF ni_nires__reg_data2pos_9_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data2pos_9_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2pos_9_.C
1 1
0 0
.names nx148.BLIF reg_TXD_12_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_12_reg.C
1 1
0 0
.names clk.BLIF ni_reg_ce_prty_bit_pos.C
1 1
0 0
.names NI_D_9_.BLIF ni_nires__reg_data0pos_9_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data0pos_9_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0pos_9_.C
1 1
0 0
.names NI_D_9_.BLIF ni_nires__reg_data1pos_9_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data1pos_9_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1pos_9_.C
1 1
0 0
.names nx148.BLIF reg_TXD_0_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_0_reg.C
1 1
0 0
.names nx148.BLIF reg_TXD_13_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_13_reg.C
1 1
0 0
.names NI_D_9_.BLIF ni_nires__reg_data3pos_9_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data3pos_9_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3pos_9_.C
1 1
0 0
.names ni_nires__nx1078.BLIF ni_nires__reg_valid.D
1 1
0 0
.names clk.BLIF ni_nires__reg_valid.C
1 1
0 0
.names clk.BLIF ni_reg_valid2reg.C
1 1
0 0
.names nx148.BLIF reg_TXD_14_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_14_reg.C
1 1
0 0
.names clk.BLIF reg_ni_pattcount_0_.C
1 1
0 0
.names reg_ni_pattcount_1_.BLIF reg_ni_pattcount_0_.BLIF reg_ni_pattcount_1_.D
10 1
01 1
00 0
11 0
.names clk.BLIF reg_ni_pattcount_1_.C
1 1
0 0
.names reg_ni_pattcount_2_.BLIF reg_ni_pattcount_1_.BLIF \
reg_ni_pattcount_0_.BLIF reg_ni_pattcount_3_.BLIF reg_ni_pattcount_3_.D
1110 1
--01 1
-0-1 1
0--1 1
1111 0
--00 0
-0-0 0
0--0 0
.names clk.BLIF reg_ni_pattcount_3_.C
1 1
0 0
.names reg_ni_pattcount_2_.BLIF reg_ni_pattcount_1_.BLIF \
reg_ni_pattcount_0_.BLIF reg_ni_pattcount_2_.D
011 1
10- 1
1-0 1
111 0
00- 0
0-0 0
.names clk.BLIF reg_ni_pattcount_2_.C
1 1
0 0
.names nx148.BLIF reg_TXD_11_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_11_reg.C
1 1
0 0
.names clk.BLIF reg_ni_pattcount_4_.C
1 1
0 0
.names nx148.BLIF reg_TXD_10_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_10_reg.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_0_.C
1 1
0 0
.names nx148.BLIF reg_TXD_9_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_9_reg.C
1 1
0 0
.names NI_D_0_.BLIF ni_nires__reg_data2neg_0_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data2neg_0_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2neg_0_.C
0 1
1 0
.names ni_nires__reg_gray_cntf_0_.BLIF ni_nires__reg_gray_cntf_1_.D
1 1
0 0
.names NI_STR.BLIF ni_nires__reg_gray_cntf_1_.C
0 1
1 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.D
0 1
1 0
.names NI_STR.BLIF ni_nires__reg_gray_cntf_0_.C
0 1
1 0
.names reset_n.BLIF j2c__reg_rstout_n_i.BLIF ni_nires__reg_clear_n_i.D
11 1
0- 0
-0 0
.names clk.BLIF ni_nires__reg_clear_n_i.C
1 1
0 0
.names ni_nires__reg_old_cnt_0_.BLIF ni_nires__reg_old_cnt_1_.D
1 1
0 0
.names ni_nires__nx1078.BLIF ni_nires__reg_old_cnt_1_.CE
1 1
0 0
.names clk.BLIF ni_nires__reg_old_cnt_1_.C
1 1
0 0
.names reg_ID_2_6_.BLIF reg_ID_2_5_.BLIF reg_ID_2_4_.BLIF reg_ID_2_3_.BLIF \
reg_ID_2_2_.BLIF reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF ni_reg_ce_prty_bit_neg.BLIF \
reg_ID_2_6_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_2_6_.C
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_new_cnt_1_.D
1 1
0 0
.names clk.BLIF ni_nires__reg_new_cnt_1_.C
1 1
0 0
.names reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF reg_ID_2_1_.D
10 1
01 1
00 0
11 0
.names reg_ID_2_6_.BLIF reg_ID_2_5_.BLIF reg_ID_2_4_.BLIF reg_ID_2_3_.BLIF \
reg_ID_2_2_.BLIF reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF ni_reg_ce_prty_bit_neg.BLIF \
reg_ID_2_1_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_2_1_.C
1 1
0 0
.names ni_nires__reg_old_cnt_1_.BLIF ni_nires__reg_old_cnt_0_.D
0 1
1 0
.names ni_nires__nx1078.BLIF ni_nires__reg_old_cnt_0_.CE
1 1
0 0
.names clk.BLIF ni_nires__reg_old_cnt_0_.C
1 1
0 0
.names clk.BLIF ni_reg_prty_bit_pos_r.C
1 1
0 0
.names reg_ID_2_2_.BLIF reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF reg_ID_2_2_.D
011 1
10- 1
1-0 1
111 0
00- 0
0-0 0
.names reg_ID_2_6_.BLIF reg_ID_2_5_.BLIF reg_ID_2_4_.BLIF reg_ID_2_3_.BLIF \
reg_ID_2_2_.BLIF reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF ni_reg_ce_prty_bit_neg.BLIF \
reg_ID_2_2_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_2_2_.C
1 1
0 0
.names ni_nires__reg_gray_cntf_0_.BLIF ni_nires__reg_new_cnt_0_.D
1 1
0 0
.names clk.BLIF ni_nires__reg_new_cnt_0_.C
1 1
0 0
.names NI_D_0_.BLIF ni_nires__reg_data0neg_0_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data0neg_0_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0neg_0_.C
0 1
1 0
.names reg_ID_2_3_.BLIF reg_ID_2_2_.BLIF reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF \
reg_ID_2_3_.D
0111 1
1-0- 1
10-- 1
1--0 1
1111 0
0-0- 0
00-- 0
0--0 0
.names reg_ID_2_6_.BLIF reg_ID_2_5_.BLIF reg_ID_2_4_.BLIF reg_ID_2_3_.BLIF \
reg_ID_2_2_.BLIF reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF ni_reg_ce_prty_bit_neg.BLIF \
reg_ID_2_3_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_2_3_.C
1 1
0 0
.names reg_ID_2_6_.BLIF reg_ID_2_5_.BLIF reg_ID_2_4_.BLIF reg_ID_2_3_.BLIF \
reg_ID_2_2_.BLIF reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF ni_reg_ce_prty_bit_neg.BLIF \
reg_ID_2_4_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_2_4_.C
1 1
0 0
.names NI_D_0_.BLIF ni_nires__reg_data1neg_0_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data1neg_0_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1neg_0_.C
0 1
1 0
.names reg_ID_2_6_.BLIF reg_ID_2_5_.BLIF reg_ID_2_4_.BLIF reg_ID_2_3_.BLIF \
reg_ID_2_2_.BLIF reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF ni_reg_ce_prty_bit_neg.BLIF \
reg_ID_2_5_.CE
------01 1
-----0-1 1
----0--1 1
---0---1 1
--0----1 1
-0-----1 1
0------1 1
1111111- 0
-------0 0
.names clk.BLIF reg_ID_2_5_.C
1 1
0 0
.names NI_D_0_.BLIF ni_nires__reg_data3neg_0_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data3neg_0_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3neg_0_.C
0 1
1 0
.names clk.BLIF ni_nires__reg_data_out_1_.C
1 1
0 0
.names reg_ID_1_0_.BLIF nx96.BLIF reg_ID_1_0_.D
10 1
01 1
00 0
11 0
.names ni_reg_valid2reg.BLIF reg_ID_1_0_.CE
1 1
0 0
.names clk.BLIF reg_ID_1_0_.C
1 1
0 0
.names NI_D_1_.BLIF ni_nires__reg_data2neg_1_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data2neg_1_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2neg_1_.C
0 1
1 0
.names ni_reg_valid2reg.BLIF reg_ID_0_0_.CE
1 1
0 0
.names clk.BLIF reg_ID_0_0_.C
1 1
0 0
.names NI_D_1_.BLIF ni_nires__reg_data0neg_1_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data0neg_1_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0neg_1_.C
0 1
1 0
.names reg_ID_0_1_.BLIF reg_ID_0_0_.BLIF reg_ID_0_1_.D
10 1
01 1
00 0
11 0
.names ni_reg_valid2reg.BLIF reg_ID_0_1_.CE
1 1
0 0
.names clk.BLIF reg_ID_0_1_.C
1 1
0 0
.names NI_D_1_.BLIF ni_nires__reg_data1neg_1_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data1neg_1_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1neg_1_.C
0 1
1 0
.names reg_ID_0_2_.BLIF reg_ID_0_1_.BLIF reg_ID_0_0_.BLIF reg_ID_0_2_.D
011 1
10- 1
1-0 1
111 0
00- 0
0-0 0
.names ni_reg_valid2reg.BLIF reg_ID_0_2_.CE
1 1
0 0
.names clk.BLIF reg_ID_0_2_.C
1 1
0 0
.names NI_D_1_.BLIF ni_nires__reg_data3neg_1_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data3neg_1_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3neg_1_.C
0 1
1 0
.names clk.BLIF ni_nires__reg_data_out_2_.C
1 1
0 0
.names reg_ID_0_3_.BLIF reg_ID_0_2_.BLIF reg_ID_0_1_.BLIF reg_ID_0_0_.BLIF \
reg_ID_0_3_.D
0111 1
1-0- 1
10-- 1
1--0 1
1111 0
0-0- 0
00-- 0
0--0 0
.names ni_reg_valid2reg.BLIF reg_ID_0_3_.CE
1 1
0 0
.names clk.BLIF reg_ID_0_3_.C
1 1
0 0
.names NI_D_2_.BLIF ni_nires__reg_data2neg_2_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data2neg_2_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2neg_2_.C
0 1
1 0
.names ni_reg_valid2reg.BLIF reg_ID_0_4_.CE
1 1
0 0
.names clk.BLIF reg_ID_0_4_.C
1 1
0 0
.names NI_D_2_.BLIF ni_nires__reg_data0neg_2_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data0neg_2_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0neg_2_.C
0 1
1 0
.names ni_reg_valid2reg.BLIF reg_ID_0_5_.CE
1 1
0 0
.names clk.BLIF reg_ID_0_5_.C
1 1
0 0
.names NI_D_2_.BLIF ni_nires__reg_data1neg_2_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data1neg_2_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1neg_2_.C
0 1
1 0
.names NI_D_2_.BLIF ni_nires__reg_data3neg_2_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data3neg_2_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3neg_2_.C
0 1
1 0
.names ni_reg_valid2reg.BLIF reg_ID_0_6_.CE
1 1
0 0
.names clk.BLIF reg_ID_0_6_.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_3_.C
1 1
0 0
.names ni_reg_valid2reg.BLIF reg_ID_0_7_.CE
1 1
0 0
.names clk.BLIF reg_ID_0_7_.C
1 1
0 0
.names NI_D_3_.BLIF ni_nires__reg_data2neg_3_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data2neg_3_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2neg_3_.C
0 1
1 0
.names NI_D_3_.BLIF ni_nires__reg_data0neg_3_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data0neg_3_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0neg_3_.C
0 1
1 0
.names reg_ID_1_1_.BLIF reg_ID_1_0_.BLIF nx96.BLIF reg_ID_1_1_.D
011 1
10- 1
1-0 1
111 0
00- 0
0-0 0
.names ni_reg_valid2reg.BLIF reg_ID_1_1_.CE
1 1
0 0
.names clk.BLIF reg_ID_1_1_.C
1 1
0 0
.names NI_D_3_.BLIF ni_nires__reg_data1neg_3_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data1neg_3_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1neg_3_.C
0 1
1 0
.names reg_ID_1_2_.BLIF reg_ID_1_1_.BLIF reg_ID_1_0_.BLIF nx96.BLIF \
reg_ID_1_2_.D
0111 1
1-0- 1
10-- 1
1--0 1
1111 0
0-0- 0
00-- 0
0--0 0
.names ni_reg_valid2reg.BLIF reg_ID_1_2_.CE
1 1
0 0
.names clk.BLIF reg_ID_1_2_.C
1 1
0 0
.names NI_D_3_.BLIF ni_nires__reg_data3neg_3_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data3neg_3_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3neg_3_.C
0 1
1 0
.names clk.BLIF ni_nires__reg_data_out_4_.C
1 1
0 0
.names ni_reg_valid2reg.BLIF reg_ID_1_3_.CE
1 1
0 0
.names clk.BLIF reg_ID_1_3_.C
1 1
0 0
.names NI_D_4_.BLIF ni_nires__reg_data2neg_4_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data2neg_4_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2neg_4_.C
0 1
1 0
.names ni_reg_valid2reg.BLIF reg_ID_1_4_.CE
1 1
0 0
.names clk.BLIF reg_ID_1_4_.C
1 1
0 0
.names NI_D_4_.BLIF ni_nires__reg_data0neg_4_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data0neg_4_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0neg_4_.C
0 1
1 0
.names NI_D_4_.BLIF ni_nires__reg_data1neg_4_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data1neg_4_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1neg_4_.C
0 1
1 0
.names ni_reg_valid2reg.BLIF reg_ID_1_5_.CE
1 1
0 0
.names clk.BLIF reg_ID_1_5_.C
1 1
0 0
.names NI_D_4_.BLIF ni_nires__reg_data3neg_4_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data3neg_4_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3neg_4_.C
0 1
1 0
.names nx148.BLIF reg_TXD_7_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_7_reg.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_5_.C
1 1
0 0
.names ni_reg_valid2reg.BLIF reg_ID_1_6_.CE
1 1
0 0
.names clk.BLIF reg_ID_1_6_.C
1 1
0 0
.names NI_D_5_.BLIF ni_nires__reg_data2neg_5_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data2neg_5_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2neg_5_.C
0 1
1 0
.names NI_D_5_.BLIF ni_nires__reg_data0neg_5_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data0neg_5_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0neg_5_.C
0 1
1 0
.names nx148.BLIF reg_TXD_6_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_6_reg.C
1 1
0 0
.names NI_D_5_.BLIF ni_nires__reg_data1neg_5_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data1neg_5_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1neg_5_.C
0 1
1 0
.names NI_D_5_.BLIF ni_nires__reg_data3neg_5_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data3neg_5_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3neg_5_.C
0 1
1 0
.names clk.BLIF ni_nires__reg_data_out_6_.C
1 1
0 0
.names NI_D_6_.BLIF ni_nires__reg_data2neg_6_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data2neg_6_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2neg_6_.C
0 1
1 0
.names NI_D_6_.BLIF ni_nires__reg_data0neg_6_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data0neg_6_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0neg_6_.C
0 1
1 0
.names nx148.BLIF reg_TXD_5_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_5_reg.C
1 1
0 0
.names NI_D_6_.BLIF ni_nires__reg_data1neg_6_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data1neg_6_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1neg_6_.C
0 1
1 0
.names NI_D_6_.BLIF ni_nires__reg_data3neg_6_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data3neg_6_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3neg_6_.C
0 1
1 0
.names clk.BLIF ni_nires__reg_data_out_7_.C
1 1
0 0
.names nx148.BLIF reg_TXD_4_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_4_reg.C
1 1
0 0
.names NI_D_7_.BLIF ni_nires__reg_data2neg_7_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data2neg_7_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2neg_7_.C
0 1
1 0
.names NI_D_7_.BLIF ni_nires__reg_data0neg_7_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data0neg_7_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0neg_7_.C
0 1
1 0
.names j2c__reg_shreg_4_.BLIF j2c__reg_creg1hm_2_.D
1 1
0 0
.names jTDI.BLIF j2c__reg_cmdreg_0_.BLIF j2c__reg_cmdreg_3_.BLIF \
j2c__reg_creg1hm_2_.CE
001 1
-1- 0
1-- 0
--0 0
.names j2c__nx0.BLIF j2c__reg_creg1hm_2_.C
1 1
0 0
.names NI_D_7_.BLIF ni_nires__reg_data1neg_7_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data1neg_7_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1neg_7_.C
0 1
1 0
.names j2c__reg_shreg_4_.BLIF j2c__reg_cmdreg_0_.D
1 1
0 0
.names jTDI.BLIF j2c__reg_cmdreg_0_.CE
1 1
0 0
.names j2c__nx0.BLIF j2c__reg_cmdreg_0_.C
1 1
0 0
.names j2c__reg_shreg_5_.BLIF j2c__reg_shreg_4_.D
1 1
0 0
.names jTCK.BLIF j2c__reg_shreg_4_.C
1 1
0 0
.names NI_D_7_.BLIF ni_nires__reg_data3neg_7_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data3neg_7_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3neg_7_.C
0 1
1 0
.names j2c__reg_shreg_6_.BLIF j2c__reg_shreg_5_.D
1 1
0 0
.names jTCK.BLIF j2c__reg_shreg_5_.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_8_.C
1 1
0 0
.names j2c__reg_shreg_7_.BLIF j2c__reg_shreg_6_.D
1 1
0 0
.names jTCK.BLIF j2c__reg_shreg_6_.C
1 1
0 0
.names jTDI.BLIF j2c__reg_shreg_7_.D
1 1
0 0
.names jTCK.BLIF j2c__reg_shreg_7_.C
1 1
0 0
.names NI_D_8_.BLIF ni_nires__reg_data2neg_8_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data2neg_8_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2neg_8_.C
0 1
1 0
.names j2c__nx0.BLIF j2c__reg_cmdreg_3_.C
1 1
0 0
.names NI_D_8_.BLIF ni_nires__reg_data0neg_8_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data0neg_8_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0neg_8_.C
0 1
1 0
.names j2c__reg_shreg_7_.BLIF j2c__reg_creg1hm_6_.D
1 1
0 0
.names jTDI.BLIF j2c__reg_cmdreg_0_.BLIF j2c__reg_cmdreg_3_.BLIF \
j2c__reg_creg1hm_6_.CE
001 1
-1- 0
1-- 0
--0 0
.names j2c__nx0.BLIF j2c__reg_creg1hm_6_.C
1 1
0 0
.names NI_D_8_.BLIF ni_nires__reg_data1neg_8_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data1neg_8_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1neg_8_.C
0 1
1 0
.names j2c__reg_shreg_6_.BLIF j2c__reg_creg1hm_5_.D
1 1
0 0
.names jTDI.BLIF j2c__reg_cmdreg_0_.BLIF j2c__reg_cmdreg_3_.BLIF \
j2c__reg_creg1hm_5_.CE
001 1
-1- 0
1-- 0
--0 0
.names j2c__nx0.BLIF j2c__reg_creg1hm_5_.C
1 1
0 0
.names j2c__reg_shreg_5_.BLIF j2c__reg_creg1hm_4_.D
1 1
0 0
.names jTDI.BLIF j2c__reg_cmdreg_0_.BLIF j2c__reg_cmdreg_3_.BLIF \
j2c__reg_creg1hm_4_.CE
001 1
-1- 0
1-- 0
--0 0
.names j2c__nx0.BLIF j2c__reg_creg1hm_4_.C
1 1
0 0
.names NI_D_8_.BLIF ni_nires__reg_data3neg_8_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data3neg_8_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3neg_8_.C
0 1
1 0
.names j2c__reg_shreg_5_.BLIF j2c__reg_shreg_6_.BLIF j2c__reg_shreg_7_.BLIF \
j2c__reg_creg1hm_3_.D
100 1
010 1
001 1
111 1
000 0
110 0
101 0
011 0
.names jTDI.BLIF j2c__reg_cmdreg_0_.BLIF j2c__reg_cmdreg_3_.BLIF \
j2c__reg_creg1hm_3_.CE
001 1
-1- 0
1-- 0
--0 0
.names j2c__nx0.BLIF j2c__reg_creg1hm_3_.C
1 1
0 0
.names clk.BLIF ni_nires__reg_data_out_9_.C
1 1
0 0
.names nx148.BLIF reg_TXD_3_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_3_reg.C
1 1
0 0
.names NI_D_9_.BLIF ni_nires__reg_data2neg_9_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data2neg_9_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2neg_9_.C
0 1
1 0
.names NI_D_9_.BLIF ni_nires__reg_data0neg_9_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data0neg_9_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0neg_9_.C
0 1
1 0
.names j2c__reg_shreg_4_.BLIF j2c__reg_shreg_6_.BLIF j2c__reg_shreg_7_.BLIF \
j2c__reg_creg1hm_1_.D
100 1
010 1
001 1
111 1
000 0
110 0
101 0
011 0
.names jTDI.BLIF j2c__reg_cmdreg_0_.BLIF j2c__reg_cmdreg_3_.BLIF \
j2c__reg_creg1hm_1_.CE
001 1
-1- 0
1-- 0
--0 0
.names j2c__nx0.BLIF j2c__reg_creg1hm_1_.C
1 1
0 0
.names NI_D_9_.BLIF ni_nires__reg_data1neg_9_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data1neg_9_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1neg_9_.C
0 1
1 0
.names nx148.BLIF reg_TXD_1_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_1_reg.C
1 1
0 0
.names NI_D_9_.BLIF ni_nires__reg_data3neg_9_.D
1 1
0 0
.names ni_nires__reg_gray_cntf_1_.BLIF ni_nires__reg_gray_cntf_0_.BLIF \
ni_nires__reg_data3neg_9_.CE
10 1
0- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data3neg_9_.C
0 1
1 0
.names clk.BLIF ni_nires__reg_data_out_10_.C
1 1
0 0
.names j2c__reg_shreg_4_.BLIF j2c__reg_shreg_5_.BLIF j2c__reg_shreg_7_.BLIF \
j2c__reg_creg1hm_0_.D
100 1
010 1
001 1
111 1
000 0
110 0
101 0
011 0
.names jTDI.BLIF j2c__reg_cmdreg_0_.BLIF j2c__reg_cmdreg_3_.BLIF \
j2c__reg_creg1hm_0_.CE
001 1
-1- 0
1-- 0
--0 0
.names j2c__nx0.BLIF j2c__reg_creg1hm_0_.C
1 1
0 0
.names NI_D_0_.BLIF ni_nires__reg_data2pos_0_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data2pos_0_.CE
11 1
0- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data2pos_0_.C
1 1
0 0
.names ni_nires__reg_gray_cnt_0_.BLIF ni_nires__reg_gray_cnt_1_.D
1 1
0 0
.names NI_STR.BLIF ni_nires__reg_gray_cnt_1_.C
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.D
0 1
1 0
.names NI_STR.BLIF ni_nires__reg_gray_cnt_0_.C
1 1
0 0
.names nx148.BLIF reg_TXD_2_reg.CE
1 1
0 0
.names clk.BLIF reg_TXD_2_reg.C
1 1
0 0
.names NI_D_0_.BLIF ni_nires__reg_data0pos_0_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data0pos_0_.CE
00 1
1- 0
-1 0
.names NI_STR.BLIF ni_nires__reg_data0pos_0_.C
1 1
0 0
.names NI_D_0_.BLIF ni_nires__reg_data1pos_0_.D
1 1
0 0
.names ni_nires__reg_gray_cnt_1_.BLIF ni_nires__reg_gray_cnt_0_.BLIF \
ni_nires__reg_data1pos_0_.CE
01 1
1- 0
-0 0
.names NI_STR.BLIF ni_nires__reg_data1pos_0_.C
1 1
0 0
.names SDA
 0
.names nx20.BLIF SDA.OE
1 1
0 0
.names nx12.BLIF SCL.OE
1 1
0 0
.names nx197.BLIF jTDO.OE
1 1
0 0
.names DIS_JTG.BLIF j2c__bitcnt_0_.BLIF j2c__bitcnt_1_.BLIF \
j2c__reg_cmdreg_2_.BLIF j2c__reg_cmdreg_1_.BLIF jTDO.X1
01111 1
1---- 0
-0--- 0
--0-- 0
---0- 0
----0 0
.names DIS_JTG.BLIF j2c__reg_cmdreg_0_.BLIF j2c__ix59.BLIF j2c__ix71.BLIF \
j2c__ix77.BLIF j2c__ix99.BLIF j2c__ix85.BLIF j2c__reg_creg0hm_3_.BLIF \
j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF j2c__ix45.BLIF \
j2c__bitcnt_0_.BLIF j2c__bitcnt_1_.BLIF j2c__bitcnt_2_.BLIF \
j2c__reg_cmdreg_2_.BLIF j2c__reg_cmdreg_1_.BLIF j2c__nx414.BLIF \
j2c__ix107.BLIF j2c__reg_creg0hm_0_.BLIF j2c__nx330.BLIF j2c__nx365.BLIF \
SDA.PIN.BLIF jTDO.X2
00------------00----0- 1
01------------00---1-- 1
0-------------011----- 1
0----------00010--1--- 1
0----------00110-1---- 1
0-------1--01010------ 1
0----1-----01110------ 1
0--------1-10010------ 1
0-----1----10110------ 1
0------1---11010------ 1
0---1------11110------ 1
0-00------011111------ 1
1--------------------1 1
1--------------------0 0
0-1-----------11------ 0
0--1----------11------ 0
0---------1---11------ 0
0----------0--11------ 0
0-----------0-11------ 0
0------------011------ 0
0-------------010----- 0
01------------00---0-- 0
00------------00----1- 0
0----0-----0111------- 0
0-----0----1011------- 0
0------0---1101------- 0
0-------0--0101------- 0
0--------0-1001------- 0
0----------0011--0---- 0
0----------0001---0--- 0
0---0------11110------ 0
.names int_SD2ANL.BLIF reg_TXD_15_reg.BLIF testpatt.BLIF reg_TXD_15_reg.D.X1
111 1
0-- 0
-0- 0
--0 0
.names int_SD2ANL.BLIF reg_TXD_15_reg.BLIF reg_TXD_14_reg.BLIF \
reg_TXD_13_reg.BLIF reg_TXD_12_reg.BLIF j2c__ix77.BLIF \
j2c__reg_creg0hm_3_.BLIF testpatt.BLIF ni_nires__reg_data_out_18_.BLIF \
ni_nires__reg_data_out_17_.BLIF nx1341.BLIF reg_TXD_15_reg.D.X2
1-----00--0 1
1----0101-- 1
1----110-1- 1
1-111--1--- 1
0---------- 0
--0----1--- 0
---0---1--- 0
----0--1--- 0
------00--1 0
-----0100-- 0
-----110-0- 0
.names int_SD2ANL.BLIF reg_TXD_11_reg.BLIF testpatt.BLIF reg_TXD_11_reg.D.X1
111 1
0-- 0
-0- 0
--0 0
.names int_SD2ANL.BLIF reg_TXD_11_reg.BLIF reg_TXD_10_reg.BLIF \
reg_TXD_9_reg.BLIF reg_TXD_8_reg.BLIF j2c__ix77.BLIF j2c__ix99.BLIF \
j2c__reg_creg0hm_3_.BLIF j2c__reg_creg0hm_2_.BLIF testpatt.BLIF \
ni_nires__reg_data_out_14_.BLIF ni_nires__reg_data_out_13_.BLIF nx1309.BLIF \
reg_TXD_11_reg.D.X2
1------000--0 1
1----00-101-- 1
1----001-01-- 1
1-----1-10-1- 1
1-----11-0-1- 1
1----1--10-1- 1
1----1-1-0-1- 1
1-000----1--- 1
0------------ 0
--1------1--- 0
---1-----1--- 0
----1----1--- 0
-----1-1-0-0- 0
------11-0-0- 0
-----1--10-0- 0
------1-10-0- 0
-------000--1 0
-----001-00-- 0
-----00-100-- 0
.names int_SD2ANL.BLIF j2c__reg_creg0hm_3_.BLIF j2c__reg_creg0hm_2_.BLIF \
testpatt.BLIF ni_nires__reg_data_out_13_.BLIF reg_TXD_10_reg.D.X1
10001 1
0---- 0
-1--- 0
--1-- 0
---1- 0
----0 0
.names int_SD2ANL.BLIF reg_TXD_10_reg.BLIF reg_TXD_9_reg.BLIF \
reg_TXD_8_reg.BLIF j2c__ix77.BLIF j2c__ix99.BLIF j2c__reg_creg0hm_3_.BLIF \
j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF testpatt.BLIF nx1039.BLIF \
j2c__reg_creg0hm_0_.BLIF ni_nires__reg_data_out_14_.BLIF \
ni_nires__reg_data_out_13_.BLIF ni_nires__reg_data_out_12_.BLIF \
reg_TXD_10_reg.D.X2
1-----1--01--1- 1
1------1-01--1- 1
1-----1--00---1 1
1------1-00---1 1
1-------1001-01 1
1---000000--01- 1
1---0000-0-001- 1
1---000000--10- 1
1---0000-0-010- 1
1-----001001-10 1
1000-----1----- 1
111------1----- 1
11-1-----1----- 1
0-------------- 0
-01------1----- 0
-0-1-----1----- 0
-100-----1----- 0
------1--01--0- 0
-------1-01--0- 0
------1--00---0 0
-------1-00---0 0
------1--0---00 0
-------1-0---00 0
----1-0000----- 0
-----10000----- 0
----1-00-0-0--- 0
-----100-0-0--- 0
--------1011-0- 0
--------10-1-00 0
------001011--- 0
------0000--11- 0
------00-0-011- 0
------0000--00- 0
------00-0-000- 0
------0010-1-11 0
.names int_SD2ANL.BLIF reg_TXD_7_reg.BLIF testpatt.BLIF reg_TXD_7_reg.D.X1
111 1
0-- 0
-0- 0
--0 0
.names int_SD2ANL.BLIF reg_TXD_7_reg.BLIF reg_TXD_6_reg.BLIF \
reg_TXD_5_reg.BLIF reg_TXD_4_reg.BLIF j2c__ix77.BLIF j2c__reg_creg0hm_3_.BLIF \
testpatt.BLIF nx1099.BLIF ni_nires__reg_data_out_8_.BLIF \
ni_nires__reg_data_out_7_.BLIF reg_TXD_7_reg.D.X2
1-----000-- 1
1----010-1- 1
1----110--1 1
1-000--1--- 1
0---------- 0
--1----1--- 0
---1---1--- 0
----1--1--- 0
------001-- 0
-----010-0- 0
-----110--0 0
.names int_SD2ANL.BLIF reg_TXD_3_reg.BLIF testpatt.BLIF reg_TXD_3_reg.D.X1
111 1
0-- 0
-0- 0
--0 0
.names int_SD2ANL.BLIF reg_TXD_3_reg.BLIF reg_TXD_2_reg.BLIF \
reg_TXD_1_reg.BLIF reg_TXD_0_reg.BLIF j2c__ix77.BLIF j2c__ix99.BLIF \
j2c__reg_creg0hm_3_.BLIF j2c__reg_creg0hm_2_.BLIF testpatt.BLIF nx1052.BLIF \
ni_nires__reg_data_out_4_.BLIF ni_nires__reg_data_out_3_.BLIF \
reg_TXD_3_reg.D.X2
1------0000-- 1
1----00-10-1- 1
1----001-0-1- 1
1-----1-10--1 1
1-----11-0--1 1
1----1--10--1 1
1----1-1-0--1 1
1-111----1--- 1
0------------ 0
--0------1--- 0
---0-----1--- 0
----0----1--- 0
-------0001-- 0
-----1-1-0--0 0
------11-0--0 0
-----1--10--0 0
------1-10--0 0
-----001-0-0- 0
-----00-10-0- 0
.names int_SD2ANL.BLIF j2c__reg_creg0hm_3_.BLIF j2c__reg_creg0hm_2_.BLIF \
testpatt.BLIF ni_nires__reg_data_out_3_.BLIF reg_TXD_2_reg.D.X1
10001 1
0---- 0
-1--- 0
--1-- 0
---1- 0
----0 0
.names int_SD2ANL.BLIF reg_TXD_2_reg.BLIF reg_TXD_1_reg.BLIF \
reg_TXD_0_reg.BLIF j2c__ix77.BLIF j2c__ix99.BLIF j2c__reg_creg0hm_3_.BLIF \
j2c__reg_creg0hm_2_.BLIF j2c__reg_creg0hm_1_.BLIF testpatt.BLIF nx1039.BLIF \
j2c__reg_creg0hm_0_.BLIF ni_nires__reg_data_out_4_.BLIF \
ni_nires__reg_data_out_3_.BLIF ni_nires__reg_data_out_2_.BLIF \
reg_TXD_2_reg.D.X2
1-----1--01--1- 1
1------1-01--1- 1
1-----1--00---1 1
1------1-00---1 1
1-------1001-01 1
1---000000--01- 1
1---0000-0-001- 1
1---000000--10- 1
1---0000-0-010- 1
1-----001001-10 1
1011-----1----- 1
110------1----- 1
11-0-----1----- 1
0-------------- 0
-00------1----- 0
-0-0-----1----- 0
-111-----1----- 0
------1--01--0- 0
-------1-01--0- 0
------1--00---0 0
-------1-00---0 0
------1--0---00 0
-------1-0---00 0
----1-0000----- 0
-----10000----- 0
----1-00-0-0--- 0
-----100-0-0--- 0
--------1011-0- 0
--------10-1-00 0
------001011--- 0
------0000--11- 0
------00-0-011- 0
------0000--00- 0
------00-0-000- 0
------0010-1-11 0
.names j2c__reg_creg1hm_2_.BLIF j2c__ix59.X1
0 1
1 0
.names j2c__reg_creg1hm_2_.BLIF j2c__reg_creg1hm_6_.BLIF \
j2c__reg_creg1hm_5_.BLIF j2c__reg_creg1hm_1_.BLIF j2c__ix59.X2
-000 1
-011 1
-101 1
-110 1
-111 0
-001 0
-010 0
-100 0
.names j2c__reg_creg1hm_2_.BLIF j2c__ix71.X1
0 1
1 0
.names j2c__reg_creg1hm_2_.BLIF j2c__reg_creg1hm_6_.BLIF \
j2c__reg_creg1hm_4_.BLIF j2c__reg_creg1hm_0_.BLIF j2c__ix71.X2
-000 1
-011 1
-101 1
-110 1
-111 0
-001 0
-010 0
-100 0
.names reg_ID_0_7_.BLIF reg_ID_0_7_.D.X1
1 1
0 0
.names reg_ID_0_7_.BLIF reg_ID_0_6_.BLIF reg_ID_0_5_.BLIF reg_ID_0_4_.BLIF \
reg_ID_0_3_.BLIF reg_ID_0_2_.BLIF reg_ID_0_1_.BLIF reg_ID_0_0_.BLIF \
reg_ID_0_7_.D.X2
-1111111 1
-0------ 0
--0----- 0
---0---- 0
----0--- 0
-----0-- 0
------0- 0
-------0 0
.names j2c__reg_creg1hm_6_.BLIF j2c__ix45.X1
0 1
1 0
.names j2c__reg_creg1hm_6_.BLIF j2c__reg_creg1hm_5_.BLIF \
j2c__reg_creg1hm_4_.BLIF j2c__reg_creg1hm_3_.BLIF j2c__ix45.X2
-000 1
-011 1
-101 1
-110 1
-111 0
-001 0
-010 0
-100 0
.names reg_ID_0_6_.BLIF reg_ID_0_6_.D.X1
1 1
0 0
.names reg_ID_0_6_.BLIF reg_ID_0_5_.BLIF reg_ID_0_4_.BLIF reg_ID_0_3_.BLIF \
reg_ID_0_2_.BLIF reg_ID_0_1_.BLIF reg_ID_0_0_.BLIF reg_ID_0_6_.D.X2
-111111 1
-0----- 0
--0---- 0
---0--- 0
----0-- 0
-----0- 0
------0 0
.names reg_ID_0_5_.BLIF reg_ID_0_5_.D.X1
1 1
0 0
.names reg_ID_0_5_.BLIF reg_ID_0_4_.BLIF reg_ID_0_3_.BLIF reg_ID_0_2_.BLIF \
reg_ID_0_1_.BLIF reg_ID_0_0_.BLIF reg_ID_0_5_.D.X2
-11111 1
-0---- 0
--0--- 0
---0-- 0
----0- 0
-----0 0
.names reg_ID_0_4_.BLIF reg_ID_0_4_.D.X1
1 1
0 0
.names reg_ID_0_4_.BLIF reg_ID_0_3_.BLIF reg_ID_0_2_.BLIF reg_ID_0_1_.BLIF \
reg_ID_0_0_.BLIF reg_ID_0_4_.D.X2
-1111 1
-0--- 0
--0-- 0
---0- 0
----0 0
.names reg_ID_1_6_.BLIF reg_ID_1_6_.D.X1
1 1
0 0
.names reg_ID_1_6_.BLIF reg_ID_1_5_.BLIF reg_ID_1_4_.BLIF reg_ID_1_3_.BLIF \
reg_ID_1_2_.BLIF reg_ID_1_1_.BLIF reg_ID_1_0_.BLIF nx96.BLIF reg_ID_1_6_.D.X2
-1111111 1
-0------ 0
--0----- 0
---0---- 0
----0--- 0
-----0-- 0
------0- 0
-------0 0
.names reg_ID_1_5_.BLIF reg_ID_1_5_.D.X1
1 1
0 0
.names reg_ID_1_5_.BLIF reg_ID_1_4_.BLIF reg_ID_1_3_.BLIF reg_ID_1_2_.BLIF \
reg_ID_1_1_.BLIF reg_ID_1_0_.BLIF nx96.BLIF reg_ID_1_5_.D.X2
-111111 1
-0----- 0
--0---- 0
---0--- 0
----0-- 0
-----0- 0
------0 0
.names reg_ID_1_4_.BLIF reg_ID_1_4_.D.X1
1 1
0 0
.names reg_ID_1_4_.BLIF reg_ID_1_3_.BLIF reg_ID_1_2_.BLIF reg_ID_1_1_.BLIF \
reg_ID_1_0_.BLIF nx96.BLIF reg_ID_1_4_.D.X2
-11111 1
-0---- 0
--0--- 0
---0-- 0
----0- 0
-----0 0
.names reg_ID_1_3_.BLIF reg_ID_1_3_.D.X1
1 1
0 0
.names reg_ID_1_3_.BLIF reg_ID_1_2_.BLIF reg_ID_1_1_.BLIF reg_ID_1_0_.BLIF \
nx96.BLIF reg_ID_1_3_.D.X2
-1111 1
-0--- 0
--0-- 0
---0- 0
----0 0
.names reg_ID_2_6_.BLIF reg_ID_2_6_.D.X1
1 1
0 0
.names reg_ID_2_6_.BLIF reg_ID_2_5_.BLIF reg_ID_2_4_.BLIF reg_ID_2_3_.BLIF \
reg_ID_2_2_.BLIF reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF reg_ID_2_6_.D.X2
-111111 1
-0----- 0
--0---- 0
---0--- 0
----0-- 0
-----0- 0
------0 0
.names reg_ID_2_5_.BLIF reg_ID_2_5_.D.X1
1 1
0 0
.names reg_ID_2_5_.BLIF reg_ID_2_4_.BLIF reg_ID_2_3_.BLIF reg_ID_2_2_.BLIF \
reg_ID_2_1_.BLIF reg_ID_2_0_.BLIF reg_ID_2_5_.D.X2
-11111 1
-0---- 0
--0--- 0
---0-- 0
----0- 0
-----0 0
.names reg_ID_2_4_.BLIF reg_ID_2_4_.D.X1
1 1
0 0
.names reg_ID_2_4_.BLIF reg_ID_2_3_.BLIF reg_ID_2_2_.BLIF reg_ID_2_1_.BLIF \
reg_ID_2_0_.BLIF reg_ID_2_4_.D.X2
-1111 1
-0--- 0
--0-- 0
---0- 0
----0 0
.names reg_ID_3_6_.BLIF reg_ID_3_6_.D.X1
1 1
0 0
.names reg_ID_3_6_.BLIF reg_ID_3_5_.BLIF reg_ID_3_4_.BLIF reg_ID_3_3_.BLIF \
reg_ID_3_2_.BLIF reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF reg_ID_3_6_.D.X2
-111111 1
-0----- 0
--0---- 0
---0--- 0
----0-- 0
-----0- 0
------0 0
.names reg_ID_3_5_.BLIF reg_ID_3_5_.D.X1
1 1
0 0
.names reg_ID_3_5_.BLIF reg_ID_3_4_.BLIF reg_ID_3_3_.BLIF reg_ID_3_2_.BLIF \
reg_ID_3_1_.BLIF reg_ID_3_0_.BLIF reg_ID_3_5_.D.X2
-11111 1
-0---- 0
--0--- 0
---0-- 0
----0- 0
-----0 0
.names reg_ID_3_4_.BLIF reg_ID_3_4_.D.X1
1 1
0 0
.names reg_ID_3_4_.BLIF reg_ID_3_3_.BLIF reg_ID_3_2_.BLIF reg_ID_3_1_.BLIF \
reg_ID_3_0_.BLIF reg_ID_3_4_.D.X2
-1111 1
-0--- 0
--0-- 0
---0- 0
----0 0
.names reg_ni_pattcount_4_.BLIF reg_ni_pattcount_4_.D.X1
1 1
0 0
.names reg_ni_pattcount_2_.BLIF reg_ni_pattcount_1_.BLIF \
reg_ni_pattcount_0_.BLIF reg_ni_pattcount_4_.BLIF reg_ni_pattcount_3_.BLIF \
reg_ni_pattcount_4_.D.X2
111-1 1
0---- 0
-0--- 0
--0-- 0
----0 0
.names ni_reg_valid2reg.BLIF reg_TXD_8_reg.BLIF ni_reg_ce_prty_bit_neg.D.X1
10 1
0- 0
-1 0
.names ni_reg_valid2reg.BLIF reg_TXD_8_reg.BLIF ix449.BLIF ix521.BLIF \
ix523.BLIF ni_reg_ce_prty_bit_neg.D.X2
1-000 1
1-011 1
1-101 1
1-110 1
0---- 0
--111 0
--001 0
--010 0
--100 0
.names reg_TXD_15_reg.BLIF ix449.X1
0 1
1 0
.names reg_TXD_15_reg.BLIF reg_TXD_14_reg.BLIF reg_TXD_13_reg.BLIF \
ni_reg_prty_bit_neg_r.BLIF ix449.X2
-000 1
-011 1
-101 1
-110 1
-111 0
-001 0
-010 0
-100 0
.names reg_TXD_4_reg.BLIF ix865.X1
0 1
1 0
.names reg_TXD_4_reg.BLIF reg_TXD_3_reg.BLIF reg_TXD_2_reg.BLIF \
reg_TXD_1_reg.BLIF ix865.X2
-000 1
-011 1
-101 1
-110 1
-111 0
-001 0
-010 0
-100 0
.names reg_TXD_6_reg.BLIF ix867.X1
0 1
1 0
.names reg_TXD_6_reg.BLIF reg_TXD_5_reg.BLIF ix793.BLIF ix865.BLIF ix867.X2
-000 1
-011 1
-101 1
-110 1
-111 0
-001 0
-010 0
-100 0
.end