ispLEVER 5.0.01.73.31.05_Starter Fitter Report File
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Project Name : oase Project Path : U:\REFERENCE\SIM\PROJECTS\ORI\lattice Project Fitted on : Tue May 16 16:23:00 2006 Device : M4256_64 Package : 100 GLB Input Mux Size : 33 Available Blocks : 16 Speed : -3 Part Number : LC4256V-3T100C Source Format : EDIF Project 'oase' Fit Successfully! Compilation_Times
Prefit Time 0 secs Load Design Time 0.12 secs Partition Time 3.08 secs Place Time 0.38 secs Route Time 0.05 secs Total Fit Time 00:00:03 Design_Summary
Total Input Pins 18 Total Logic Functions 247 Total Output Pins 29 Total Bidir I/O Pins 5 Total Buried Nodes 213 Total Flip-Flops 197 Total D Flip-Flops 187 Total T Flip-Flops 10 Total Latches 0 Total Product Terms 1007 Total Reserved Pins 0 Total Locked Pins 52 Total Locked Nodes 0 Total Unique Output Enables 4 Total Unique Clocks 6 Total Unique Clock Enables 17 Total Unique Resets 5 Total Unique Presets 2 Fmax Logic Levels 3 Device_Resource_Summary
Device Total Used Not Used Utilization ----------------------------------------------------------------------- Dedicated Pins Clock/Input Pins 4 0 4 --> 0 Input-Only Pins 6 0 6 --> 0 I/O / Enable Pins 2 0 2 --> 0 I/O Pins 62 52 10 --> 83 Logic Functions 256 247 9 --> 96 Input Registers 64 0 64 --> 0 GLB Inputs 576 457 119 --> 79 Logical Product Terms 1280 833 447 --> 65 Occupied GLBs 16 16 0 --> 100 Macrocells 256 247 9 --> 96 Product Terms 1316 805 511 --> 61 Control Product Terms: GLB Clock/Clock Enables 16 16 0 --> 100 GLB Reset/Presets 16 0 16 --> 0 Macrocell Clocks 256 56 200 --> 21 Macrocell Clock Enables 256 147 109 --> 57 Macrocell Enables 256 0 256 --> 0 Macrocell Resets 256 154 102 --> 60 Macrocell Presets 256 1 255 --> 0 Global Routing Pool 324 252 72 --> 77 GRP from IFB .. 20 .. --> .. (from input signals) .. 18 .. --> .. (from output signals) .. 0 .. --> .. (from bidir signals) .. 2 .. --> .. GRP from MFB .. 232 .. --> .. ---------------------------------------------------------------------- <Note> 1 : The available PT is the product term that has not been used. <Note> 2 : IFB is I/O feedback. <Note> 3 : MFB is macrocell feedback. GLB_Resource_Summary
# of PT --- Fanin --- I/O Input Macrocells Macrocells Logic clusters Unique Shared Total Pins Regs Used Inaccessible available PTs used ------------------------------------------------------------------------------------------- Maximum GLB 36 *(1) 8 -- -- 16 80 16 ------------------------------------------------------------------------------------------- GLB A 22 8 30 3/4 0 16 0 0 43 16 GLB B 22 7 29 2/4 0 16 0 0 49 16 GLB C 7 9 16 3/4 0 16 0 0 39 16 GLB D 20 9 29 4/4 0 16 0 0 47 16 ------------------------------------------------------------------------------------------- GLB E 1 10 11 4/4 0 16 0 0 37 16 GLB F 9 23 32 2/4 0 15 1 0 60 16 GLB G 24 9 33 3/4 0 16 0 0 52 16 GLB H 16 14 30 2/4 0 16 0 0 53 15 ------------------------------------------------------------------------------------------- GLB I 26 7 33 4/4 0 15 0 1 37 11 GLB J 0 13 13 4/4 0 16 0 0 40 15 GLB K 7 27 34 4/4 0 16 0 0 51 15 GLB L 8 26 34 4/4 0 14 2 0 75 16 ------------------------------------------------------------------------------------------- GLB M 11 23 34 4/4 0 12 0 4 61 16 GLB N 12 22 34 4/4 0 15 0 1 62 15 GLB O 12 21 33 4/4 0 16 0 0 67 15 GLB P 11 21 32 1/4 0 16 0 0 60 16 ------------------------------------------------------------------------------------------- TOTALS: 208 249 457 52/64 0 247 3 6 833 246 <Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB. <Note> 2 : Four rightmost columns above reflect last status of the placement process. GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell Clk/CE Rst/Pr | Clock CE Enable Reset Preset ------------------------------------------------------------------------------ Maximum GLB 1 1 16 16 16 16 16 ============================================================================== GLB A 1 0 5 8 0 13 0 GLB B 1 0 7 13 0 14 0 GLB C 1 0 6 16 0 16 0 GLB D 1 0 4 11 0 15 0 ------------------------------------------------------------------------------ GLB E 1 0 6 9 0 6 0 GLB F 1 0 0 13 0 0 0 GLB G 1 0 6 6 0 16 0 GLB H 1 0 6 6 0 6 1 ------------------------------------------------------------------------------ GLB I 1 0 0 0 0 8 0 GLB J 1 0 4 11 0 11 0 GLB K 1 0 0 5 0 11 0 GLB L 1 0 4 10 0 10 0 ------------------------------------------------------------------------------ GLB M 1 0 0 3 0 4 0 GLB N 1 0 5 12 0 13 0 GLB O 1 0 3 11 0 11 0 GLB P 1 0 0 13 0 0 0 ------------------------------------------------------------------------------ <Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB. Optimizer_and_Fitter_Options
Pin Assignment : Yes Group Assignment : No Pin Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : Yes Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : No Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : FMAX Fmax_Logic_Level : 1 D/T Synthesis : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 80 Max Symbols : 24 @Utilization_options Max. % of Macrocells used : 100 @Usercode (HEX) @IO_Types Default = LVCMOS18 (2) @Output_Slew_Rate Default = FAST (2) @Power Default = HIGH (2) @Pull Default = PULLUP_UP (2) @Fast_Bypass Default = None (2) @ORP_Bypass Default = None @Input_Registers Default = None (2) @Register_Powerup Default = None Device Options: <Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. <Note> 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Buried Signal Lists. Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal| Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name ---------------------------------------------------------------------------------------- 1 | GND | - | | | | | 2 | TDI | - | | | | | 3 | I_O | 0 |C12 | * |LVCMOS33 | Input |reset_n 4 | I_O | 0 |C10 | * |LVCMOS33 |Tri-Out|SD2ANL 5 | I_O | 0 |C6 | | | | 6 | I_O | 0 |C2 | * |LVCMOS33 | Input |NI_STR 7 |GNDIO0 | - | | | | | 8 | I_O | 0 |D12 | * |LVCMOS33 | Input |NI_D_9_ 9 | I_O | 0 |D10 | * |LVCMOS33 | Input |NI_D_8_ 10 | I_O | 0 |D6 | * |LVCMOS33 | Input |NI_D_7_ 11 | I_O | 0 |D4 | * |LVCMOS33 | Input |NI_D_6_ 12 | IN0 | 0 | | | | | 13 |VCCIO0 | - | | | | | 14 | I_O | 0 |E4 | * |LVCMOS33 | Input |NI_D_5_ 15 | I_O | 0 |E6 | * |LVCMOS33 | Input |NI_D_4_ 16 | I_O | 0 |E10 | * |LVCMOS33 | Input |NI_D_3_ 17 | I_O | 0 |E12 | * |LVCMOS33 | Input |NI_D_2_ 18 |GNDIO0 | - | | | | | 19 | I_O | 0 |F2 | * |LVCMOS33 | Input |NI_D_1_ 20 | I_O | 0 |F6 | * |LVCMOS33 | Input |NI_D_0_ 21 | I_O | 0 |F10 | | | | 22 | I_O | 0 |F12 | | | | 23 | IN1 | 0 | | | | | 24 | TCK | - | | | | | 25 | VCC | - | | | | | 26 | GND | - | | | | | 27 | IN2 | 0 | | | | | 28 | I_O | 0 |G12 | * |LVCMOS33 | Input |DIS_JTG 29 | I_O | 0 |G10 | | | | 30 | I_O | 0 |G6 | * |LVCMOS33 | Input |jTCK 31 | I_O | 0 |G2 | * |LVCMOS33 | Input |jTMS 32 |GNDIO0 | - | | | | | 33 |VCCIO0 | - | | | | | 34 | I_O | 0 |H12 | * |LVCMOS33 | Input |jTDI 35 | I_O | 0 |H10 | * |LVCMOS33 |Tri-Out|jTDO 36 | I_O | 0 |H6 | | | | 37 | I_O | 0 |H2 | | | | 38 |INCLK1 | 0 | | | | | 39 |INCLK2 | 1 | | | | | 40 | VCC | - | | | | | 41 | I_O | 1 |I2 | * |LVCMOS33 | Output|LED_8_ 42 | I_O | 1 |I6 | * |LVCMOS33 | Output|LED_9_ 43 | I_O | 1 |I10 | * |LVCMOS33 | Output|LED_10_ 44 | I_O | 1 |I12 | * |LVCMOS33 | Output|TESTEN 45 |VCCIO1 | - | | | | | 46 |GNDIO1 | - | | | | | 47 | I_O | 1 |J2 | * |LVCMOS33 | Bidir |PRBSEN 48 | I_O | 1 |J6 | * |LVCMOS33 | Output|LCKREFN 49 | I_O | 1 |J10 | * |LVCMOS33 | Output|ENABLE 50 | I_O | 1 |J12 | * |LVCMOS33 | Output|TX_ER 51 | GND | - | | | | | 52 | TMS | - | | | | | 53 | I_O | 1 |K12 | * |LVCMOS33 | Output|LOOPEN 54 | I_O | 1 |K10 | * |LVCMOS33 | Output|TX_EN 55 | I_O | 1 |K6 | * |LVCMOS33 | Output|TXD_15_ 56 | I_O | 1 |K2 | * |LVCMOS33 | Output|TXD_14_ 57 |GNDIO1 | - | | | | | 58 | I_O | 1 |L12 | * |LVCMOS33 | Output|TXD_13_ 59 | I_O | 1 |L10 | * |LVCMOS33 | Output|TXD_12_ 60 | I_O | 1 |L6 | * |LVCMOS33 | Output|TXD_11_ 61 | I_O | 1 |L4 | * |LVCMOS33 | Output|TXD_10_ 62 | IN3 | 1 | | | | | 63 |VCCIO1 | - | | | | | 64 | I_O | 1 |M4 | * |LVCMOS33 | Output|TXD_9_ 65 | I_O | 1 |M6 | * |LVCMOS33 | Output|TXD_8_ 66 | I_O | 1 |M10 | * |LVCMOS33 | Input |clk 67 | I_O | 1 |M12 | * |LVCMOS33 | Output|TXD_7_ 68 |GNDIO1 | - | | | | | 69 | I_O | 1 |N2 | * |LVCMOS33 | Output|TXD_6_ 70 | I_O | 1 |N6 | * |LVCMOS33 | Output|TXD_5_ 71 | I_O | 1 |N10 | * |LVCMOS33 | Output|TXD_4_ 72 | I_O | 1 |N12 | * |LVCMOS33 | Output|TXD_3_ 73 | IN4 | 1 | | | | | 74 | TDO | - | | | | | 75 | VCC | - | | | | | 76 | GND | - | | | | | 77 | IN5 | 1 | | | | | 78 | I_O | 1 |O12 | * |LVCMOS33 | Output|TXD_2_ 79 | I_O | 1 |O10 | * |LVCMOS33 | Output|TXD_1_ 80 | I_O | 1 |O6 | * |LVCMOS33 | Output|TXD_0_ 81 | I_O | 1 |O2 | * |LVCMOS33 | Input |FAULT 82 |GNDIO1 | - | | | | | 83 |VCCIO1 | - | | | | | 84 | I_O | 1 |P12 | * |LVCMOS33 | Output|EN 85 | I_O | 1 |P10 | | | | 86 | I_O | 1 |P6 | | | | 87 | I_O/OE| 1 |P2 | | | | 88 |INCLK3 | 1 | | | | | 89 |INCLK0 | 0 | | | | | 90 | VCC | - | | | | | 91 | I_O/OE| 0 |A2 | | | | 92 | I_O | 0 |A6 | * |LVCMOS33 | Output|LED_5_ 93 | I_O | 0 |A10 | * |LVCMOS33 | Output|LED_6_ 94 | I_O | 0 |A12 | * |LVCMOS33 | Output|LED_7_ 95 |VCCIO0 | - | | | | | 96 |GNDIO0 | - | | | | | 97 | I_O | 0 |B2 | | | | 98 | I_O | 0 |B6 | | | | 99 | I_O | 0 |B10 | * |LVCMOS33 |Tri-Out|SCL 100 | I_O | 0 |B12 | * |LVCMOS33 | Bidir |SDA ---------------------------------------------------------------------------------------- <Note> GLB Pad : This notation refers to the GLB I/O pad number in the device. <Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins). <Note> Pin Type : ClkIn : Dedicated input or clock pin CLK : Dedicated clock pin I_O : Input/Output pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected Input_Signal_List
Input Pin Fanout Pin GLB Type Pullup Signal ------------------------------------------------- 28 G I/O 4 -----F-HI------P Up DIS_JTG 81 O I/O 2 A------H-------- Up FAULT 20 F I/O 1 -B-------------- Up NI_D_0_ 19 F I/O 2 ---D-------L---- Up NI_D_1_ 17 E I/O 2 A-----G--------- Up NI_D_2_ 16 E I/O 2 --C--------L---- Up NI_D_3_ 15 E I/O 2 -BC------------- Up NI_D_4_ 14 E I/O 2 ---------J----O- Up NI_D_5_ 11 D I/O 2 -------------NO- Up NI_D_6_ 10 D I/O 2 ---D---------N-- Up NI_D_7_ 9 D I/O 2 A-C------------- Up NI_D_8_ 8 D I/O 3 --CD-----J------ Up NI_D_9_ 6 C I/O 9 ABCD--G--J-L-NO- Up NI_STR 66 M I/O 12 AB-D-FG-I-KLMNOP Up clk 30 G I/O 2 ----E--H-------- Up jTCK 34 H I/O 4 --C-E--H-J------ Up jTDI 31 G I/O 1 --------I------- Up jTMS 3 C I/O 5 --C-E--HIJ------ Up reset_n ------------------------------------------------- Output_Signal_List
I C P R P O Output N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal -------------------------------------------------------------------------------- 84 P 0 - 1 1 COM ---------------- Slow Up EN 49 J 0 - 1 1 COM ---------------- Slow Up ENABLE 48 J 0 - 0 1 COM ---------------- Slow Up LCKREFN 43 I 0 - 1 1 COM ---------------- Slow Up LED_10_ 92 A 0 - 0 1 COM ---------------- Slow Up LED_5_ 93 A 1 1 1 1 COM ---------------- Slow Up LED_6_ 94 A 1 1 1 1 COM ---------------- Slow Up LED_7_ 41 I 0 - 1 1 COM ---------------- Slow Up LED_8_ 42 I 0 - 0 1 COM ---------------- Slow Up LED_9_ 53 K 0 - 0 1 COM ---------------- Slow Up LOOPEN 99 B 0 - 0 1 COM * ---------------- Slow Up SCL 4 C 6 1 4 1 DFF * R * * ---------------- Fast Up SD2ANL 44 I 0 - 0 1 COM ---------------- Slow Up TESTEN 80 O 15 3 9 2 DFF * R * 2 -------------NO- Fast Up TXD_0_ 61 L 17 2 16 4 DFF * R * 2 ---D-------L---- Fast Up TXD_10_ 60 L 16 2 11 3 DFF * R * 2 ---D-------L---- Fast Up TXD_11_ 59 L 15 2 14 3 DFF * R * 3 ---D------KL---- Fast Up TXD_12_ 58 L 11 2 7 2 DFF * R * 2 ----------KL---- Fast Up TXD_13_ 56 K 15 2 10 2 DFF * R * 1 ----------K----- Fast Up TXD_14_ 55 K 12 2 6 2 DFF * R * 1 ----------K----- Fast Up TXD_15_ 79 O 15 2 10 3 DFF * R * 2 -------------NO- Fast Up TXD_1_ 78 O 17 2 16 4 DFF * R * 2 -------------NO- Fast Up TXD_2_ 72 N 11 2 7 2 DFF * R * 1 -------------N-- Fast Up TXD_3_ 71 N 10 2 8 2 DFF * R * 2 ------------MN-- Fast Up TXD_4_ 70 N 11 2 7 2 DFF * R * 2 ------------MN-- Fast Up TXD_5_ 69 N 15 2 11 3 DFF * R * 2 ------------MN-- Fast Up TXD_6_ 67 M 12 2 6 2 DFF * R * 1 ------------M--- Fast Up TXD_7_ 65 M 15 3 8 3 DFF * R * 3 A----------LM--- Fast Up TXD_8_ 64 M 15 2 9 2 DFF * R * 3 ---D-------LM--- Fast Up TXD_9_ 54 K 8 1 2 1 DFF * R 5 A----F----K--N-P Fast Up TX_EN 50 J 0 - 0 1 COM ---------------- Slow Up TX_ER 35 H 16 2 10 2 COM * ---------------- Slow Up jTDO -------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Bidir_Signal_List
I C P R P O Bidir N L Mc R E U C O F B Fanout Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal ------------------------------------------------------------------------------- 47 J 6 1 4 2 DFF * R * * 1 A--------------- Slow Up PRBSEN 100 B 0 - 0 1 COM * 1 -------H-------- Slow Up SDA ------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation FP = Fast path used OBP = ORP bypass used Buried_Signal_List
I C P R P Node N L Mc R E U C I F Fanout Mc GLB P LL PTs S Type E S P E R P Signal ---------------------------------------------------------------------------------- 5 P 4 1 2 1 DFF * R * 2 ----------K----P ID_0_0_ 12 P 5 1 3 1 DFF * R * 2 ----------K----P ID_0_1_ 6 K 6 1 5 1 DFF * R * 2 ----------K----P ID_0_2_ 7 P 7 1 5 2 DFF * R * 2 ----------K----P ID_0_3_ 2 I 2 - 1 1 COM 3 -----F----K----P ID_0_3__0 13 K 8 1 4 1 DFF * R * 2 ----------K----P ID_0_4_ 0 P 8 1 2 1 TFF * R * 2 ----------K----P ID_0_5_ 15 P 9 1 2 1 TFF * R * 2 ----------K----P ID_0_6_ 14 K 10 1 3 1 TFF * R * 2 -------H--K----- ID_0_7_ 14 P 5 2 3 1 DFF * R * 2 -----F---------P ID_1_0_ 8 F 6 2 4 2 DFF * R * 1 -----F---------- ID_1_1_ 2 F 7 2 5 1 DFF * R * 1 -----F---------- ID_1_2_ 11 F 8 2 3 1 DFF * R * 1 -----F---------- ID_1_3_ 15 F 8 2 2 1 TFF * R * 1 -----F---------- ID_1_4_ 14 F 9 2 2 1 TFF * R * 1 -----F---------- ID_1_5_ 1 F 10 2 2 2 TFF * R * 1 -----F---------- ID_1_6_ 11 P 4 1 2 1 DFF * R * 1 ---------------P ID_2_0_ 13 P 5 1 3 1 DFF * R * 1 ---------------P ID_2_1_ 9 P 6 1 4 2 DFF * R * 1 ---------------P ID_2_2_ 8 P 7 1 5 2 DFF * R * 1 ---------------P ID_2_3_ 10 P 8 1 3 2 DFF * R * 1 ---------------P ID_2_4_ 1 P 8 1 2 1 TFF * R * 1 ---------------P ID_2_5_ 2 P 9 1 2 1 TFF * R * 1 ---------------P ID_2_6_ 5 F 4 1 2 1 DFF * R * 1 -----F---------- ID_3_0_ 13 F 5 1 3 1 DFF * R * 1 -----F---------- ID_3_1_ 10 F 6 1 4 1 DFF * R * 1 -----F---------- ID_3_2_ 4 F 7 1 5 2 DFF * R * 1 -----F---------- ID_3_3_ 12 F 8 1 3 1 DFF * R * 1 -----F---------- ID_3_4_ 9 F 8 1 2 1 TFF * R * 1 -----F---------- ID_3_5_ 0 F 9 1 2 1 TFF * R * 1 -----F---------- ID_3_6_ 9 K 4 - 5 2 COM 1 A--------------- ix1373 5 D 4 - 5 1 COM 1 A--------------- ix1379 10 M 4 - 5 1 COM 1 -------------N-- ix1693 8 N 4 - 5 1 COM 1 -------------N-- ix1699 5 H 3 1 3 1 DFF * R 3 -----F-H-------P j2c_bitcnt_0_ 3 H 4 1 4 2 DFF * R 3 -----F-H-------P j2c_bitcnt_1_ 14 H 5 1 5 1 DFF * R 1 -------H-------- j2c_bitcnt_2_ 10 E 4 1 2 1 DFF * * S * 4 --C-E--H-J------ j2c_reg_cmdreg_0_ 7 H 4 1 2 1 DFF * * S * 3 -----F-H-------P j2c_reg_cmdreg_1_ 8 E 4 1 2 1 DFF * * S * 3 -----F-H-------P j2c_reg_cmdreg_2_ 1 E 4 1 1 1 DFF * R 4 --C-E--H-J------ j2c_reg_cmdreg_3_ 13 J 6 1 4 2 DFF * R * 7 -B--------KLMNOP j2c_reg_creg0hm_0_ 13 E 6 1 2 1 DFF * R * 7 -B--------KLMNOP j2c_reg_creg0hm_1_ 15 J 6 1 4 2 DFF * R * 7 -B--------KLMNOP j2c_reg_creg0hm_2_ 10 H 6 1 2 1 DFF * R * 7 -B--------KLMNOP j2c_reg_creg0hm_3_ 14 E 6 1 2 1 DFF * R * 5 -B---------LM-OP j2c_reg_creg0hm_4_ 9 H 6 1 2 1 DFF * R * 6 -B-----H---LM-OP j2c_reg_creg0hm_5_ 12 E 6 1 2 1 DFF * R * 7 -B-----H---LMNOP j2c_reg_creg0hm_6_ 11 E 6 1 2 1 DFF * R * 7 -B-----H--KLMNO- j2c_reg_creg0hm_7_ 14 J 6 1 4 2 DFF * R * 1 -----F---------- j2c_reg_creg1hm_0_ 8 H 6 1 2 1 DFF * R * 6 -----F----KLMNO- j2c_reg_creg1hm_3_ 0 E 6 1 2 1 DFF * R * 1 -----F---------- j2c_reg_creg1hm_4_ 11 H 6 1 2 2 DFF * R * 1 -----F---------- j2c_reg_creg1hm_5_ 15 E 6 1 2 1 DFF * R * 1 -----F---------- j2c_reg_creg1hm_6_ 9 E 6 1 2 1 DFF * R * 2 -B-----H-------- j2c_reg_creg1hm_7_reg 15 H 6 1 4 1 DFF * * S * 1 --------I------- j2c_reg_rstout_n_i 13 H 5 - 2 1 COM 1 -------H-------- j2c_reg_rstout_n_i_0 7 E 2 1 3 1 DFF * R 1 ---------J------ j2c_reg_shreg_0_ 6 E 2 1 3 1 DFF * R 2 --C-E----------- j2c_reg_shreg_1_ 6 H 2 1 3 1 DFF * R 2 ----E----J------ j2c_reg_shreg_2_ 5 E 2 1 3 1 DFF * R 1 -------H-------- j2c_reg_shreg_3_ 4 H 2 1 3 1 DFF * R 1 ----E----------- j2c_reg_shreg_4_ 2 E 2 1 3 2 DFF * R 1 -------H-------- j2c_reg_shreg_5_ 3 E 2 1 3 1 DFF * R 1 ----E----------- j2c_reg_shreg_6_ 4 E 2 - 3 1 DFF * R 1 ----E----------- j2c_reg_shreg_7_ 1 I 3 1 1 1 DFF * R 2 ------G--J------ ni_nires_reg_clear_n_i 4 B 4 - 2 2 DFF * R * 1 ------G--------- ni_nires_reg_data0neg_0_ 10 D 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data0neg_1_ 10 G 4 - 3 1 DFF * R * 1 ------G--------- ni_nires_reg_data0neg_2_ 5 C 4 - 2 1 DFF * R * 1 ---D------------ ni_nires_reg_data0neg_3_ 14 B 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data0neg_4_ 14 O 4 - 2 2 DFF * R * 1 ---D------------ ni_nires_reg_data0neg_5_ 3 O 4 - 2 2 DFF * R * 1 ---D------------ ni_nires_reg_data0neg_6_ 14 D 4 - 2 2 DFF * R * 1 --------I------- ni_nires_reg_data0neg_7_ 10 C 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data0neg_8_ 2 D 4 - 2 2 DFF * R * 1 --------I------- ni_nires_reg_data0neg_9_ 5 B 4 - 3 2 DFF * R * 1 ---D------------ ni_nires_reg_data0pos_0_ 3 L 4 - 2 1 DFF * R * 1 ------G--------- ni_nires_reg_data0pos_1_ 12 A 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data0pos_2_ 1 C 4 - 3 1 DFF * R * 1 --------I------- ni_nires_reg_data0pos_3_ 3 C 4 - 3 1 DFF * R * 1 ------G--------- ni_nires_reg_data0pos_4_ 4 J 4 - 3 2 DFF * R * 1 --------I------- ni_nires_reg_data0pos_5_ 4 N 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data0pos_6_ 13 N 4 - 2 1 DFF * R * 1 ------G--------- ni_nires_reg_data0pos_7_ 8 A 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data0pos_8_ 0 J 4 - 3 1 DFF * R * 1 ------G--------- ni_nires_reg_data0pos_9_ 11 B 4 - 2 1 DFF * R * 1 ------G--------- ni_nires_reg_data1neg_0_ 11 D 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data1neg_1_ 11 G 4 - 3 1 DFF * R * 1 ------G--------- ni_nires_reg_data1neg_2_ 6 C 4 - 2 1 DFF * R * 1 ---D------------ ni_nires_reg_data1neg_3_ 15 B 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data1neg_4_ 15 O 4 - 2 1 DFF * R * 1 ---D------------ ni_nires_reg_data1neg_5_ 4 O 4 - 2 1 DFF * R * 1 ---D------------ ni_nires_reg_data1neg_6_ 15 D 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data1neg_7_ 11 C 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data1neg_8_ 3 D 4 - 2 2 DFF * R * 1 --------I------- ni_nires_reg_data1neg_9_ 6 B 4 - 3 1 DFF * R * 1 ---D------------ ni_nires_reg_data1pos_0_ 4 L 4 - 2 1 DFF * R * 1 ------G--------- ni_nires_reg_data1pos_1_ 13 A 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data1pos_2_ 11 L 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data1pos_3_ 4 C 4 - 3 1 DFF * R * 1 ------G--------- ni_nires_reg_data1pos_4_ 5 J 4 - 3 2 DFF * R * 1 --------I------- ni_nires_reg_data1pos_5_ 5 N 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data1pos_6_ 14 N 4 - 2 1 DFF * R * 1 ------G--------- ni_nires_reg_data1pos_7_ 9 A 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data1pos_8_ 0 C 4 - 3 1 DFF * R * 1 ------G--------- ni_nires_reg_data1pos_9_ 12 B 4 - 2 1 DFF * R * 1 ------G--------- ni_nires_reg_data2neg_0_ 12 D 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data2neg_1_ 12 G 4 - 3 1 DFF * R * 1 ------G--------- ni_nires_reg_data2neg_2_ 7 C 4 - 2 1 DFF * R * 1 ---D------------ ni_nires_reg_data2neg_3_ 9 C 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data2neg_4_ 0 O 4 - 2 1 DFF * R * 1 ---D------------ ni_nires_reg_data2neg_5_ 5 O 4 - 2 1 DFF * R * 1 ---D------------ ni_nires_reg_data2neg_6_ 0 D 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data2neg_7_ 12 C 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data2neg_8_ 14 C 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data2neg_9_ 7 B 4 - 3 1 DFF * R * 1 ---D------------ ni_nires_reg_data2pos_0_ 7 L 4 - 2 1 DFF * R * 1 ------G--------- ni_nires_reg_data2pos_1_ 14 A 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data2pos_2_ 12 L 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data2pos_3_ 9 B 4 - 3 1 DFF * R * 1 ------G--------- ni_nires_reg_data2pos_4_ 6 J 4 - 3 1 DFF * R * 1 --------I------- ni_nires_reg_data2pos_5_ 7 N 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data2pos_6_ 15 N 4 - 2 1 DFF * R * 1 ------G--------- ni_nires_reg_data2pos_7_ 10 A 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data2pos_8_ 1 J 4 - 3 2 DFF * R * 1 ------G--------- ni_nires_reg_data2pos_9_ 13 B 4 - 2 1 DFF * R * 1 ------G--------- ni_nires_reg_data3neg_0_ 13 D 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data3neg_1_ 13 G 4 - 3 1 DFF * R * 1 ------G--------- ni_nires_reg_data3neg_2_ 8 C 4 - 2 1 DFF * R * 1 ---D------------ ni_nires_reg_data3neg_3_ 0 B 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data3neg_4_ 2 O 4 - 2 2 DFF * R * 1 ---D------------ ni_nires_reg_data3neg_5_ 6 O 4 - 2 1 DFF * R * 1 ---D------------ ni_nires_reg_data3neg_6_ 1 D 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data3neg_7_ 13 C 4 - 2 1 DFF * R * 1 --------I------- ni_nires_reg_data3neg_8_ 4 D 4 - 2 2 DFF * R * 1 --------I------- ni_nires_reg_data3neg_9_ 8 B 4 - 3 1 DFF * R * 1 ---D------------ ni_nires_reg_data3pos_0_ 10 L 4 - 2 2 DFF * R * 1 ------G--------- ni_nires_reg_data3pos_1_ 15 A 4 - 2 2 DFF * R * 1 A--------------- ni_nires_reg_data3pos_2_ 2 C 4 - 3 1 DFF * R * 1 --------I------- ni_nires_reg_data3pos_3_ 10 B 4 - 3 1 DFF * R * 1 ------G--------- ni_nires_reg_data3pos_4_ 7 J 4 - 3 2 DFF * R * 1 --------I------- ni_nires_reg_data3pos_5_ 11 N 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data3pos_6_ 0 N 4 - 2 1 DFF * R * 1 ------G--------- ni_nires_reg_data3pos_7_ 11 A 4 - 2 1 DFF * R * 1 A--------------- ni_nires_reg_data3pos_8_ 3 J 4 - 3 2 DFF * R * 1 ------G--------- ni_nires_reg_data3pos_9_ 3 G 7 1 4 1 DFF * R 2 -B------------O- ni_nires_reg_data_out_0_ 9 D 7 1 5 1 DFF * R 1 ------------M--- ni_nires_reg_data_out_10_ 4 G 7 1 4 1 DFF * R 1 ------------M--- ni_nires_reg_data_out_11_ 7 A 7 1 5 1 DFF * R 2 -----------LM--- ni_nires_reg_data_out_12_ 14 I 7 1 4 1 DFF * R 2 -------H----M--- ni_nires_reg_data_out_13_ 5 G 7 1 4 1 DFF * R 2 -------H---L---- ni_nires_reg_data_out_14_ 15 I 7 1 4 1 DFF * R 2 -----------L--O- ni_nires_reg_data_out_15_ 2 A 7 1 5 2 DFF * R 2 -----------L--O- ni_nires_reg_data_out_16_ 0 G 7 1 4 1 DFF * R 2 ----------KL---- ni_nires_reg_data_out_17_ 3 A 7 1 5 2 DFF * R 3 ----------KL--O- ni_nires_reg_data_out_18_ 1 G 7 1 4 1 DFF * R 1 --------------O- ni_nires_reg_data_out_19_ 5 A 7 1 5 1 DFF * R 3 -B-----H------O- ni_nires_reg_data_out_1_ 2 G 7 1 4 1 DFF * R 3 -B-----H------O- ni_nires_reg_data_out_2_ 6 D 7 1 5 1 DFF * R 2 -------------NO- ni_nires_reg_data_out_3_ 8 I 7 1 4 1 DFF * R 2 -------------NO- ni_nires_reg_data_out_4_ 7 D 7 1 5 1 DFF * R 2 ------------M-O- ni_nires_reg_data_out_5_ 8 D 7 1 5 1 DFF * R 1 ------------M--- ni_nires_reg_data_out_6_ 9 I 7 1 4 1 DFF * R 3 -B----------MN-- ni_nires_reg_data_out_7_ 11 I 7 1 4 1 DFF * R 3 -B----------MN-- ni_nires_reg_data_out_8_ 13 I 7 1 4 1 DFF * R 1 ------------M--- ni_nires_reg_data_out_9_ 9 J 3 1 1 1 DFF * R 6 ABC------J-L-N-- ni_nires_reg_gray_cnt_0_ 8 J 3 1 1 1 DFF * R 6 ABC------J-L-N-- ni_nires_reg_gray_cnt_1_ 6 G 3 1 3 1 DFF * R 5 -BCD--G-------O- ni_nires_reg_gray_cntf_0_ 7 G 3 1 3 2 DFF * R 5 -BCD--G-------O- ni_nires_reg_gray_cntf_1_ 14 G 3 1 2 1 DFF * R 1 --------I------- ni_nires_reg_new_cnt_0_ 15 G 3 1 2 2 DFF * R 1 --------I------- ni_nires_reg_new_cnt_1_ 8 G 4 1 3 1 DFF * R * 4 A--D--G-I------- ni_nires_reg_old_cnt_0_ 9 G 4 1 3 2 DFF * R * 4 A--D--G-I------- ni_nires_reg_old_cnt_1_ 5 I 5 1 4 1 DFF * R 1 ----------K----- ni_nires_reg_valid 3 K 2 1 1 1 DFF * R 1 ----------K----- ni_pattcount_0_ 1 K 3 1 2 1 DFF * R 1 ----------K----- ni_pattcount_1_ 15 K 4 1 3 1 DFF * R 1 ----------K----- ni_pattcount_2_ 8 K 5 1 4 1 DFF * R 1 ----------K----- ni_pattcount_3_ 0 K 6 1 2 1 DFF * R 1 ----------K----- ni_pattcount_4_ 4 A 5 2 5 1 DFF * R 1 ---------------P ni_reg_ce_prty_bit_neg 2 N 5 2 5 1 DFF * R 1 -----F---------- ni_reg_ce_prty_bit_pos 7 M 17 3 12 3 DFF * R 1 ----------K----- ni_reg_prty_bit_neg_r 3 B 21 2 17 4 DFF * R 1 ------------M--- ni_reg_prty_bit_pos_r 0 I 2 - 1 1 COM 4 --C-E--H-J------ nx0 7 O 5 - 2 1 COM 2 -B------------O- nx1051 8 O 6 - 5 1 COM 2 -B-----------N-- nx1107 13 M 6 - 4 2 COM 2 -B-----------N-- nx1145 2 M 5 - 4 1 COM 2 -B-----------N-- nx1179 1 M 6 - 4 2 COM 2 -B----------M--- nx1191 4 M 4 - 2 1 COM 2 ----------K--N-- nx1241 1 L 4 - 2 1 COM 2 -----------L-N-- nx1291 13 L 12 - 7 2 COM 1 ------------M--- nx1334 5 K 8 - 1 1 COM 1 -----F---------- nx1461 3 F 17 - 12 3 COM 1 -------H-------- nx1531 2 K 3 - 2 1 COM 5 ----------KLMNO- nx158 6 P 14 - 9 2 COM 1 -------H-------- nx1596 4 K 8 - 1 1 COM 2 -----F---------P nx1610 14 M 6 - 1 1 COM 1 ------------M--- nx1671 3 M 5 - 4 1 COM 1 ------------M--- nx1673 2 H 4 - 3 1 COM 2 -----------LM--- nx1715 5 M 5 - 2 1 COM 2 -----------LM--- nx1769 9 L 5 - 2 1 COM 1 -----------L---- nx1831 2 L 6 - 4 2 COM 2 ----------KL---- nx1855 6 F 14 - 9 2 COM 1 -------H-------- nx1868 13 O 5 - 4 1 COM 1 -----------L---- nx1881 10 O 6 - 4 2 COM 2 ----------K-M--- nx1889 4 P 17 - 12 3 COM 1 -------H-------- nx2049 12 H 3 - 2 1 COM 1 --C------------- nx216 7 I 4 - 4 1 COM 1 ------G--------- nx595 12 O 6 - 1 1 COM 1 --------------O- nx939 1 H 5 - 4 1 COM 2 -B------------O- nx941 9 N 4 - 3 1 COM 3 -B-----------NO- nx993 -- H 2 1 0 PTOE ---------------- SCL.OE -- I 2 1 0 PTOE ---------------- SDA.OE -- C 1 1 0 PTOE ---------------- jTDO.OE -- B 1 1 0 PTOE ---------------- SD2ANL.OE ---------------------------------------------------------------------------------- <Note> CLS = Number of clusters used INP = Number of input signals PTs = Number of product terms LL = Number of logic levels PRE = Has preset equation RES = Has reset equation PUP = Power-Up initial state: R=Reset, S=Set CE = Has clock enable equation OE = Has output enable equation IR = Input register FP = Fast path used OBP = ORP bypass used PostFit_Equations
EN = 1 ; (1 pterm, 0 signal) ENABLE = 1 ; (1 pterm, 0 signal) ID_0_0_.D = !ID_0_0_.Q ; (1 pterm, 1 signal) ID_0_0_.C = clk ; (1 pterm, 1 signal) ID_0_0_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_0_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_0_1_.D = ID_0_1_.Q & !ID_0_0_.Q # !ID_0_1_.Q & ID_0_0_.Q ; (2 pterms, 2 signals) ID_0_1_.C = clk ; (1 pterm, 1 signal) ID_0_1_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_1_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_0_2_.D = !ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q # ID_0_2_.Q & !ID_0_1_.Q # ID_0_2_.Q & !ID_0_0_.Q ; (3 pterms, 3 signals) ID_0_2_.C = clk ; (1 pterm, 1 signal) ID_0_2_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_2_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_0_3_.D = !ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q # ID_0_3_.Q & !ID_0_1_.Q # ID_0_3_.Q & !ID_0_2_.Q # ID_0_3_.Q & !ID_0_0_.Q ; (4 pterms, 4 signals) ID_0_3_.C = clk ; (1 pterm, 1 signal) ID_0_3_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_3_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_0_3__0 = !( reset_n & j2c_reg_rstout_n_i.Q ) ; (1 pterm, 2 signals) ID_0_4_.D.X1 = ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q ; (1 pterm, 4 signals) ID_0_4_.D.X2 = ID_0_4_.Q ; (1 pterm, 1 signal) ID_0_4_.C = clk ; (1 pterm, 1 signal) ID_0_4_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_4_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_0_5_.T = ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q & ID_0_4_.Q ; (1 pterm, 5 signals) ID_0_5_.C = clk ; (1 pterm, 1 signal) ID_0_5_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_5_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_0_6_.T = ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q & ID_0_5_.Q & ID_0_4_.Q ; (1 pterm, 6 signals) ID_0_6_.C = clk ; (1 pterm, 1 signal) ID_0_6_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_6_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_0_7_.T = ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q & ID_0_6_.Q & ID_0_5_.Q & ID_0_4_.Q ; (1 pterm, 7 signals) ID_0_7_.C = clk ; (1 pterm, 1 signal) ID_0_7_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_0_7_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_1_0_.D = ID_1_0_.Q & !nx1610 # !ID_1_0_.Q & nx1610 ; (2 pterms, 2 signals) ID_1_0_.C = clk ; (1 pterm, 1 signal) ID_1_0_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_0_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_1_1_.D = !ID_1_1_.Q & ID_1_0_.Q & !nx1461 # ID_1_1_.Q & !ID_1_0_.Q # ID_1_1_.Q & nx1461 ; (3 pterms, 3 signals) ID_1_1_.C = clk ; (1 pterm, 1 signal) ID_1_1_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_1_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_1_2_.D = !ID_1_2_.Q & ID_1_1_.Q & ID_1_0_.Q & !nx1461 # ID_1_2_.Q & !ID_1_0_.Q # ID_1_2_.Q & !ID_1_1_.Q # ID_1_2_.Q & nx1461 ; (4 pterms, 4 signals) ID_1_2_.C = clk ; (1 pterm, 1 signal) ID_1_2_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_2_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_1_3_.D.X1 = ID_1_3_.Q ; (1 pterm, 1 signal) ID_1_3_.D.X2 = ID_1_2_.Q & ID_1_1_.Q & ID_1_0_.Q & nx1610 ; (1 pterm, 4 signals) ID_1_3_.C = clk ; (1 pterm, 1 signal) ID_1_3_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_3_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_1_4_.T = ID_1_3_.Q & ID_1_2_.Q & ID_1_1_.Q & ID_1_0_.Q & nx1610 ; (1 pterm, 5 signals) ID_1_4_.C = clk ; (1 pterm, 1 signal) ID_1_4_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_4_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_1_5_.T = ID_1_3_.Q & ID_1_2_.Q & ID_1_1_.Q & ID_1_0_.Q & nx1610 & ID_1_4_.Q ; (1 pterm, 6 signals) ID_1_5_.C = clk ; (1 pterm, 1 signal) ID_1_5_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_5_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_1_6_.T = ID_1_3_.Q & ID_1_2_.Q & ID_1_1_.Q & ID_1_0_.Q & nx1610 & ID_1_5_.Q & ID_1_4_.Q ; (1 pterm, 7 signals) ID_1_6_.C = clk ; (1 pterm, 1 signal) ID_1_6_.CE = TX_EN.Q ; (1 pterm, 1 signal) ID_1_6_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_2_0_.D = !ID_2_0_.Q ; (1 pterm, 1 signal) ID_2_0_.C = clk ; (1 pterm, 1 signal) ID_2_0_.CE = ni_reg_ce_prty_bit_neg.Q ; (1 pterm, 1 signal) ID_2_0_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_2_1_.D = ID_2_1_.Q & !ID_2_0_.Q # !ID_2_1_.Q & ID_2_0_.Q ; (2 pterms, 2 signals) ID_2_1_.C = clk ; (1 pterm, 1 signal) ID_2_1_.CE = ni_reg_ce_prty_bit_neg.Q ; (1 pterm, 1 signal) ID_2_1_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_2_2_.D = !ID_2_2_.Q & ID_2_1_.Q & ID_2_0_.Q # ID_2_2_.Q & !ID_2_1_.Q # ID_2_2_.Q & !ID_2_0_.Q ; (3 pterms, 3 signals) ID_2_2_.C = clk ; (1 pterm, 1 signal) ID_2_2_.CE = ni_reg_ce_prty_bit_neg.Q ; (1 pterm, 1 signal) ID_2_2_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_2_3_.D = !ID_2_3_.Q & ID_2_2_.Q & ID_2_1_.Q & ID_2_0_.Q # ID_2_3_.Q & !ID_2_1_.Q # ID_2_3_.Q & !ID_2_2_.Q # ID_2_3_.Q & !ID_2_0_.Q ; (4 pterms, 4 signals) ID_2_3_.C = clk ; (1 pterm, 1 signal) ID_2_3_.CE = ni_reg_ce_prty_bit_neg.Q ; (1 pterm, 1 signal) ID_2_3_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_2_4_.D.X1 = ID_2_3_.Q & ID_2_2_.Q & ID_2_1_.Q & ID_2_0_.Q ; (1 pterm, 4 signals) ID_2_4_.D.X2 = ID_2_4_.Q ; (1 pterm, 1 signal) ID_2_4_.C = clk ; (1 pterm, 1 signal) ID_2_4_.CE = ni_reg_ce_prty_bit_neg.Q ; (1 pterm, 1 signal) ID_2_4_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_2_5_.T = ID_2_3_.Q & ID_2_2_.Q & ID_2_1_.Q & ID_2_0_.Q & ID_2_4_.Q ; (1 pterm, 5 signals) ID_2_5_.C = clk ; (1 pterm, 1 signal) ID_2_5_.CE = ni_reg_ce_prty_bit_neg.Q ; (1 pterm, 1 signal) ID_2_5_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_2_6_.T = ID_2_3_.Q & ID_2_2_.Q & ID_2_1_.Q & ID_2_0_.Q & ID_2_5_.Q & ID_2_4_.Q ; (1 pterm, 6 signals) ID_2_6_.C = clk ; (1 pterm, 1 signal) ID_2_6_.CE = ni_reg_ce_prty_bit_neg.Q ; (1 pterm, 1 signal) ID_2_6_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_3_0_.D = !ID_3_0_.Q ; (1 pterm, 1 signal) ID_3_0_.C = clk ; (1 pterm, 1 signal) ID_3_0_.CE = ni_reg_ce_prty_bit_pos.Q ; (1 pterm, 1 signal) ID_3_0_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_3_1_.D = ID_3_1_.Q & !ID_3_0_.Q # !ID_3_1_.Q & ID_3_0_.Q ; (2 pterms, 2 signals) ID_3_1_.C = clk ; (1 pterm, 1 signal) ID_3_1_.CE = ni_reg_ce_prty_bit_pos.Q ; (1 pterm, 1 signal) ID_3_1_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_3_2_.D = !ID_3_2_.Q & ID_3_1_.Q & ID_3_0_.Q # ID_3_2_.Q & !ID_3_1_.Q # ID_3_2_.Q & !ID_3_0_.Q ; (3 pterms, 3 signals) ID_3_2_.C = clk ; (1 pterm, 1 signal) ID_3_2_.CE = ni_reg_ce_prty_bit_pos.Q ; (1 pterm, 1 signal) ID_3_2_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_3_3_.D = !ID_3_3_.Q & ID_3_2_.Q & ID_3_1_.Q & ID_3_0_.Q # ID_3_3_.Q & !ID_3_1_.Q # ID_3_3_.Q & !ID_3_2_.Q # ID_3_3_.Q & !ID_3_0_.Q ; (4 pterms, 4 signals) ID_3_3_.C = clk ; (1 pterm, 1 signal) ID_3_3_.CE = ni_reg_ce_prty_bit_pos.Q ; (1 pterm, 1 signal) ID_3_3_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_3_4_.D.X1 = ID_3_3_.Q & ID_3_2_.Q & ID_3_1_.Q & ID_3_0_.Q ; (1 pterm, 4 signals) ID_3_4_.D.X2 = ID_3_4_.Q ; (1 pterm, 1 signal) ID_3_4_.C = clk ; (1 pterm, 1 signal) ID_3_4_.CE = ni_reg_ce_prty_bit_pos.Q ; (1 pterm, 1 signal) ID_3_4_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_3_5_.T = ID_3_3_.Q & ID_3_2_.Q & ID_3_1_.Q & ID_3_0_.Q & ID_3_4_.Q ; (1 pterm, 5 signals) ID_3_5_.C = clk ; (1 pterm, 1 signal) ID_3_5_.CE = ni_reg_ce_prty_bit_pos.Q ; (1 pterm, 1 signal) ID_3_5_.AR = ID_0_3__0 ; (1 pterm, 1 signal) ID_3_6_.T = ID_3_3_.Q & ID_3_2_.Q & ID_3_1_.Q & ID_3_0_.Q & ID_3_5_.Q & ID_3_4_.Q ; (1 pterm, 6 signals) ID_3_6_.C = clk ; (1 pterm, 1 signal) ID_3_6_.CE = ni_reg_ce_prty_bit_pos.Q ; (1 pterm, 1 signal) ID_3_6_.AR = ID_0_3__0 ; (1 pterm, 1 signal) LCKREFN = 0 ; (0 pterm, 0 signal) LED_10_ = 1 ; (1 pterm, 0 signal) LED_5_ = 0 ; (0 pterm, 0 signal) LED_6_ = PRBSEN.PIN ; (1 pterm, 1 signal) LED_7_ = FAULT ; (1 pterm, 1 signal) LED_8_ = 1 ; (1 pterm, 0 signal) LED_9_ = 0 ; (0 pterm, 0 signal) LOOPEN = 0 ; (0 pterm, 0 signal) PRBSEN.D = j2c_reg_shreg_2_.Q ; (1 pterm, 1 signal) PRBSEN.OE = j2c_reg_creg1hm_7_reg.Q ; (1 pterm, 1 signal) PRBSEN.C = nx0 ; (1 pterm, 1 signal) PRBSEN.CE = !jTDI & j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) PRBSEN.AR = !reset_n ; (1 pterm, 1 signal) SCL = 0 ; (0 pterm, 0 signal) SCL.OE = DIS_JTG & !jTCK ; (1 pterm, 2 signals) SD2ANL.D = j2c_reg_shreg_1_.Q ; (1 pterm, 1 signal) SD2ANL.OE = j2c_reg_creg1hm_7_reg.Q ; (1 pterm, 1 signal) SD2ANL.C = nx0 ; (1 pterm, 1 signal) SD2ANL.CE = !jTDI & j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) SD2ANL.AR = !reset_n ; (1 pterm, 1 signal) SDA = 0 ; (0 pterm, 0 signal) SDA.OE = DIS_JTG & !jTMS ; (1 pterm, 2 signals) TESTEN = 0 ; (0 pterm, 0 signal) TXD_0_.D = !( !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_1_.Q & !j2c_reg_creg0hm_4_.Q & nx939 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & nx939 # TXD_0_.Q & j2c_reg_creg1hm_3_.Q & nx939 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_4_.Q & !ni_nires_reg_data_out_0_.Q & nx939 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_0_.Q & nx939 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_0_.Q & nx939 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_5_.Q & !ni_nires_reg_data_out_0_.Q & nx939 ) ; (7 pterms, 13 signals) TXD_0_.C = clk ; (1 pterm, 1 signal) TXD_0_.CE = nx158 ; (1 pterm, 1 signal) TXD_0_.AR = 0 ; (0 pterm, 0 signal) TXD_10_.D = !( !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_4_.Q & nx1769 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & nx1769 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & nx1715 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & nx1715 # TXD_10_.Q & !TXD_9_.Q & !TXD_8_.Q & j2c_reg_creg1hm_3_.Q # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_4_.Q & nx1769 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_4_.Q & nx1769 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_2_.Q & nx1769 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_3_.Q & nx1769 # !TXD_10_.Q & TXD_8_.Q & j2c_reg_creg1hm_3_.Q # !TXD_10_.Q & TXD_9_.Q & j2c_reg_creg1hm_3_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & !ni_nires_reg_data_out_12_.Q & nx1769 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_2_.Q & !ni_nires_reg_data_out_12_.Q & nx1769 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_3_.Q & !ni_nires_reg_data_out_12_.Q & nx1769 ) ; (14 pterms, 15 signals) TXD_10_.C = clk ; (1 pterm, 1 signal) TXD_10_.CE = nx158 ; (1 pterm, 1 signal) TXD_10_.AR = 0 ; (0 pterm, 0 signal) TXD_11_.D = !( !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_4_.Q & nx1831 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & nx1831 # TXD_11_.Q & !TXD_10_.Q & !TXD_9_.Q & !TXD_8_.Q & j2c_reg_creg1hm_3_.Q # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & nx1831 & !ni_nires_reg_data_out_14_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_2_.Q & nx1715 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_3_.Q & nx1715 # !TXD_11_.Q & TXD_8_.Q & j2c_reg_creg1hm_3_.Q # !TXD_11_.Q & TXD_9_.Q & j2c_reg_creg1hm_3_.Q # !TXD_11_.Q & TXD_10_.Q & j2c_reg_creg1hm_3_.Q ) ; (9 pterms, 14 signals) TXD_11_.C = clk ; (1 pterm, 1 signal) TXD_11_.CE = nx158 ; (1 pterm, 1 signal) TXD_11_.AR = 0 ; (0 pterm, 0 signal) TXD_12_.D = !( !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_0_.Q & j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_4_.Q & nx1831 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_4_.Q & nx1831 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_4_.Q & nx1831 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & nx1881 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_0_.Q & j2c_reg_creg0hm_2_.Q & nx1831 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_2_.Q & nx1831 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_0_.Q & j2c_reg_creg0hm_2_.Q & nx1831 & !ni_nires_reg_data_out_14_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_2_.Q & nx1831 & !ni_nires_reg_data_out_14_.Q # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_3_.Q & nx1831 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & nx1881 # TXD_12_.Q & j2c_reg_creg1hm_3_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_3_.Q & nx1831 & !ni_nires_reg_data_out_14_.Q ) ; (12 pterms, 13 signals) TXD_12_.C = clk ; (1 pterm, 1 signal) TXD_12_.CE = nx158 ; (1 pterm, 1 signal) TXD_12_.AR = 0 ; (0 pterm, 0 signal) TXD_13_.D = !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !nx1855 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_3_.Q & !nx1855 # TXD_13_.Q & !TXD_12_.Q & j2c_reg_creg1hm_3_.Q # !TXD_13_.Q & TXD_12_.Q & j2c_reg_creg1hm_3_.Q # !nx1291 & !nx1881 ; (5 pterms, 9 signals) TXD_13_.C = clk ; (1 pterm, 1 signal) TXD_13_.CE = nx158 ; (1 pterm, 1 signal) TXD_13_.AR = 0 ; (0 pterm, 0 signal) TXD_14_.D = ni_nires_reg_data_out_18_.Q & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q # ni_nires_reg_data_out_17_.Q & !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & j2c_reg_creg0hm_2_.Q & !nx1855 # !TXD_14_.Q & TXD_13_.Q & TXD_12_.Q & j2c_reg_creg1hm_3_.Q # ni_nires_reg_data_out_18_.Q & !nx1241 & !j2c_reg_creg0hm_7_.Q # ni_nires_reg_data_out_17_.Q & !nx1241 & j2c_reg_creg0hm_7_.Q # TXD_14_.Q & !TXD_12_.Q & j2c_reg_creg1hm_3_.Q # TXD_14_.Q & !TXD_13_.Q & j2c_reg_creg1hm_3_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_3_.Q & !nx1855 ; (9 pterms, 13 signals) TXD_14_.C = clk ; (1 pterm, 1 signal) TXD_14_.CE = nx158 ; (1 pterm, 1 signal) TXD_14_.AR = 0 ; (0 pterm, 0 signal) TXD_15_.D.X1 = !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_3_.Q & !nx1889 # ni_nires_reg_data_out_18_.Q & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_3_.Q # ni_nires_reg_data_out_17_.Q & !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_3_.Q # TXD_14_.Q & TXD_13_.Q & TXD_12_.Q & j2c_reg_creg1hm_3_.Q ; (4 pterms, 9 signals) TXD_15_.D.X2 = TXD_15_.Q & j2c_reg_creg1hm_3_.Q ; (1 pterm, 2 signals) TXD_15_.C = clk ; (1 pterm, 1 signal) TXD_15_.CE = nx158 ; (1 pterm, 1 signal) TXD_15_.AR = 0 ; (0 pterm, 0 signal) TXD_1_.D = !( nx1051 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_4_.Q # nx1051 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q # nx1051 & !j2c_reg_creg1hm_3_.Q & !ni_nires_reg_data_out_2_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q # !TXD_1_.Q & !TXD_0_.Q & j2c_reg_creg1hm_3_.Q # TXD_1_.Q & TXD_0_.Q & j2c_reg_creg1hm_3_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_2_.Q & nx941 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_3_.Q & nx941 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_1_.Q & nx941 ) ; (8 pterms, 13 signals) TXD_1_.C = clk ; (1 pterm, 1 signal) TXD_1_.CE = nx158 ; (1 pterm, 1 signal) TXD_1_.AR = 0 ; (0 pterm, 0 signal) TXD_2_.D = !( nx1051 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q # nx1051 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_2_.Q # nx1051 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_3_.Q # nx1051 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_4_.Q # nx993 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q # nx993 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q # TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & j2c_reg_creg1hm_3_.Q # nx1051 & !j2c_reg_creg1hm_3_.Q & !ni_nires_reg_data_out_2_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q # nx1051 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_4_.Q # nx1051 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_4_.Q # !TXD_2_.Q & !TXD_0_.Q & j2c_reg_creg1hm_3_.Q # !TXD_2_.Q & !TXD_1_.Q & j2c_reg_creg1hm_3_.Q # nx1051 & !j2c_reg_creg1hm_3_.Q & !ni_nires_reg_data_out_2_.Q & j2c_reg_creg0hm_2_.Q # nx1051 & !j2c_reg_creg1hm_3_.Q & !ni_nires_reg_data_out_2_.Q & j2c_reg_creg0hm_3_.Q ) ; (14 pterms, 15 signals) TXD_2_.C = clk ; (1 pterm, 1 signal) TXD_2_.CE = nx158 ; (1 pterm, 1 signal) TXD_2_.AR = 0 ; (0 pterm, 0 signal) TXD_3_.D.X1 = !nx1107 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q # !nx993 & !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_2_.Q # !nx993 & !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_3_.Q # TXD_2_.Q & TXD_1_.Q & TXD_0_.Q & j2c_reg_creg1hm_3_.Q ; (4 pterms, 8 signals) TXD_3_.D.X2 = TXD_3_.Q & j2c_reg_creg1hm_3_.Q ; (1 pterm, 2 signals) TXD_3_.C = clk ; (1 pterm, 1 signal) TXD_3_.CE = nx158 ; (1 pterm, 1 signal) TXD_3_.AR = 0 ; (0 pterm, 0 signal) TXD_4_.D = !nx1179 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q # !nx1179 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q # !nx1107 & !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_3_.Q # !TXD_4_.Q & j2c_reg_creg1hm_3_.Q # !nx1107 & !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_0_.Q & j2c_reg_creg0hm_2_.Q # !nx1107 & !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_2_.Q ; (6 pterms, 8 signals) TXD_4_.C = clk ; (1 pterm, 1 signal) TXD_4_.CE = nx158 ; (1 pterm, 1 signal) TXD_4_.AR = 0 ; (0 pterm, 0 signal) TXD_5_.D = !nx1145 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_3_.Q # !nx1145 & !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q # !TXD_5_.Q & !TXD_4_.Q & j2c_reg_creg1hm_3_.Q # TXD_5_.Q & TXD_4_.Q & j2c_reg_creg1hm_3_.Q # !nx1179 & !nx1291 ; (5 pterms, 9 signals) TXD_5_.C = clk ; (1 pterm, 1 signal) TXD_5_.CE = nx158 ; (1 pterm, 1 signal) TXD_5_.AR = 0 ; (0 pterm, 0 signal) TXD_6_.D = !nx1145 & !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & j2c_reg_creg0hm_2_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & ni_nires_reg_data_out_7_.Q # !TXD_6_.Q & !TXD_5_.Q & !TXD_4_.Q & j2c_reg_creg1hm_3_.Q # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & ni_nires_reg_data_out_8_.Q # !nx1241 & j2c_reg_creg0hm_7_.Q & ni_nires_reg_data_out_7_.Q # TXD_6_.Q & TXD_4_.Q & j2c_reg_creg1hm_3_.Q # TXD_6_.Q & TXD_5_.Q & j2c_reg_creg1hm_3_.Q # !nx1145 & !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_3_.Q # !nx1241 & !j2c_reg_creg0hm_7_.Q & ni_nires_reg_data_out_8_.Q ; (9 pterms, 13 signals) TXD_6_.C = clk ; (1 pterm, 1 signal) TXD_6_.CE = nx158 ; (1 pterm, 1 signal) TXD_6_.AR = 0 ; (0 pterm, 0 signal) TXD_7_.D.X1 = !j2c_reg_creg1hm_3_.Q & !nx1191 & !j2c_reg_creg0hm_3_.Q # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_3_.Q & ni_nires_reg_data_out_8_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_3_.Q & ni_nires_reg_data_out_7_.Q # !TXD_6_.Q & !TXD_5_.Q & !TXD_4_.Q & j2c_reg_creg1hm_3_.Q ; (4 pterms, 9 signals) TXD_7_.D.X2 = TXD_7_.Q & j2c_reg_creg1hm_3_.Q ; (1 pterm, 2 signals) TXD_7_.C = clk ; (1 pterm, 1 signal) TXD_7_.CE = nx158 ; (1 pterm, 1 signal) TXD_7_.AR = 0 ; (0 pterm, 0 signal) TXD_8_.D = !( !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_4_.Q & nx1671 & !ni_nires_reg_data_out_11_.Q # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & nx1671 # TXD_8_.Q & j2c_reg_creg1hm_3_.Q & nx1671 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_4_.Q & nx1671 & !ni_nires_reg_data_out_10_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_6_.Q & nx1671 & !ni_nires_reg_data_out_10_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_7_.Q & nx1671 & !ni_nires_reg_data_out_10_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_5_.Q & nx1671 & !ni_nires_reg_data_out_10_.Q ) ; (7 pterms, 13 signals) TXD_8_.C = clk ; (1 pterm, 1 signal) TXD_8_.CE = nx158 ; (1 pterm, 1 signal) TXD_8_.AR = 0 ; (0 pterm, 0 signal) TXD_9_.D = !( !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_4_.Q & nx1769 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & nx1769 # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !ni_nires_reg_data_out_12_.Q & nx1769 # TXD_9_.Q & !TXD_8_.Q & j2c_reg_creg1hm_3_.Q # !TXD_9_.Q & TXD_8_.Q & j2c_reg_creg1hm_3_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_2_.Q & nx1673 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_3_.Q & nx1673 # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_1_.Q & nx1673 ) ; (8 pterms, 13 signals) TXD_9_.C = clk ; (1 pterm, 1 signal) TXD_9_.CE = nx158 ; (1 pterm, 1 signal) TXD_9_.AR = 0 ; (0 pterm, 0 signal) TX_EN.D = !( j2c_reg_creg1hm_3_.Q & !ni_pattcount_2_.Q & !ni_pattcount_1_.Q & !ni_pattcount_0_.Q & !ni_pattcount_4_.Q & !ni_pattcount_3_.Q # !j2c_reg_creg1hm_3_.Q & !ni_nires_reg_valid.Q ) ; (2 pterms, 7 signals) TX_EN.C = clk ; (1 pterm, 1 signal) TX_EN.AR = 0 ; (0 pterm, 0 signal) TX_ER = 0 ; (0 pterm, 0 signal) ix1373.X1 = !TXD_14_.Q & !TXD_13_.Q & !ni_reg_prty_bit_neg_r.Q # !TXD_14_.Q & TXD_13_.Q & ni_reg_prty_bit_neg_r.Q # TXD_14_.Q & !TXD_13_.Q & ni_reg_prty_bit_neg_r.Q # TXD_14_.Q & TXD_13_.Q & !ni_reg_prty_bit_neg_r.Q ; (4 pterms, 3 signals) ix1373.X2 = !TXD_15_.Q ; (1 pterm, 1 signal) ix1379.X1 = !TXD_11_.Q & !TXD_10_.Q & !TXD_9_.Q # !TXD_11_.Q & TXD_10_.Q & TXD_9_.Q # TXD_11_.Q & !TXD_10_.Q & TXD_9_.Q # TXD_11_.Q & TXD_10_.Q & !TXD_9_.Q ; (4 pterms, 3 signals) ix1379.X2 = !TXD_12_.Q ; (1 pterm, 1 signal) ix1693.X1 = !TXD_6_.Q & !TXD_5_.Q & !ni_reg_prty_bit_pos_r.Q # !TXD_6_.Q & TXD_5_.Q & ni_reg_prty_bit_pos_r.Q # TXD_6_.Q & !TXD_5_.Q & ni_reg_prty_bit_pos_r.Q # TXD_6_.Q & TXD_5_.Q & !ni_reg_prty_bit_pos_r.Q ; (4 pterms, 3 signals) ix1693.X2 = !TXD_7_.Q ; (1 pterm, 1 signal) ix1699.X1 = !TXD_3_.Q & !TXD_2_.Q & !TXD_1_.Q # !TXD_3_.Q & TXD_2_.Q & TXD_1_.Q # TXD_3_.Q & !TXD_2_.Q & TXD_1_.Q # TXD_3_.Q & TXD_2_.Q & !TXD_1_.Q ; (4 pterms, 3 signals) ix1699.X2 = !TXD_4_.Q ; (1 pterm, 1 signal) j2c_bitcnt_0_.D = !j2c_bitcnt_0_.Q ; (1 pterm, 1 signal) j2c_bitcnt_0_.C = !jTCK ; (1 pterm, 1 signal) j2c_bitcnt_0_.AR = !nx0 ; (1 pterm, 1 signal) j2c_bitcnt_1_.D = j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q ; (2 pterms, 2 signals) j2c_bitcnt_1_.C = !jTCK ; (1 pterm, 1 signal) j2c_bitcnt_1_.AR = !nx0 ; (1 pterm, 1 signal) j2c_bitcnt_2_.D = !j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # j2c_bitcnt_2_.Q & !j2c_bitcnt_1_.Q # j2c_bitcnt_2_.Q & !j2c_bitcnt_0_.Q ; (3 pterms, 3 signals) j2c_bitcnt_2_.C = !jTCK ; (1 pterm, 1 signal) j2c_bitcnt_2_.AR = !nx0 ; (1 pterm, 1 signal) j2c_reg_cmdreg_0_.D = j2c_reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c_reg_cmdreg_0_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_cmdreg_0_.CE = jTDI ; (1 pterm, 1 signal) j2c_reg_cmdreg_0_.AR = 0 ; (0 pterm, 0 signal) j2c_reg_cmdreg_0_.AP = !reset_n ; (1 pterm, 1 signal) j2c_reg_cmdreg_1_.D = j2c_reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c_reg_cmdreg_1_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_cmdreg_1_.CE = jTDI ; (1 pterm, 1 signal) j2c_reg_cmdreg_1_.AR = 0 ; (0 pterm, 0 signal) j2c_reg_cmdreg_1_.AP = !reset_n ; (1 pterm, 1 signal) j2c_reg_cmdreg_2_.D = j2c_reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c_reg_cmdreg_2_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_cmdreg_2_.CE = jTDI ; (1 pterm, 1 signal) j2c_reg_cmdreg_2_.AR = 0 ; (0 pterm, 0 signal) j2c_reg_cmdreg_2_.AP = !reset_n ; (1 pterm, 1 signal) j2c_reg_cmdreg_3_.D = jTDI & j2c_reg_shreg_7_.Q ; (1 pterm, 2 signals) j2c_reg_cmdreg_3_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_cmdreg_3_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_0_.D = j2c_reg_shreg_0_.Q ; (1 pterm, 1 signal) j2c_reg_creg0hm_0_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_0_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_0_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_1_.D = j2c_reg_shreg_1_.Q ; (1 pterm, 1 signal) j2c_reg_creg0hm_1_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_1_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_1_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_2_.D = j2c_reg_shreg_2_.Q ; (1 pterm, 1 signal) j2c_reg_creg0hm_2_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_2_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_2_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_3_.D = j2c_reg_shreg_3_.Q ; (1 pterm, 1 signal) j2c_reg_creg0hm_3_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_3_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_3_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_4_.D = j2c_reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c_reg_creg0hm_4_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_4_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_4_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_5_.D = j2c_reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c_reg_creg0hm_5_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_5_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_5_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_6_.D = j2c_reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c_reg_creg0hm_6_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_6_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_6_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg0hm_7_.D = j2c_reg_shreg_7_.Q ; (1 pterm, 1 signal) j2c_reg_creg0hm_7_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg0hm_7_.CE = !jTDI & !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg0hm_7_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_0_.D = j2c_reg_shreg_0_.Q ; (1 pterm, 1 signal) j2c_reg_creg1hm_0_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_0_.CE = !jTDI & j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_0_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_3_.D = j2c_reg_shreg_3_.Q ; (1 pterm, 1 signal) j2c_reg_creg1hm_3_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_3_.CE = !jTDI & j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_3_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_4_.D = j2c_reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c_reg_creg1hm_4_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_4_.CE = !jTDI & j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_4_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_5_.D = j2c_reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c_reg_creg1hm_5_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_5_.CE = !jTDI & j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_5_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_6_.D = j2c_reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c_reg_creg1hm_6_.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_6_.CE = !jTDI & j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_6_.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_creg1hm_7_reg.D = j2c_reg_shreg_7_.Q ; (1 pterm, 1 signal) j2c_reg_creg1hm_7_reg.C = nx0 ; (1 pterm, 1 signal) j2c_reg_creg1hm_7_reg.CE = !jTDI & j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q ; (1 pterm, 3 signals) j2c_reg_creg1hm_7_reg.AR = !reset_n ; (1 pterm, 1 signal) j2c_reg_rstout_n_i.D = j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q ; (1 pterm, 3 signals) j2c_reg_rstout_n_i.C = !jTCK ; (1 pterm, 1 signal) j2c_reg_rstout_n_i.CE = j2c_reg_rstout_n_i_0 ; (1 pterm, 1 signal) j2c_reg_rstout_n_i.AR = 0 ; (0 pterm, 0 signal) j2c_reg_rstout_n_i.AP = !nx0 ; (1 pterm, 1 signal) j2c_reg_rstout_n_i_0 = j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !j2c_reg_cmdreg_0_.Q & j2c_reg_cmdreg_3_.Q & !j2c_bitcnt_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q ; (2 pterms, 5 signals) j2c_reg_shreg_0_.D = j2c_reg_shreg_1_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_0_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_0_.AR = 0 ; (0 pterm, 0 signal) j2c_reg_shreg_1_.D = j2c_reg_shreg_2_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_1_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_1_.AR = 0 ; (0 pterm, 0 signal) j2c_reg_shreg_2_.D = j2c_reg_shreg_3_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_2_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_2_.AR = 0 ; (0 pterm, 0 signal) j2c_reg_shreg_3_.D = j2c_reg_shreg_4_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_3_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_3_.AR = 0 ; (0 pterm, 0 signal) j2c_reg_shreg_4_.D = j2c_reg_shreg_5_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_4_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_4_.AR = 0 ; (0 pterm, 0 signal) j2c_reg_shreg_5_.D = j2c_reg_shreg_6_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_5_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_5_.AR = 0 ; (0 pterm, 0 signal) j2c_reg_shreg_6_.D = j2c_reg_shreg_7_.Q ; (1 pterm, 1 signal) j2c_reg_shreg_6_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_6_.AR = 0 ; (0 pterm, 0 signal) j2c_reg_shreg_7_.D = jTDI ; (1 pterm, 1 signal) j2c_reg_shreg_7_.C = jTCK ; (1 pterm, 1 signal) j2c_reg_shreg_7_.AR = 0 ; (0 pterm, 0 signal) jTDO = !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & !j2c_reg_cmdreg_0_.Q & ID_0_7_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & FAULT & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & !j2c_reg_cmdreg_0_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & j2c_reg_creg0hm_7_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & j2c_reg_creg1hm_7_reg.Q & j2c_reg_cmdreg_0_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & FAULT & !j2c_reg_cmdreg_2_.Q & j2c_reg_cmdreg_0_.Q & j2c_bitcnt_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # j2c_reg_cmdreg_0_.Q & !j2c_bitcnt_2_.Q & !nx1531 # !nx2049 & !j2c_reg_cmdreg_0_.Q & !j2c_bitcnt_2_.Q # j2c_reg_cmdreg_0_.Q & j2c_bitcnt_2_.Q & nx1868 # !j2c_reg_cmdreg_0_.Q & j2c_bitcnt_2_.Q & nx1596 # DIS_JTG & SDA.PIN ; (10 pterms, 16 signals) jTDO.OE = nx216 ; (1 pterm, 1 signal) ni_nires_reg_clear_n_i.D = reset_n & j2c_reg_rstout_n_i.Q ; (1 pterm, 2 signals) ni_nires_reg_clear_n_i.C = clk ; (1 pterm, 1 signal) ni_nires_reg_clear_n_i.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_0_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_0_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_1_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_1_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_2_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_2_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_3_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_3_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_4_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_4_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_5_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_5_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_6_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_6_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_7_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_7_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_8_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_8_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data0neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0neg_9_.CE = !ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0neg_9_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_0_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_0_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_1_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_1_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_2_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_2_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_3_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_3_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_4_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_4_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_5_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_5_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_6_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_6_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_7_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_7_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_8_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_8_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data0pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data0pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data0pos_9_.CE = !ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data0pos_9_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_0_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_0_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_1_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_1_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_2_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_2_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_3_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_3_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_4_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_4_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_5_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_5_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_6_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_6_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_7_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_7_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_8_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_8_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data1neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1neg_9_.CE = ni_nires_reg_gray_cntf_0_.Q & !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1neg_9_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_0_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_0_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_1_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_1_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_2_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_2_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_3_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_3_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_4_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_4_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_5_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_5_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_6_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_6_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_7_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_7_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_8_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_8_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data1pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data1pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data1pos_9_.CE = !ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data1pos_9_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_0_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_0_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_1_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_1_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_2_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_2_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_3_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_3_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_4_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_4_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_5_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_5_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_6_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_6_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_7_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_7_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_8_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_8_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data2neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2neg_9_.CE = ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2neg_9_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_0_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_0_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_1_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_1_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_2_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_2_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_3_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_3_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_4_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_4_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_5_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_5_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_6_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_6_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_7_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_7_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_8_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_8_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data2pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data2pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data2pos_9_.CE = ni_nires_reg_gray_cnt_1_.Q & ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data2pos_9_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3neg_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_0_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_0_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3neg_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_1_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_1_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3neg_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_2_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_2_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_2_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3neg_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_3_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_3_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_3_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3neg_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_4_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_4_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_4_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3neg_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_5_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_5_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_5_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3neg_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_6_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_6_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_6_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3neg_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_7_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_7_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_7_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3neg_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_8_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_8_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_8_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3neg_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data3neg_9_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3neg_9_.CE = !ni_nires_reg_gray_cntf_0_.Q & ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3neg_9_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3pos_0_.D = NI_D_0_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_0_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_0_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3pos_1_.D = NI_D_1_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_1_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_1_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3pos_2_.D = NI_D_2_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_2_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_2_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_2_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3pos_3_.D = NI_D_3_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_3_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_3_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_3_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3pos_4_.D = NI_D_4_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_4_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_4_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_4_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3pos_5_.D = NI_D_5_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_5_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_5_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_5_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3pos_6_.D = NI_D_6_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_6_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_6_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_6_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3pos_7_.D = NI_D_7_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_7_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_7_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_7_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3pos_8_.D = NI_D_8_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_8_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_8_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_8_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data3pos_9_.D = NI_D_9_ ; (1 pterm, 1 signal) ni_nires_reg_data3pos_9_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_data3pos_9_.CE = ni_nires_reg_gray_cnt_1_.Q & !ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 2 signals) ni_nires_reg_data3pos_9_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_0_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_0_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_0_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_0_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_0_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_0_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_0_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_10_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2pos_0_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0pos_0_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1pos_0_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3pos_0_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_10_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_10_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_11_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2pos_1_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0pos_1_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1pos_1_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3pos_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_11_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_11_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_12_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2pos_2_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0pos_2_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1pos_2_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3pos_2_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_12_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_12_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_13_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2pos_3_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0pos_3_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1pos_3_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3pos_3_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_13_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_13_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_14_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2pos_4_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0pos_4_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1pos_4_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3pos_4_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_14_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_14_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_15_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2pos_5_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0pos_5_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1pos_5_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3pos_5_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_15_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_15_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_16_.D = ni_nires_reg_data0pos_6_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_6_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_6_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_6_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_16_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_16_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_17_.D = ni_nires_reg_data0pos_7_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_7_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_7_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_7_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_17_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_17_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_18_.D = ni_nires_reg_data0pos_8_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_8_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_8_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_8_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_18_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_18_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_19_.D = ni_nires_reg_data0pos_9_.Q & !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data1pos_9_.Q & ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data3pos_9_.Q & !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q # ni_nires_reg_data2pos_9_.Q & ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_19_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_19_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_1_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_1_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_1_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_1_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_1_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_1_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_1_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_2_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_2_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_2_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_2_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_2_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_2_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_2_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_3_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_3_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_3_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_3_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_3_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_3_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_3_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_4_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_4_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_4_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_4_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_4_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_4_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_4_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_5_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_5_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_5_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_5_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_5_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_5_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_5_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_6_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_6_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_6_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_6_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_6_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_6_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_6_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_7_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_7_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_7_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_7_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_7_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_7_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_7_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_8_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_8_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_8_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_8_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_8_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_8_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_8_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_data_out_9_.D = ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data2neg_9_.Q # !ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data0neg_9_.Q # ni_nires_reg_old_cnt_0_.Q & !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data1neg_9_.Q # !ni_nires_reg_old_cnt_0_.Q & ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_data3neg_9_.Q ; (4 pterms, 6 signals) ni_nires_reg_data_out_9_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_data_out_9_.AR = 0 ; (0 pterm, 0 signal) ni_nires_reg_gray_cnt_0_.D = !ni_nires_reg_gray_cnt_1_.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cnt_0_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_gray_cnt_0_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cnt_1_.D = ni_nires_reg_gray_cnt_0_.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cnt_1_.C = NI_STR ; (1 pterm, 1 signal) ni_nires_reg_gray_cnt_1_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cntf_0_.D = !ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cntf_0_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_gray_cntf_0_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cntf_1_.D = ni_nires_reg_gray_cntf_0_.Q ; (1 pterm, 1 signal) ni_nires_reg_gray_cntf_1_.C = !NI_STR ; (1 pterm, 1 signal) ni_nires_reg_gray_cntf_1_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_new_cnt_0_.D = ni_nires_reg_gray_cntf_0_.Q ; (1 pterm, 1 signal) ni_nires_reg_new_cnt_0_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_new_cnt_0_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_new_cnt_1_.D = ni_nires_reg_gray_cntf_1_.Q ; (1 pterm, 1 signal) ni_nires_reg_new_cnt_1_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_new_cnt_1_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_0_.D = !ni_nires_reg_old_cnt_1_.Q ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_0_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_0_.CE = nx595 ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_0_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_1_.D = ni_nires_reg_old_cnt_0_.Q ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_1_.C = clk ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_1_.CE = nx595 ; (1 pterm, 1 signal) ni_nires_reg_old_cnt_1_.AR = !ni_nires_reg_clear_n_i.Q ; (1 pterm, 1 signal) ni_nires_reg_valid.D = ni_nires_reg_new_cnt_0_.Q & !ni_nires_reg_old_cnt_0_.Q # !ni_nires_reg_new_cnt_0_.Q & ni_nires_reg_old_cnt_0_.Q # ni_nires_reg_old_cnt_1_.Q & !ni_nires_reg_new_cnt_1_.Q # !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_new_cnt_1_.Q ; (4 pterms, 4 signals) ni_nires_reg_valid.C = clk ; (1 pterm, 1 signal) ni_nires_reg_valid.AR = 0 ; (0 pterm, 0 signal) ni_pattcount_0_.D = !ni_pattcount_0_.Q ; (1 pterm, 1 signal) ni_pattcount_0_.C = clk ; (1 pterm, 1 signal) ni_pattcount_0_.AR = 0 ; (0 pterm, 0 signal) ni_pattcount_1_.D = ni_pattcount_1_.Q & !ni_pattcount_0_.Q # !ni_pattcount_1_.Q & ni_pattcount_0_.Q ; (2 pterms, 2 signals) ni_pattcount_1_.C = clk ; (1 pterm, 1 signal) ni_pattcount_1_.AR = 0 ; (0 pterm, 0 signal) ni_pattcount_2_.D = !ni_pattcount_2_.Q & ni_pattcount_1_.Q & ni_pattcount_0_.Q # ni_pattcount_2_.Q & !ni_pattcount_1_.Q # ni_pattcount_2_.Q & !ni_pattcount_0_.Q ; (3 pterms, 3 signals) ni_pattcount_2_.C = clk ; (1 pterm, 1 signal) ni_pattcount_2_.AR = 0 ; (0 pterm, 0 signal) ni_pattcount_3_.D = ni_pattcount_2_.Q & ni_pattcount_1_.Q & ni_pattcount_0_.Q & !ni_pattcount_3_.Q # !ni_pattcount_0_.Q & ni_pattcount_3_.Q # !ni_pattcount_1_.Q & ni_pattcount_3_.Q # !ni_pattcount_2_.Q & ni_pattcount_3_.Q ; (4 pterms, 4 signals) ni_pattcount_3_.C = clk ; (1 pterm, 1 signal) ni_pattcount_3_.AR = 0 ; (0 pterm, 0 signal) ni_pattcount_4_.D.X1 = ni_pattcount_2_.Q & ni_pattcount_1_.Q & ni_pattcount_0_.Q & ni_pattcount_3_.Q ; (1 pterm, 4 signals) ni_pattcount_4_.D.X2 = ni_pattcount_4_.Q ; (1 pterm, 1 signal) ni_pattcount_4_.C = clk ; (1 pterm, 1 signal) ni_pattcount_4_.AR = 0 ; (0 pterm, 0 signal) ni_reg_ce_prty_bit_neg.D = TX_EN.Q & TXD_8_.Q & !ix1373 & !ix1379 # TX_EN.Q & !TXD_8_.Q & ix1373 & !ix1379 # TX_EN.Q & !TXD_8_.Q & !ix1373 & ix1379 # TX_EN.Q & TXD_8_.Q & ix1373 & ix1379 ; (4 pterms, 4 signals) ni_reg_ce_prty_bit_neg.C = clk ; (1 pterm, 1 signal) ni_reg_ce_prty_bit_neg.AR = 0 ; (0 pterm, 0 signal) ni_reg_ce_prty_bit_pos.D = TX_EN.Q & TXD_0_.Q & !ix1693 & !ix1699 # TX_EN.Q & !TXD_0_.Q & ix1693 & !ix1699 # TX_EN.Q & !TXD_0_.Q & !ix1693 & ix1699 # TX_EN.Q & TXD_0_.Q & ix1693 & ix1699 ; (4 pterms, 4 signals) ni_reg_ce_prty_bit_pos.C = clk ; (1 pterm, 1 signal) ni_reg_ce_prty_bit_pos.AR = 0 ; (0 pterm, 0 signal) ni_reg_prty_bit_neg_r.D = !( !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_4_.Q & !ni_nires_reg_data_out_11_.Q # !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_4_.Q & nx1769 # !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & nx1769 # j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !ni_nires_reg_data_out_12_.Q & nx1769 # j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & nx1715 # !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & j2c_reg_creg0hm_4_.Q & !ni_nires_reg_data_out_10_.Q # j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !ni_nires_reg_data_out_10_.Q # j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !ni_nires_reg_data_out_10_.Q # j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !ni_nires_reg_data_out_10_.Q # !j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & nx1673 # !nx1334 & !j2c_reg_creg0hm_3_.Q & j2c_reg_creg0hm_2_.Q # j2c_reg_creg0hm_3_.Q & nx1889 ) ; (12 pterms, 16 signals) ni_reg_prty_bit_neg_r.C = clk ; (1 pterm, 1 signal) ni_reg_prty_bit_neg_r.AR = 0 ; (0 pterm, 0 signal) ni_reg_prty_bit_pos_r.D = !( !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_1_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_4_.Q # nx1051 & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !j2c_reg_creg0hm_4_.Q # nx1051 & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q # j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & j2c_reg_creg0hm_2_.Q & !ni_nires_reg_data_out_7_.Q # !j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & j2c_reg_creg0hm_2_.Q & !ni_nires_reg_data_out_8_.Q # nx1051 & !ni_nires_reg_data_out_2_.Q & j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q # !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & j2c_reg_creg0hm_4_.Q & !ni_nires_reg_data_out_0_.Q # j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !ni_nires_reg_data_out_0_.Q # j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !ni_nires_reg_data_out_0_.Q # j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !ni_nires_reg_data_out_0_.Q # nx1179 & !j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & j2c_reg_creg0hm_2_.Q # nx993 & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q # nx1145 & j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & j2c_reg_creg0hm_2_.Q # nx1107 & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & j2c_reg_creg0hm_2_.Q # nx1191 & j2c_reg_creg0hm_3_.Q # !j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & nx941 ) ; (16 pterms, 20 signals) ni_reg_prty_bit_pos_r.C = clk ; (1 pterm, 1 signal) ni_reg_prty_bit_pos_r.AR = 0 ; (0 pterm, 0 signal) nx0 = !( !DIS_JTG & !jTMS ) ; (1 pterm, 2 signals) nx1051 = !( !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_4_.Q & ni_nires_reg_data_out_3_.Q # !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & ni_nires_reg_data_out_3_.Q ) ; (2 pterms, 5 signals) nx1107 = !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_4_.Q & !ni_nires_reg_data_out_5_.Q # j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_4_.Q & !ni_nires_reg_data_out_4_.Q # j2c_reg_creg0hm_5_.Q & j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_4_.Q # !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_5_.Q # j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_4_.Q ; (5 pterms, 6 signals) nx1145.X1 = j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_6_.Q # j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_4_.Q & ni_nires_reg_data_out_6_.Q & !ni_nires_reg_data_out_7_.Q # j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_4_.Q & !ni_nires_reg_data_out_6_.Q & ni_nires_reg_data_out_7_.Q ; (3 pterms, 6 signals) nx1145.X2 = !j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_7_.Q ; (1 pterm, 2 signals) nx1179 = j2c_reg_creg0hm_5_.Q & j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_5_.Q # !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_6_.Q # !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_6_.Q # j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_5_.Q ; (4 pterms, 5 signals) nx1191.X1 = !j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_9_.Q # !j2c_reg_creg0hm_5_.Q & j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_4_.Q & !ni_nires_reg_data_out_8_.Q & ni_nires_reg_data_out_9_.Q # !j2c_reg_creg0hm_5_.Q & j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_4_.Q & ni_nires_reg_data_out_8_.Q & !ni_nires_reg_data_out_9_.Q ; (3 pterms, 6 signals) nx1191.X2 = j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_8_.Q ; (1 pterm, 2 signals) nx1241 = !( !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q # !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_3_.Q ) ; (2 pterms, 4 signals) nx1291 = !( !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_3_.Q # !j2c_reg_creg1hm_3_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_2_.Q ) ; (2 pterms, 4 signals) nx1334 = !( !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_4_.Q & nx1831 # !ni_nires_reg_data_out_17_.Q & j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q # !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & nx1831 # !ni_nires_reg_data_out_18_.Q & !j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q # !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & nx1831 & !ni_nires_reg_data_out_14_.Q # j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & nx1855 # !j2c_reg_creg0hm_1_.Q & j2c_reg_creg0hm_0_.Q & nx1881 ) ; (7 pterms, 12 signals) nx1461 = !( ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q & ID_0_7_.Q & ID_0_6_.Q & ID_0_5_.Q & ID_0_4_.Q ) ; (1 pterm, 8 signals) nx1531 = !( !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_3_0_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_1_0_.Q # !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_3_1_.Q # !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_3_2_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_1_1_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_1_2_.Q # !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_3_3_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_1_3_.Q # !DIS_JTG & PRBSEN.Q & j2c_reg_cmdreg_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !DIS_JTG & SD2ANL.Q & j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & j2c_reg_creg1hm_3_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & j2c_reg_creg1hm_0_.Q ) ; (12 pterms, 17 signals) nx158 = TX_EN.Q & j2c_reg_creg1hm_3_.Q # !j2c_reg_creg1hm_3_.Q & ni_nires_reg_valid.Q ; (2 pterms, 3 signals) nx1596 = !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_2_6_.Q # !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_2_5_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & ID_0_6_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & ID_0_5_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & j2c_reg_creg0hm_6_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & j2c_reg_creg0hm_5_.Q # !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_2_4_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & ID_0_4_.Q & !j2c_bitcnt_0_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & j2c_reg_creg0hm_4_.Q ; (9 pterms, 14 signals) nx1610 = ID_0_3_.Q & ID_0_2_.Q & ID_0_1_.Q & ID_0_0_.Q & ID_0_7_.Q & ID_0_6_.Q & ID_0_5_.Q & ID_0_4_.Q ; (1 pterm, 8 signals) nx1671 = !( !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !nx1673 ) ; (1 pterm, 6 signals) nx1673 = !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_12_.Q # j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_11_.Q # j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_11_.Q # j2c_reg_creg0hm_5_.Q & !ni_nires_reg_data_out_11_.Q ; (4 pterms, 5 signals) nx1715 = !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_14_.Q # j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_13_.Q # j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_13_.Q ; (3 pterms, 4 signals) nx1769 = !( !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_4_.Q & ni_nires_reg_data_out_13_.Q # !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & ni_nires_reg_data_out_13_.Q ) ; (2 pterms, 5 signals) nx1831 = !( !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_4_.Q & ni_nires_reg_data_out_15_.Q # !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & ni_nires_reg_data_out_15_.Q ) ; (2 pterms, 5 signals) nx1855.X1 = !ni_nires_reg_data_out_16_.Q & j2c_reg_creg0hm_7_.Q # ni_nires_reg_data_out_16_.Q & !ni_nires_reg_data_out_17_.Q & j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_4_.Q # !ni_nires_reg_data_out_16_.Q & ni_nires_reg_data_out_17_.Q & j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & j2c_reg_creg0hm_6_.Q & j2c_reg_creg0hm_4_.Q ; (3 pterms, 6 signals) nx1855.X2 = !ni_nires_reg_data_out_17_.Q & !j2c_reg_creg0hm_7_.Q ; (1 pterm, 2 signals) nx1868 = !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_1_6_.Q # !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_3_6_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_1_5_.Q # !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & ID_3_5_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & j2c_reg_creg1hm_6_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & j2c_reg_creg1hm_5_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_1_4_.Q # !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & ID_3_4_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & j2c_reg_creg1hm_4_.Q ; (9 pterms, 14 signals) nx1881 = !ni_nires_reg_data_out_16_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q # !ni_nires_reg_data_out_16_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q # j2c_reg_creg0hm_5_.Q & j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_15_.Q # j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_15_.Q ; (4 pterms, 5 signals) nx1889.X1 = !ni_nires_reg_data_out_19_.Q & !j2c_reg_creg0hm_7_.Q # !ni_nires_reg_data_out_18_.Q & ni_nires_reg_data_out_19_.Q & !j2c_reg_creg0hm_5_.Q & j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_4_.Q # ni_nires_reg_data_out_18_.Q & !ni_nires_reg_data_out_19_.Q & !j2c_reg_creg0hm_5_.Q & j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !j2c_reg_creg0hm_4_.Q ; (3 pterms, 6 signals) nx1889.X2 = !ni_nires_reg_data_out_18_.Q & j2c_reg_creg0hm_7_.Q ; (1 pterm, 2 signals) nx2049 = !( !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & ID_2_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & ID_0_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & ID_2_0_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & ID_0_0_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q # !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & ID_2_3_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & ID_0_3_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & ID_2_1_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & !j2c_reg_cmdreg_1_.Q & !j2c_reg_cmdreg_2_.Q & ID_0_1_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & j2c_reg_creg0hm_3_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & j2c_reg_creg0hm_0_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & !j2c_bitcnt_1_.Q & j2c_bitcnt_0_.Q & j2c_reg_creg0hm_1_.Q # !DIS_JTG & j2c_reg_cmdreg_2_.Q & j2c_bitcnt_1_.Q & !j2c_bitcnt_0_.Q & j2c_reg_creg0hm_2_.Q ) ; (12 pterms, 17 signals) nx216 = DIS_JTG # jTCK & nx0 ; (2 pterms, 3 signals) nx595 = ni_nires_reg_new_cnt_0_.Q & !ni_nires_reg_old_cnt_0_.Q # !ni_nires_reg_new_cnt_0_.Q & ni_nires_reg_old_cnt_0_.Q # ni_nires_reg_old_cnt_1_.Q & !ni_nires_reg_new_cnt_1_.Q # !ni_nires_reg_old_cnt_1_.Q & ni_nires_reg_new_cnt_1_.Q ; (4 pterms, 4 signals) nx939 = !( !j2c_reg_creg1hm_3_.Q & !j2c_reg_creg0hm_1_.Q & !j2c_reg_creg0hm_0_.Q & !j2c_reg_creg0hm_3_.Q & !j2c_reg_creg0hm_2_.Q & !nx941 ) ; (1 pterm, 6 signals) nx941 = !ni_nires_reg_data_out_2_.Q & !j2c_reg_creg0hm_5_.Q & !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q # j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_1_.Q # j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_1_.Q # j2c_reg_creg0hm_5_.Q & !ni_nires_reg_data_out_1_.Q ; (4 pterms, 5 signals) nx993 = !j2c_reg_creg0hm_7_.Q & !j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_4_.Q # j2c_reg_creg0hm_6_.Q & !ni_nires_reg_data_out_3_.Q # j2c_reg_creg0hm_7_.Q & !ni_nires_reg_data_out_3_.Q ; (3 pterms, 4 signals)