Timing Report // Project = oase // Family = lc4k // Device = LC4256V // Speed = -3 // Voltage = 3.3 // Operating Condition = COM // Data sheet version = 3.2 // Pass Bidirection = OFF // Pass S/R = OFF // Pass Latch = OFF // Pass Clock = OFF // Maximum Paths = 20 // T_SU Endpoints D/T inputs = ON // T_SU Endpoints CE inputs = OFF // T_SU Endpoints S/R inputs = OFF // T_SU Endpoints RAM gated = ON // Fmax of CE = ON // Fmax of RAM = ON // Location(From => To) // Pin number: numeric number preceded by "p", BGA number as is // Macrocell number: Segment#,GLB#,Macrocell# // Segment#: starts from 0 (if applicable) // GLB#: starts from A..Z, AA..ZZ // Macrocell#: starts from 0 to 31 Section fMAX Maximum Operating Frequency: 128.21 MHz Clock Source From: jTMS Logic Levels: 3 Path Delay: 7.80 ns Path Expansion Source Destination ============== ====== =========== 0.52 tCOi j2c_reg_creg0i_7_.C j2c_reg_creg0i_7_.Q 1.81 tFBK+tROUTE+tBLA*5+tMCELL j2c_reg_creg0i_7_.Q nx1089.X2 0.64 tPDi nx1089.X2 nx1089 1.61 tFBK+tROUTE+tBLA+tMCELL nx1089 nx1164 0.64 tPDi nx1164 nx1164 1.56 tFBK+tROUTE+tMCELL nx1164 ni_reg_prty_bit_neg_r.D 1.02 tS ni_reg_prty_bit_neg_r.D ni_reg_prty_bit_neg_r.C Clock Source From: NI_STR Delay Level Location(From => To) Source Destination Destination_Clock ===== ===== ==================== ====== =========== ================= 4.85 1 O9 => O11 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data0pos_0_.CE NI_STR 4.85 1 O9 => D4 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data0pos_1_.CE NI_STR 4.85 1 O9 => D8 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data0pos_2_.CE NI_STR 4.85 1 O9 => E11 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data0pos_3_.CE NI_STR 4.85 1 O9 => E7 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data0pos_4_.CE NI_STR 4.85 1 O9 => M9 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data0pos_5_.CE NI_STR 4.85 1 O9 => M3 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data0pos_6_.CE NI_STR 4.85 1 O9 => D12 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data0pos_7_.CE NI_STR 4.85 1 O9 => M13 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data0pos_8_.CE NI_STR 4.85 1 O9 => D0 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data0pos_9_.CE NI_STR 4.85 1 O9 => O14 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data1pos_0_.CE NI_STR 4.85 1 O9 => D7 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data1pos_1_.CE NI_STR 4.85 1 O9 => D11 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data1pos_2_.CE NI_STR 4.85 1 O9 => E13 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data1pos_3_.CE NI_STR 4.85 1 O9 => E10 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data1pos_4_.CE NI_STR 4.85 1 O9 => M12 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data1pos_5_.CE NI_STR 4.85 1 O9 => M8 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data1pos_6_.CE NI_STR 4.85 1 O9 => D15 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data1pos_7_.CE NI_STR 4.85 1 O9 => M0 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data1pos_8_.CE NI_STR 4.85 1 O9 => D3 ni_nires_reg_gray_cnt_0_.C ni_nires_reg_data1pos_9_.CE NI_STR Clock Source From: clk Delay Level Location(From => To) Source Destination Destination_Clock ===== ===== ==================== ====== =========== ================= 7.60 3 A15 => M2 ni_nires_reg_data_out_17_.C ni_reg_prty_bit_neg_r.D clk 7.55 3 B7 => O3 ni_nires_reg_data_out_7_.C ni_reg_prty_bit_pos_r.D clk 7.55 3 A14 => M2 ni_nires_reg_data_out_16_.C ni_reg_prty_bit_neg_r.D clk 7.50 3 O10 => N6 TXD_1_.C ni_reg_ce_prty_bit_pos.D clk 7.50 3 O1 => N6 TXD_2_.C ni_reg_ce_prty_bit_pos.D clk 7.50 3 N12 => N6 TXD_3_.C ni_reg_ce_prty_bit_pos.D clk 7.50 3 N10 => N6 TXD_4_.C ni_reg_ce_prty_bit_pos.D clk 7.50 3 M1 => N6 TXD_7_.C ni_reg_ce_prty_bit_pos.D clk 7.50 3 I9 => O3 ni_nires_reg_data_out_5_.C ni_reg_prty_bit_pos_r.D clk 7.50 3 I8 => O3 ni_nires_reg_data_out_6_.C ni_reg_prty_bit_pos_r.D clk 7.50 3 I5 => M2 ni_nires_reg_data_out_15_.C ni_reg_prty_bit_neg_r.D clk 7.50 3 O3 => N6 ni_reg_prty_bit_pos_r.C ni_reg_ce_prty_bit_pos.D clk 7.15 2 A0 => A0 ni_nires_reg_old_cnt_0_.C ni_nires_reg_old_cnt_0_.CE clk 7.15 2 A0 => A1 ni_nires_reg_old_cnt_0_.C ni_nires_reg_old_cnt_1_.CE clk 7.15 2 A1 => A0 ni_nires_reg_old_cnt_1_.C ni_nires_reg_old_cnt_0_.CE clk 7.15 2 A1 => A1 ni_nires_reg_old_cnt_1_.C ni_nires_reg_old_cnt_1_.CE clk 6.85 2 O15 => A0 ni_nires_reg_new_cnt_0_.C ni_nires_reg_old_cnt_0_.CE clk 6.85 2 O15 => A1 ni_nires_reg_new_cnt_0_.C ni_nires_reg_old_cnt_1_.CE clk 6.85 2 A3 => A0 ni_nires_reg_new_cnt_1_.C ni_nires_reg_old_cnt_0_.CE clk 6.85 2 A3 => A1 ni_nires_reg_new_cnt_1_.C ni_nires_reg_old_cnt_1_.CE clk Clock Source From: jTCK Delay Level Location(From => To) Source Destination Destination_Clock ===== ===== ==================== ====== =========== ================= 7.05 2 I15 => I0 j2c_bitcnt_2_.C j2c_reg_rstout_n_i.CE jTCK 6.90 2 I3 => I0 j2c_bitcnt_0_.C j2c_reg_rstout_n_i.CE jTCK 6.90 2 I1 => I0 j2c_bitcnt_1_.C j2c_reg_rstout_n_i.CE jTCK 3.60 1 I15 => I15 j2c_bitcnt_2_.C j2c_bitcnt_2_.D jTCK 3.60 1 I15 => I0 j2c_bitcnt_2_.C j2c_reg_rstout_n_i.D jTCK 3.50 1 J7 => J10 j2c_reg_shreg_4_.C ENABLE.D jTMS 3.50 1 J7 => L3 j2c_reg_shreg_4_.C j2c_reg_cmdreg_0_.D jTMS 3.50 1 J7 => K14 j2c_reg_shreg_4_.C j2c_reg_creg0i_4_.D jTMS 3.50 1 J7 => K9 j2c_reg_shreg_4_.C j2c_reg_shreg_3_.D jTCK 3.45 1 I3 => I3 j2c_bitcnt_0_.C j2c_bitcnt_0_.D jTCK 3.45 1 I3 => I1 j2c_bitcnt_0_.C j2c_bitcnt_1_.D jTCK 3.45 1 I3 => I15 j2c_bitcnt_0_.C j2c_bitcnt_2_.D jTCK 3.45 1 I3 => I0 j2c_bitcnt_0_.C j2c_reg_rstout_n_i.D jTCK 3.45 1 I1 => I1 j2c_bitcnt_1_.C j2c_bitcnt_1_.D jTCK 3.45 1 I1 => I15 j2c_bitcnt_1_.C j2c_bitcnt_2_.D jTCK 3.45 1 I1 => I0 j2c_bitcnt_1_.C j2c_reg_rstout_n_i.D jTCK 3.45 1 K7 => K2 j2c_reg_shreg_5_.C LOOPEN.D jTMS 3.45 1 K7 => K13 j2c_reg_shreg_5_.C j2c_reg_cmdreg_1_.D jTMS 3.45 1 K7 => J15 j2c_reg_shreg_5_.C j2c_reg_creg0i_5_.D jTMS 3.45 1 K7 => J7 j2c_reg_shreg_5_.C j2c_reg_shreg_4_.D jTCK Clock Source From: jTMS Delay Level Location(From => To) Source Destination Destination_Clock ===== ===== ==================== ====== =========== ================= 7.80 3 J14 => M2 j2c_reg_creg0i_7_.C ni_reg_prty_bit_neg_r.D clk 7.80 3 J14 => O3 j2c_reg_creg0i_7_.C ni_reg_prty_bit_pos_r.D clk 7.75 3 K14 => M2 j2c_reg_creg0i_4_.C ni_reg_prty_bit_neg_r.D clk 7.75 3 K14 => O3 j2c_reg_creg0i_4_.C ni_reg_prty_bit_pos_r.D clk 7.75 3 J15 => M2 j2c_reg_creg0i_5_.C ni_reg_prty_bit_neg_r.D clk 7.75 3 J15 => O3 j2c_reg_creg0i_5_.C ni_reg_prty_bit_pos_r.D clk 7.75 3 K15 => M2 j2c_reg_creg0i_6_.C ni_reg_prty_bit_neg_r.D clk 7.75 3 K15 => O3 j2c_reg_creg0i_6_.C ni_reg_prty_bit_pos_r.D clk 7.15 2 L3 => I0 j2c_reg_cmdreg_0_.C j2c_reg_rstout_n_i.CE jTCK 7.00 2 J3 => I0 j2c_reg_cmdreg_3_.C j2c_reg_rstout_n_i.CE jTCK 5.65 2 J14 => O10 j2c_reg_creg0i_7_.C TXD_1_.D clk 5.65 2 J14 => O1 j2c_reg_creg0i_7_.C TXD_2_.D clk 5.65 2 J14 => M4 j2c_reg_creg0i_7_.C TXD_9_.D clk 5.65 2 J14 => L9 j2c_reg_creg0i_7_.C TXD_10_.D clk 5.60 2 J0 => N10 j2c_reg_creg0i_0_.C TXD_4_.D clk 5.60 2 J0 => N9 j2c_reg_creg0i_0_.C TXD_6_.D clk 5.60 2 J0 => L12 j2c_reg_creg0i_0_.C TXD_12_.D clk 5.60 2 J0 => K3 j2c_reg_creg0i_0_.C TXD_14_.D clk 5.60 2 I11 => N10 j2c_reg_creg0i_1_.C TXD_4_.D clk 5.60 2 I11 => N9 j2c_reg_creg0i_1_.C TXD_6_.D clk Section tSU tSU, tHD Level Location(From => To) Source Destination Reference_Clock =========== ===== ==================== ====== =========== =============== 2.20,- 0.20 1 p3 => K12 reset_n ni_nires_reg_clear_n_i.D clk 1.10, 1.20 1 p30 => K8 jTDI j2c_reg_shreg_7_.D jTCK 0.75, 1.55 1 p30 => J3 jTDI j2c_reg_cmdreg_3_.D jTMS 0.70, 1.60 1 p16 => F2 NI_D[3] ni_nires_reg_data3pos_3_.D NI_STR 0.60, 1.70 1 p20 => O2 NI_D[0] ni_nires_reg_data0neg_0_.D NI_STR 0.60, 1.70 1 p20 => O7 NI_D[0] ni_nires_reg_data1neg_0_.D NI_STR 0.60, 1.70 1 p20 => O4 NI_D[0] ni_nires_reg_data2neg_0_.D NI_STR 0.60, 1.70 1 p20 => O5 NI_D[0] ni_nires_reg_data3neg_0_.D NI_STR 0.45, 1.85 1 p16 => C13 NI_D[3] ni_nires_reg_data0neg_3_.D NI_STR 0.45, 1.85 1 p16 => E11 NI_D[3] ni_nires_reg_data0pos_3_.D NI_STR 0.45, 1.85 1 p16 => C0 NI_D[3] ni_nires_reg_data1neg_3_.D NI_STR 0.45, 1.85 1 p16 => E13 NI_D[3] ni_nires_reg_data1pos_3_.D NI_STR 0.45, 1.85 1 p16 => C14 NI_D[3] ni_nires_reg_data2neg_3_.D NI_STR 0.45, 1.85 1 p16 => E12 NI_D[3] ni_nires_reg_data2pos_3_.D NI_STR 0.45, 1.85 1 p16 => C15 NI_D[3] ni_nires_reg_data3neg_3_.D NI_STR 0.45, 1.85 1 p10 => B13 NI_D[7] ni_nires_reg_data0neg_7_.D NI_STR 0.45, 1.85 1 p10 => D12 NI_D[7] ni_nires_reg_data0pos_7_.D NI_STR 0.45, 1.85 1 p10 => C8 NI_D[7] ni_nires_reg_data1neg_7_.D NI_STR 0.45, 1.85 1 p10 => D15 NI_D[7] ni_nires_reg_data1pos_7_.D NI_STR 0.45, 1.85 1 p10 => C6 NI_D[7] ni_nires_reg_data2neg_7_.D NI_STR Section tRCV Delay Level Location(From => To) Source Destination ===== ===== ==================== ====== =========== 6.48 1 p3 => G7 reset_n ID_0_0_.AR 6.48 1 p3 => G3 reset_n ID_0_1_.AR 6.48 1 p3 => G0 reset_n ID_0_2_.AR 6.48 1 p3 => G15 reset_n ID_0_3_.AR 6.48 1 p3 => G1 reset_n ID_0_4_.AR 6.48 1 p3 => G6 reset_n ID_0_5_.AR 6.48 1 p3 => G5 reset_n ID_0_6_.AR 6.48 1 p3 => G4 reset_n ID_0_7_.AR 6.48 1 p3 => H5 reset_n ID_1_0_.AR 6.48 1 p3 => H3 reset_n ID_1_1_.AR 6.48 1 p3 => H2 reset_n ID_1_2_.AR 6.48 1 p3 => H4 reset_n ID_1_3_.AR 6.48 1 p3 => H7 reset_n ID_1_4_.AR 6.48 1 p3 => H6 reset_n ID_1_5_.AR 6.48 1 p3 => H10 reset_n ID_1_6_.AR 6.48 1 p3 => F4 reset_n ID_2_0_.AR 6.48 1 p3 => F9 reset_n ID_2_1_.AR 6.48 1 p3 => F7 reset_n ID_2_2_.AR 6.48 1 p3 => F6 reset_n ID_2_3_.AR 6.48 1 p3 => F8 reset_n ID_2_4_.AR Section tPD Delay Level Location(From => To) Source Destination ===== ===== ==================== ====== =========== 4.65 1 p81 => p94 FAULT LED[7] 4.65 1 p81 => p31 FAULT jTDO 4.60 1 p84 => p43 EN LED[10] 4.60 1 p49 => p41 ENABLE LED[8] 4.60 1 p53 => p42 LOOPEN LED[9] 4.60 1 p47 => p93 PRBSEN LED[6] 4.60 1 p50 => p92 TX_ER LED[5] Section tCO tCO Level Location(From => To) Source Destination Register_Clock === ===== ==================== ====== =========== ============== 9.90 3 p29 => p31 jTMS jTDO j2c_reg_creg0i_2_.C 9.90 3 p29 => p31 jTMS jTDO j2c_reg_creg0i_0_.C 9.85 3 p29 => p31 jTMS jTDO j2c_reg_creg0i_5_.C 9.85 3 p29 => p31 jTMS jTDO j2c_reg_creg0i_4_.C 9.85 3 p29 => p31 jTMS jTDO j2c_reg_creg0i_6_.C 9.80 3 p29 => p31 jTMS jTDO j2c_reg_cmdreg_1_.C 9.80 3 p29 => p31 jTMS jTDO j2c_reg_cmdreg_2_.C 9.75 3 p28 => p31 jTCK jTDO j2c_bitcnt_2_.C 9.70 3 p29 => p31 jTMS jTDO j2c_reg_cmdreg_0_.C 9.65 3 p29 => p31 jTMS jTDO ENABLE.C 9.65 3 p29 => p31 jTMS jTDO PRBSEN.C 9.65 3 p29 => p31 jTMS jTDO LOOPEN.C 9.65 3 p29 => p31 jTMS jTDO TX_ER.C 9.65 3 p29 => p31 jTMS jTDO j2c_reg_creg0i_1_.C 9.40 3 p29 => p31 jTMS jTDO TESTEN.C 9.40 3 p29 => p31 jTMS jTDO EN.C 8.00 3 p89 => p31 clk jTDO ID_3_2_.C 7.95 3 p89 => p31 clk jTDO ID_1_0_.C 7.95 3 p89 => p31 clk jTDO ID_1_5_.C 7.95 3 p89 => p31 clk jTDO ID_0_2_.C Section tOE tENA, tDIS Level Location(From => To) Source Destination =========== ===== ==================== ====== =========== 8.80, 8.80 1 p29 => G2 jTMS jTDO.OE 8.70, 8.70 1 p28 => G2 jTCK jTDO.OE Section tCOE tENA, tDIS Level Location(From => To) Source Destination =========== ===== ==================== ====== =========== 11.45, 11.45 1 p29 => P1 jTMS EN.OE 11.45, 11.45 1 p29 => J10 jTMS ENABLE.OE 11.45, 11.45 1 p29 => J6 jTMS LCKREFN.OE 11.45, 11.45 1 p29 => K2 jTMS LOOPEN.OE 11.45, 11.45 1 p29 => J4 jTMS PRBSEN.OE 11.45, 11.45 1 p29 => I12 jTMS TESTEN.OE 11.45, 11.45 1 p29 => J12 jTMS TX_ER.OE