// Batch Timer Log File (Release Version: 4.2.01.50.05_05_Starter)

//  Project = oase
//  Family  = lc4k
//  Device  = LC4256V
//  Speed   = -3
//  Voltage = 3.3
//  Operating Condition = COM
//  Data sheet version  = 3.2

//  Pass Bidirection = OFF
//  Pass S/R = OFF
//  Pass Latch = OFF
//  Pass Clock = OFF
//  Maximum Paths = 20
//  T_SU Endpoints D/T inputs = ON
//  T_SU Endpoints CE inputs = OFF
//  T_SU Endpoints S/R inputs = OFF
//  T_SU Endpoints RAM gated = ON
//  Fmax of CE = ON
//  Fmax of RAM = ON

//  Location(From => To)
//    Pin number: numeric number preceded by "p", BGA number as is
//    Macrocell number: Segment#,GLB#,Macrocell#
//                      Segment#: starts from 0 (if applicable)
//                      GLB#: starts from A..Z, AA..ZZ
//                      Macrocell#: starts from 0 to 31

//  Register-to-register critical path delay: 6.85 ns
//    -    0.52  tCOi                              ni_nires_reg_new_cnt_0_.C ==>  ni_nires_reg_new_cnt_0_.Q
//    -    1.56  tFBK+tROUTE+tMCELL                ni_nires_reg_new_cnt_0_.Q ==>  ni_nires_reg_old_cnt_0__0
//    -    0.64  tPDi                              ni_nires_reg_old_cnt_0__0 ==>  ni_nires_reg_old_cnt_0__0
//    -    1.88  tFBK+tROUTE+tPTCLK                ni_nires_reg_old_cnt_0__0 ==>  ni_nires_reg_old_cnt_0_.CE
//    -    2.25  tCES                              ni_nires_reg_old_cnt_0_.CE ==>  ni_nires_reg_old_cnt_0_.C