// Node Statistic Information File
// Tool:  ispLEVER 5.0.01.73.31.05_Starter

// Design 'top_ni' created   Wed Jan 04 17:21:46 2006


// Fmax Logic Level: 2.

// Path: ni_nires_reg_new_cnt_0_.Q
//    -> nx601
//    -> ni_nires_reg_old_cnt_1_.CE

// Signal Name: EN.D
// Type: Output_reg
BEGIN EN.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_6_.Q  	1
END

// Signal Name: EN.C
// Type: Output_reg
BEGIN EN.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: EN.CE
// Type: Output_reg
BEGIN EN.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: EN.AR
// Type: Output_reg
BEGIN EN.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: EN.AP
// Type: Output_reg
BEGIN EN.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TESTEN
// Type: Output
BEGIN TESTEN
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: SCL
// Type: Tri
BEGIN SCL
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: SCL.OE
// Type: Tri
BEGIN SCL.OE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: SDA
// Type: Bidi
BEGIN SDA
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: SDA.OE
// Type: Bidi
BEGIN SDA.OE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Input     	jTMS.BLIF           	0
END

// Signal Name: jTDO
// Type: Tri
BEGIN jTDO
Fanin Number		21
Pterm Number		15
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Input     	FAULT.BLIF          	0
Fanin Node      	j2c_reg_cmdreg_1_.Q 	1
Fanin Node      	j2c_reg_cmdreg_2_.Q 	1
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_0_.Q           	1
Fanin Node      	j2c_reg_creg1i_7_reg.Q	1
Fanin Node      	ID_0_7_.Q           	1
Fanin Node      	j2c_bitcnt_2_.Q     	3
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
Fanin Node      	nx1474.BLIF         	9
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
Fanin Node      	nx1435.BLIF         	12
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	nx1738.BLIF         	9
Fanin Node      	nx1922.BLIF         	5
Fanin Node      	nx1946.BLIF         	3
Fanin Output    	SDA.PIN             	0
END

// Signal Name: jTDO.OE
// Type: Tri
BEGIN jTDO.OE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx234.BLIF          	2
END

// Signal Name: LED_9_
// Type: Output
BEGIN LED_9_
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	LOOPEN.PIN          	1
END

// Signal Name: LED_8_
// Type: Output
BEGIN LED_8_
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	ENABLE.PIN          	1
END

// Signal Name: LED_10_.D
// Type: Output_reg
BEGIN LED_10_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_6_.Q  	1
END

// Signal Name: LED_10_.C
// Type: Output_reg
BEGIN LED_10_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: LED_10_.CE
// Type: Output_reg
BEGIN LED_10_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: LED_10_.AR
// Type: Output_reg
BEGIN LED_10_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: LED_10_.AP
// Type: Output_reg
BEGIN LED_10_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: LED_7_
// Type: Output
BEGIN LED_7_
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	FAULT.BLIF          	0
END

// Signal Name: LED_6_
// Type: Output
BEGIN LED_6_
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	PRBSEN.PIN          	1
END

// Signal Name: LED_5_
// Type: Output
BEGIN LED_5_
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TX_ER.PIN           	1
END

// Signal Name: PRBSEN.D
// Type: Bidi
BEGIN PRBSEN.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_shreg_2_.Q  	1
END

// Signal Name: PRBSEN.C
// Type: Bidi
BEGIN PRBSEN.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: PRBSEN.CE
// Type: Bidi
BEGIN PRBSEN.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: PRBSEN.AR
// Type: Bidi
BEGIN PRBSEN.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: PRBSEN.OE
// Type: Bidi
BEGIN PRBSEN.OE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1i_7_reg.Q	1
END

// Signal Name: LCKREFN.D
// Type: Tri
BEGIN LCKREFN.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_shreg_3_.Q  	1
END

// Signal Name: LCKREFN.C
// Type: Tri
BEGIN LCKREFN.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: LCKREFN.CE
// Type: Tri
BEGIN LCKREFN.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: LCKREFN.AR
// Type: Tri
BEGIN LCKREFN.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: LCKREFN.OE
// Type: Tri
BEGIN LCKREFN.OE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1i_7_reg.Q	1
END

// Signal Name: ENABLE.D
// Type: Bidi
BEGIN ENABLE.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_shreg_4_.Q  	1
END

// Signal Name: ENABLE.C
// Type: Bidi
BEGIN ENABLE.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: ENABLE.CE
// Type: Bidi
BEGIN ENABLE.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: ENABLE.AR
// Type: Bidi
BEGIN ENABLE.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ENABLE.AP
// Type: Bidi
BEGIN ENABLE.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ENABLE.OE
// Type: Bidi
BEGIN ENABLE.OE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1i_7_reg.Q	1
END

// Signal Name: TXD_14_.D
// Type: Output_reg
BEGIN TXD_14_.D
Fanin Number		9
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx1189.BLIF         	2
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	ni_nires_reg_data_out_17_.Q	4
Fanin Node      	nx1743.BLIF         	3
Fanin Node      	ni_nires_reg_data_out_18_.Q	4
END

// Signal Name: TXD_14_.C
// Type: Output_reg
BEGIN TXD_14_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_14_.CE
// Type: Output_reg
BEGIN TXD_14_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_14_.AR
// Type: Output_reg
BEGIN TXD_14_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: LOOPEN.D
// Type: Bidi
BEGIN LOOPEN.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_shreg_5_.Q  	1
END

// Signal Name: LOOPEN.C
// Type: Bidi
BEGIN LOOPEN.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: LOOPEN.CE
// Type: Bidi
BEGIN LOOPEN.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: LOOPEN.AR
// Type: Bidi
BEGIN LOOPEN.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: LOOPEN.OE
// Type: Bidi
BEGIN LOOPEN.OE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1i_7_reg.Q	1
END

// Signal Name: TXD_13_.D
// Type: Output_reg
BEGIN TXD_13_.D
Fanin Number		5
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	nx1743.BLIF         	3
Fanin Node      	nx1770.BLIF         	4
END

// Signal Name: TXD_13_.C
// Type: Output_reg
BEGIN TXD_13_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_13_.CE
// Type: Output_reg
BEGIN TXD_13_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_13_.AR
// Type: Output_reg
BEGIN TXD_13_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TX_ER.D
// Type: Bidi
BEGIN TX_ER.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_shreg_0_.Q  	1
END

// Signal Name: TX_ER.C
// Type: Bidi
BEGIN TX_ER.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: TX_ER.CE
// Type: Bidi
BEGIN TX_ER.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: TX_ER.AR
// Type: Bidi
BEGIN TX_ER.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: TX_ER.OE
// Type: Bidi
BEGIN TX_ER.OE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1i_7_reg.Q	1
END

// Signal Name: TXD_12_.D
// Type: Output_reg
BEGIN TXD_12_.D
Fanin Number		11
Pterm Number		11
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	ni_nires_reg_data_out_14_.Q	4
Fanin Node      	nx1719.BLIF         	2
Fanin Node      	nx1770.BLIF         	4
END

// Signal Name: TXD_12_.C
// Type: Output_reg
BEGIN TXD_12_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_12_.CE
// Type: Output_reg
BEGIN TXD_12_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_12_.AR
// Type: Output_reg
BEGIN TXD_12_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TX_EN.D
// Type: Output_reg
BEGIN TX_EN.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TX_EN.C
// Type: Output_reg
BEGIN TX_EN.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TX_EN.AR
// Type: Output_reg
BEGIN TX_EN.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_11_.D
// Type: Output_reg
BEGIN TXD_11_.D
Fanin Number		9
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	ni_nires_reg_data_out_14_.Q	4
Fanin Node      	nx1719.BLIF         	2
Fanin Node      	nx1782.BLIF         	3
END

// Signal Name: TXD_11_.C
// Type: Output_reg
BEGIN TXD_11_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_11_.CE
// Type: Output_reg
BEGIN TXD_11_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_11_.AR
// Type: Output_reg
BEGIN TXD_11_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_10_.D
// Type: Output_reg
BEGIN TXD_10_.D
Fanin Number		8
Pterm Number		8
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx1161.BLIF         	2
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	ni_nires_reg_data_out_12_.Q	4
Fanin Node      	nx1782.BLIF         	3
Fanin Node      	nx1808.BLIF         	2
END

// Signal Name: TXD_10_.C
// Type: Output_reg
BEGIN TXD_10_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_10_.CE
// Type: Output_reg
BEGIN TXD_10_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_10_.AR
// Type: Output_reg
BEGIN TXD_10_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_15_.D
// Type: Output_reg
BEGIN TXD_15_.D
Fanin Number		5
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	nx1613.BLIF         	3
Fanin Node      	ni_nires_reg_data_out_17_.Q	4
Fanin Node      	ni_nires_reg_data_out_18_.Q	4
END

// Signal Name: TXD_15_.C
// Type: Output_reg
BEGIN TXD_15_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_15_.CE
// Type: Output_reg
BEGIN TXD_15_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_15_.AR
// Type: Output_reg
BEGIN TXD_15_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_9_.D
// Type: Output_reg
BEGIN TXD_9_.D
Fanin Number		7
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx1161.BLIF         	2
Fanin Node      	nx1519.BLIF         	4
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	ni_nires_reg_data_out_12_.Q	4
Fanin Node      	nx1808.BLIF         	2
END

// Signal Name: TXD_9_.C
// Type: Output_reg
BEGIN TXD_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_9_.CE
// Type: Output_reg
BEGIN TXD_9_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_9_.AR
// Type: Output_reg
BEGIN TXD_9_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_8_.D.X1
// Type: Output_reg
BEGIN TXD_8_.D.X1
Fanin Number		10
Pterm Number		6
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_10_.Q	4
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	nx1601.BLIF         	1
END

// Signal Name: TXD_8_.D.X2
// Type: Output_reg
BEGIN TXD_8_.D.X2
Fanin Number		5
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx1519.BLIF         	4
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
END

// Signal Name: TXD_8_.C
// Type: Output_reg
BEGIN TXD_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_8_.CE
// Type: Output_reg
BEGIN TXD_8_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_8_.AR
// Type: Output_reg
BEGIN TXD_8_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_7_.D
// Type: Output_reg
BEGIN TXD_7_.D
Fanin Number		5
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ni_nires_reg_data_out_8_.Q	4
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	nx939.BLIF          	3
Fanin Node      	ni_nires_reg_data_out_7_.Q	4
END

// Signal Name: TXD_7_.C
// Type: Output_reg
BEGIN TXD_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_7_.CE
// Type: Output_reg
BEGIN TXD_7_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_7_.AR
// Type: Output_reg
BEGIN TXD_7_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_6_.D
// Type: Output_reg
BEGIN TXD_6_.D
Fanin Number		9
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ni_nires_reg_data_out_8_.Q	4
Fanin Node      	nx1083.BLIF         	3
Fanin Node      	nx1189.BLIF         	2
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	ni_nires_reg_data_out_7_.Q	4
END

// Signal Name: TXD_6_.C
// Type: Output_reg
BEGIN TXD_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_6_.CE
// Type: Output_reg
BEGIN TXD_6_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_6_.AR
// Type: Output_reg
BEGIN TXD_6_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: SD2ANL.D
// Type: Tri
BEGIN SD2ANL.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_shreg_1_.Q  	1
END

// Signal Name: SD2ANL.C
// Type: Tri
BEGIN SD2ANL.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: SD2ANL.CE
// Type: Tri
BEGIN SD2ANL.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: SD2ANL.AR
// Type: Tri
BEGIN SD2ANL.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: SD2ANL.AP
// Type: Tri
BEGIN SD2ANL.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: SD2ANL.OE
// Type: Tri
BEGIN SD2ANL.OE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg1i_7_reg.Q	1
END

// Signal Name: TXD_5_.D
// Type: Output_reg
BEGIN TXD_5_.D
Fanin Number		5
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx1083.BLIF         	3
Fanin Node      	nx1113.BLIF         	4
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
END

// Signal Name: TXD_5_.C
// Type: Output_reg
BEGIN TXD_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_5_.CE
// Type: Output_reg
BEGIN TXD_5_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_5_.AR
// Type: Output_reg
BEGIN TXD_5_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_4_.D
// Type: Output_reg
BEGIN TXD_4_.D
Fanin Number		6
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx1113.BLIF         	4
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	nx1033.BLIF         	5
END

// Signal Name: TXD_4_.C
// Type: Output_reg
BEGIN TXD_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_4_.CE
// Type: Output_reg
BEGIN TXD_4_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_4_.AR
// Type: Output_reg
BEGIN TXD_4_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_3_.D
// Type: Output_reg
BEGIN TXD_3_.D
Fanin Number		4
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx1129.BLIF         	3
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	nx1033.BLIF         	5
END

// Signal Name: TXD_3_.C
// Type: Output_reg
BEGIN TXD_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_3_.CE
// Type: Output_reg
BEGIN TXD_3_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_3_.AR
// Type: Output_reg
BEGIN TXD_3_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_2_.D
// Type: Output_reg
BEGIN TXD_2_.D
Fanin Number		8
Pterm Number		8
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx1129.BLIF         	3
Fanin Node      	nx1161.BLIF         	2
Fanin Node      	nx1165.BLIF         	2
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	ni_nires_reg_data_out_2_.Q	4
END

// Signal Name: TXD_2_.C
// Type: Output_reg
BEGIN TXD_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_2_.CE
// Type: Output_reg
BEGIN TXD_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_2_.AR
// Type: Output_reg
BEGIN TXD_2_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_1_.D
// Type: Output_reg
BEGIN TXD_1_.D
Fanin Number		7
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx1161.BLIF         	2
Fanin Node      	nx1165.BLIF         	2
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	nx815.BLIF          	4
Fanin Node      	ni_nires_reg_data_out_2_.Q	4
END

// Signal Name: TXD_1_.C
// Type: Output_reg
BEGIN TXD_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_1_.CE
// Type: Output_reg
BEGIN TXD_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_1_.AR
// Type: Output_reg
BEGIN TXD_1_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: TXD_0_.D
// Type: Output_reg
BEGIN TXD_0_.D
Fanin Number		11
Pterm Number		9
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	nx815.BLIF          	4
Fanin Node      	ni_nires_reg_data_out_0_.Q	4
Fanin Node      	nx923.BLIF          	1
END

// Signal Name: TXD_0_.C
// Type: Output_reg
BEGIN TXD_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: TXD_0_.CE
// Type: Output_reg
BEGIN TXD_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_valid.Q	4
END

// Signal Name: TXD_0_.AR
// Type: Output_reg
BEGIN TXD_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data_out_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_8_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_data2neg_8_.Q	1
Fanin Node      	ni_nires_reg_data3neg_8_.Q	1
Fanin Node      	ni_nires_reg_data0neg_8_.Q	1
Fanin Node      	ni_nires_reg_data1neg_8_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_8_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_8_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2neg_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data2neg_8_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_8_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3neg_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_8_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_8_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0neg_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_8_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_8_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1083.X1
// Type: Node
BEGIN nx1083.X1
Fanin Number		6
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_6_.Q	4
Fanin Node      	ni_nires_reg_data_out_7_.Q	4
END

// Signal Name: nx1083.X2
// Type: Node
BEGIN nx1083.X2
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	ni_nires_reg_data_out_7_.Q	4
END

// Signal Name: ni_nires_reg_data1neg_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_8_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_8_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data_out_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_9_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_data2neg_9_.Q	1
Fanin Node      	ni_nires_reg_data3neg_9_.Q	1
Fanin Node      	ni_nires_reg_data0neg_9_.Q	1
Fanin Node      	ni_nires_reg_data1neg_9_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_9_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_9_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2neg_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data2neg_9_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_9_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3neg_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_9_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_9_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0neg_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_9_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_9_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1neg_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_9_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_9_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1113
// Type: Node
BEGIN nx1113
Fanin Number		5
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_5_.Q	4
Fanin Node      	ni_nires_reg_data_out_6_.Q	4
END

// Signal Name: j2c_reg_cmdreg_1_.D
// Type: Node_reg
BEGIN j2c_reg_cmdreg_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_5_.Q  	1
END

// Signal Name: j2c_reg_cmdreg_1_.C
// Type: Node_reg
BEGIN j2c_reg_cmdreg_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_cmdreg_1_.CE
// Type: Node_reg
BEGIN j2c_reg_cmdreg_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
END

// Signal Name: j2c_reg_cmdreg_1_.AR
// Type: Node_reg
BEGIN j2c_reg_cmdreg_1_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_cmdreg_1_.AP
// Type: Node_reg
BEGIN j2c_reg_cmdreg_1_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: j2c_reg_cmdreg_2_.D
// Type: Node_reg
BEGIN j2c_reg_cmdreg_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_6_.Q  	1
END

// Signal Name: j2c_reg_cmdreg_2_.C
// Type: Node_reg
BEGIN j2c_reg_cmdreg_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_cmdreg_2_.CE
// Type: Node_reg
BEGIN j2c_reg_cmdreg_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
END

// Signal Name: j2c_reg_cmdreg_2_.AR
// Type: Node_reg
BEGIN j2c_reg_cmdreg_2_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_cmdreg_2_.AP
// Type: Node_reg
BEGIN j2c_reg_cmdreg_2_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ID_2_2_.D
// Type: Node_reg
BEGIN ID_2_2_.D
Fanin Number		3
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
END

// Signal Name: ID_2_2_.C
// Type: Node_reg
BEGIN ID_2_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_2_.CE
// Type: Node_reg
BEGIN ID_2_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_neg.Q	4
END

// Signal Name: ID_2_2_.AR
// Type: Node_reg
BEGIN ID_2_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ni_reg_ce_prty_bit_neg.D
// Type: Node_reg
BEGIN ni_reg_ce_prty_bit_neg.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Output    	TX_EN.Q             	1
Fanin Node      	ix1217.BLIF         	4
Fanin Node      	ix1223.BLIF         	4
Fanin Output    	TXD_8_.Q            	6
END

// Signal Name: ni_reg_ce_prty_bit_neg.C
// Type: Node_reg
BEGIN ni_reg_ce_prty_bit_neg.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_reg_ce_prty_bit_neg.AR
// Type: Node_reg
BEGIN ni_reg_ce_prty_bit_neg.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1129
// Type: Node
BEGIN nx1129
Fanin Number		4
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_3_.Q	4
Fanin Node      	ni_nires_reg_data_out_4_.Q	4
END

// Signal Name: ni_reg_prty_bit_neg_r.D
// Type: Node_reg
BEGIN ni_reg_prty_bit_neg_r.D
Fanin Number		22
Pterm Number		14
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx1161.BLIF         	2
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_10_.Q	4
Fanin Node      	nx1519.BLIF         	4
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	ni_nires_reg_data_out_12_.Q	4
Fanin Node      	nx1601.BLIF         	1
Fanin Node      	nx1613.BLIF         	3
Fanin Node      	ni_nires_reg_data_out_14_.Q	4
Fanin Node      	nx1719.BLIF         	2
Fanin Node      	ni_nires_reg_data_out_17_.Q	4
Fanin Node      	nx1743.BLIF         	3
Fanin Node      	nx1770.BLIF         	4
Fanin Node      	ni_nires_reg_data_out_18_.Q	4
Fanin Node      	nx1782.BLIF         	3
Fanin Node      	nx1808.BLIF         	2
END

// Signal Name: ni_reg_prty_bit_neg_r.C
// Type: Node_reg
BEGIN ni_reg_prty_bit_neg_r.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_reg_prty_bit_neg_r.AR
// Type: Node_reg
BEGIN ni_reg_prty_bit_neg_r.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ix1217.X1
// Type: Node
BEGIN ix1217.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_15_.Q           	3
Fanin Output    	TXD_14_.Q           	4
Fanin Output    	TXD_13_.Q           	4
END

// Signal Name: ix1217.X2
// Type: Node
BEGIN ix1217.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_reg_prty_bit_neg_r.Q	14
END

// Signal Name: ix1223.X1
// Type: Node
BEGIN ix1223.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_11_.Q           	5
Fanin Output    	TXD_10_.Q           	8
Fanin Output    	TXD_9_.Q            	5
END

// Signal Name: ix1223.X2
// Type: Node
BEGIN ix1223.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_12_.Q           	11
END

// Signal Name: nx1161
// Type: Node
BEGIN nx1161
Fanin Number		4
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
END

// Signal Name: nx1165
// Type: Node
BEGIN nx1165
Fanin Number		5
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_3_.Q	4
END

// Signal Name: ID_2_1_.D
// Type: Node_reg
BEGIN ID_2_1_.D
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
END

// Signal Name: ID_2_1_.C
// Type: Node_reg
BEGIN ID_2_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_1_.CE
// Type: Node_reg
BEGIN ID_2_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_neg.Q	4
END

// Signal Name: ID_2_1_.AR
// Type: Node_reg
BEGIN ID_2_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ID_2_0_.D
// Type: Node_reg
BEGIN ID_2_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_0_.Q           	1
END

// Signal Name: ID_2_0_.C
// Type: Node_reg
BEGIN ID_2_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_0_.CE
// Type: Node_reg
BEGIN ID_2_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_neg.Q	4
END

// Signal Name: ID_2_0_.AR
// Type: Node_reg
BEGIN ID_2_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: nx1189
// Type: Node
BEGIN nx1189
Fanin Number		4
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
END

// Signal Name: ID_0_3_.D
// Type: Node_reg
BEGIN ID_0_3_.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_3_.C
// Type: Node_reg
BEGIN ID_0_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_3_.CE
// Type: Node_reg
BEGIN ID_0_3_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_0_3_.AR
// Type: Node_reg
BEGIN ID_0_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ID_0_2_.D
// Type: Node_reg
BEGIN ID_0_2_.D
Fanin Number		3
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_2_.C
// Type: Node_reg
BEGIN ID_0_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_2_.CE
// Type: Node_reg
BEGIN ID_0_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_0_2_.AR
// Type: Node_reg
BEGIN ID_0_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: j2c_reg_creg1i_6_reg.D
// Type: Node_reg
BEGIN j2c_reg_creg1i_6_reg.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_6_.Q  	1
END

// Signal Name: j2c_reg_creg1i_6_reg.C
// Type: Node_reg
BEGIN j2c_reg_creg1i_6_reg.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_creg1i_6_reg.CE
// Type: Node_reg
BEGIN j2c_reg_creg1i_6_reg.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: j2c_reg_creg1i_6_reg.AR
// Type: Node_reg
BEGIN j2c_reg_creg1i_6_reg.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_creg1i_6_reg.AP
// Type: Node_reg
BEGIN j2c_reg_creg1i_6_reg.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ID_0_1_.D
// Type: Node_reg
BEGIN ID_0_1_.D
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_1_.C
// Type: Node_reg
BEGIN ID_0_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_1_.CE
// Type: Node_reg
BEGIN ID_0_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_0_1_.AR
// Type: Node_reg
BEGIN ID_0_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ID_0_0_.D
// Type: Node_reg
BEGIN ID_0_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_0_.C
// Type: Node_reg
BEGIN ID_0_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_0_.CE
// Type: Node_reg
BEGIN ID_0_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_0_0_.AR
// Type: Node_reg
BEGIN ID_0_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: j2c_reg_creg1i_7_reg.D
// Type: Node_reg
BEGIN j2c_reg_creg1i_7_reg.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_7_.Q  	1
END

// Signal Name: j2c_reg_creg1i_7_reg.C
// Type: Node_reg
BEGIN j2c_reg_creg1i_7_reg.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_creg1i_7_reg.CE
// Type: Node_reg
BEGIN j2c_reg_creg1i_7_reg.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: j2c_reg_creg1i_7_reg.AR
// Type: Node_reg
BEGIN j2c_reg_creg1i_7_reg.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_creg1i_7_reg.AP
// Type: Node_reg
BEGIN j2c_reg_creg1i_7_reg.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ID_2_3_.D
// Type: Node_reg
BEGIN ID_2_3_.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
Fanin Node      	ID_2_3_.Q           	4
END

// Signal Name: ID_2_3_.C
// Type: Node_reg
BEGIN ID_2_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_3_.CE
// Type: Node_reg
BEGIN ID_2_3_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_neg.Q	4
END

// Signal Name: ID_2_3_.AR
// Type: Node_reg
BEGIN ID_2_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ID_0_7_.T
// Type: Node_reg
BEGIN ID_0_7_.T
Fanin Number		7
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
Fanin Node      	ID_0_6_.Q           	1
Fanin Node      	ID_0_5_.Q           	1
Fanin Node      	ID_0_4_.Q           	1
END

// Signal Name: ID_0_7_.C
// Type: Node_reg
BEGIN ID_0_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_7_.CE
// Type: Node_reg
BEGIN ID_0_7_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_0_7_.AR
// Type: Node_reg
BEGIN ID_0_7_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ID_0_6_.T
// Type: Node_reg
BEGIN ID_0_6_.T
Fanin Number		6
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
Fanin Node      	ID_0_5_.Q           	1
Fanin Node      	ID_0_4_.Q           	1
END

// Signal Name: ID_0_6_.C
// Type: Node_reg
BEGIN ID_0_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_6_.CE
// Type: Node_reg
BEGIN ID_0_6_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_0_6_.AR
// Type: Node_reg
BEGIN ID_0_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ID_0_5_.T
// Type: Node_reg
BEGIN ID_0_5_.T
Fanin Number		5
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
Fanin Node      	ID_0_4_.Q           	1
END

// Signal Name: ID_0_5_.C
// Type: Node_reg
BEGIN ID_0_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_5_.CE
// Type: Node_reg
BEGIN ID_0_5_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_0_5_.AR
// Type: Node_reg
BEGIN ID_0_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ID_0_4_.D.X1
// Type: Node_reg
BEGIN ID_0_4_.D.X1
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
END

// Signal Name: ID_0_4_.D.X2
// Type: Node_reg
BEGIN ID_0_4_.D.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_0_4_.Q           	1
END

// Signal Name: ID_0_4_.C
// Type: Node_reg
BEGIN ID_0_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_0_4_.CE
// Type: Node_reg
BEGIN ID_0_4_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_0_4_.AR
// Type: Node_reg
BEGIN ID_0_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: nx234
// Type: Node
BEGIN nx234
Fanin Number		3
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Input     	jTCK.BLIF           	0
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: ni_nires_reg_valid.D
// Type: Node_reg
BEGIN ni_nires_reg_valid.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_new_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_new_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_valid.C
// Type: Node_reg
BEGIN ni_nires_reg_valid.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_valid.AR
// Type: Node_reg
BEGIN ni_nires_reg_valid.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_new_cnt_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_new_cnt_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
END

// Signal Name: ni_nires_reg_new_cnt_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_new_cnt_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_new_cnt_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_new_cnt_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ni_nires_reg_gray_cntf_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_gray_cntf_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_gray_cntf_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_gray_cntf_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_gray_cntf_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_gray_cntf_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ni_nires_reg_gray_cntf_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_gray_cntf_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
END

// Signal Name: ni_nires_reg_gray_cntf_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_gray_cntf_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_gray_cntf_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_gray_cntf_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ni_nires_reg_clear_n_i.D
// Type: Node_reg
BEGIN ni_nires_reg_clear_n_i.D
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	reset_n.BLIF        	0
Fanin Node      	j2c_reg_rstout_n_i.Q	1
END

// Signal Name: ni_nires_reg_clear_n_i.C
// Type: Node_reg
BEGIN ni_nires_reg_clear_n_i.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_clear_n_i.AR
// Type: Node_reg
BEGIN ni_nires_reg_clear_n_i.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ID_2_6_.T
// Type: Node_reg
BEGIN ID_2_6_.T
Fanin Number		6
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
Fanin Node      	ID_2_3_.Q           	4
Fanin Node      	ID_2_5_.Q           	1
Fanin Node      	ID_2_4_.Q           	1
END

// Signal Name: ID_2_6_.C
// Type: Node_reg
BEGIN ID_2_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_6_.CE
// Type: Node_reg
BEGIN ID_2_6_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_neg.Q	4
END

// Signal Name: ID_2_6_.AR
// Type: Node_reg
BEGIN ID_2_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: j2c_reg_rstout_n_i.D
// Type: Node_reg
BEGIN j2c_reg_rstout_n_i.D
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_bitcnt_2_.Q     	3
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
END

// Signal Name: j2c_reg_rstout_n_i.C
// Type: Node_reg
BEGIN j2c_reg_rstout_n_i.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_rstout_n_i.CE
// Type: Node_reg
BEGIN j2c_reg_rstout_n_i.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	j2c_reg_rstout_n_i_0.BLIF	2
END

// Signal Name: j2c_reg_rstout_n_i.AR
// Type: Node_reg
BEGIN j2c_reg_rstout_n_i.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_rstout_n_i.AP
// Type: Node_reg
BEGIN j2c_reg_rstout_n_i.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: ID_2_5_.T
// Type: Node_reg
BEGIN ID_2_5_.T
Fanin Number		5
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
Fanin Node      	ID_2_3_.Q           	4
Fanin Node      	ID_2_4_.Q           	1
END

// Signal Name: ID_2_5_.C
// Type: Node_reg
BEGIN ID_2_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_5_.CE
// Type: Node_reg
BEGIN ID_2_5_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_neg.Q	4
END

// Signal Name: ID_2_5_.AR
// Type: Node_reg
BEGIN ID_2_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: j2c_bitcnt_2_.D
// Type: Node_reg
BEGIN j2c_bitcnt_2_.D
Fanin Number		3
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_bitcnt_2_.Q     	3
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
END

// Signal Name: j2c_bitcnt_2_.C
// Type: Node_reg
BEGIN j2c_bitcnt_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_bitcnt_2_.AR
// Type: Node_reg
BEGIN j2c_bitcnt_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: ID_2_4_.D.X1
// Type: Node_reg
BEGIN ID_2_4_.D.X1
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_2_.Q           	3
Fanin Node      	ID_2_1_.Q           	2
Fanin Node      	ID_2_0_.Q           	1
Fanin Node      	ID_2_3_.Q           	4
END

// Signal Name: ID_2_4_.D.X2
// Type: Node_reg
BEGIN ID_2_4_.D.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_2_4_.Q           	1
END

// Signal Name: ID_2_4_.C
// Type: Node_reg
BEGIN ID_2_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_2_4_.CE
// Type: Node_reg
BEGIN ID_2_4_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_neg.Q	4
END

// Signal Name: ID_2_4_.AR
// Type: Node_reg
BEGIN ID_2_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: j2c_bitcnt_1_.D
// Type: Node_reg
BEGIN j2c_bitcnt_1_.D
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
END

// Signal Name: j2c_bitcnt_1_.C
// Type: Node_reg
BEGIN j2c_bitcnt_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_bitcnt_1_.AR
// Type: Node_reg
BEGIN j2c_bitcnt_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: nx1387
// Type: Node
BEGIN nx1387
Fanin Number		8
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
Fanin Node      	ID_0_7_.Q           	1
Fanin Node      	ID_0_6_.Q           	1
Fanin Node      	ID_0_5_.Q           	1
Fanin Node      	ID_0_4_.Q           	1
END

// Signal Name: j2c_bitcnt_0_.D
// Type: Node_reg
BEGIN j2c_bitcnt_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_bitcnt_0_.Q     	1
END

// Signal Name: j2c_bitcnt_0_.C
// Type: Node_reg
BEGIN j2c_bitcnt_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_bitcnt_0_.AR
// Type: Node_reg
BEGIN j2c_bitcnt_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: nx599
// Type: Node
BEGIN nx599
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Input     	jTMS.BLIF           	0
END

// Signal Name: nx1474
// Type: Node
BEGIN nx1474
Fanin Number		14
Pterm Number		9
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Node      	j2c_reg_cmdreg_1_.Q 	1
Fanin Node      	j2c_reg_cmdreg_2_.Q 	1
Fanin Node      	ID_0_6_.Q           	1
Fanin Node      	ID_0_5_.Q           	1
Fanin Node      	ID_0_4_.Q           	1
Fanin Node      	ID_2_6_.Q           	1
Fanin Node      	ID_2_5_.Q           	1
Fanin Node      	ID_2_4_.Q           	1
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
END

// Signal Name: ID_3_2_.D
// Type: Node_reg
BEGIN ID_3_2_.D
Fanin Number		3
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
END

// Signal Name: ID_3_2_.C
// Type: Node_reg
BEGIN ID_3_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_2_.CE
// Type: Node_reg
BEGIN ID_3_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_pos.Q	4
END

// Signal Name: ID_3_2_.AR
// Type: Node_reg
BEGIN ID_3_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ni_reg_ce_prty_bit_pos.D
// Type: Node_reg
BEGIN ni_reg_ce_prty_bit_pos.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Output    	TX_EN.Q             	1
Fanin Output    	TXD_0_.Q            	9
Fanin Node      	ix1547.BLIF         	4
Fanin Node      	ix1553.BLIF         	4
END

// Signal Name: ni_reg_ce_prty_bit_pos.C
// Type: Node_reg
BEGIN ni_reg_ce_prty_bit_pos.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_reg_ce_prty_bit_pos.AR
// Type: Node_reg
BEGIN ni_reg_ce_prty_bit_pos.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_cmdreg_3_.D
// Type: Node_reg
BEGIN j2c_reg_cmdreg_3_.D
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_shreg_7_.Q  	1
END

// Signal Name: j2c_reg_cmdreg_3_.C
// Type: Node_reg
BEGIN j2c_reg_cmdreg_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_cmdreg_3_.AR
// Type: Node_reg
BEGIN j2c_reg_cmdreg_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ni_reg_prty_bit_pos_r.D
// Type: Node_reg
BEGIN ni_reg_prty_bit_pos_r.D
Fanin Number		21
Pterm Number		12
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ni_nires_reg_data_out_8_.Q	4
Fanin Node      	nx1083.BLIF         	3
Fanin Node      	nx1113.BLIF         	4
Fanin Node      	nx1129.BLIF         	3
Fanin Node      	nx1161.BLIF         	2
Fanin Node      	nx1165.BLIF         	2
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
Fanin Node      	nx815.BLIF          	4
Fanin Node      	ni_nires_reg_data_out_0_.Q	4
Fanin Node      	ni_nires_reg_data_out_2_.Q	4
Fanin Node      	nx923.BLIF          	1
Fanin Node      	nx939.BLIF          	3
Fanin Node      	nx1033.BLIF         	5
Fanin Node      	ni_nires_reg_data_out_7_.Q	4
END

// Signal Name: ni_reg_prty_bit_pos_r.C
// Type: Node_reg
BEGIN ni_reg_prty_bit_pos_r.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_reg_prty_bit_pos_r.AR
// Type: Node_reg
BEGIN ni_reg_prty_bit_pos_r.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_shreg_7_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
END

// Signal Name: j2c_reg_shreg_7_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_shreg_7_.AR
// Type: Node_reg
BEGIN j2c_reg_shreg_7_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_cmdreg_0_.D
// Type: Node_reg
BEGIN j2c_reg_cmdreg_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_4_.Q  	1
END

// Signal Name: j2c_reg_cmdreg_0_.C
// Type: Node_reg
BEGIN j2c_reg_cmdreg_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_cmdreg_0_.CE
// Type: Node_reg
BEGIN j2c_reg_cmdreg_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTDI.BLIF           	0
END

// Signal Name: j2c_reg_cmdreg_0_.AR
// Type: Node_reg
BEGIN j2c_reg_cmdreg_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_cmdreg_0_.AP
// Type: Node_reg
BEGIN j2c_reg_cmdreg_0_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: j2c_reg_shreg_4_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_5_.Q  	1
END

// Signal Name: j2c_reg_shreg_4_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_shreg_4_.AR
// Type: Node_reg
BEGIN j2c_reg_shreg_4_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_shreg_5_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_6_.Q  	1
END

// Signal Name: j2c_reg_shreg_5_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_shreg_5_.AR
// Type: Node_reg
BEGIN j2c_reg_shreg_5_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ix1547.X1
// Type: Node
BEGIN ix1547.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_6_.Q            	4
Fanin Output    	TXD_5_.Q            	4
Fanin Node      	ni_reg_prty_bit_pos_r.Q	12
END

// Signal Name: ix1547.X2
// Type: Node
BEGIN ix1547.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_7_.Q            	3
END

// Signal Name: j2c_reg_shreg_6_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_7_.Q  	1
END

// Signal Name: j2c_reg_shreg_6_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_shreg_6_.AR
// Type: Node_reg
BEGIN j2c_reg_shreg_6_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1435
// Type: Node
BEGIN nx1435
Fanin Number		17
Pterm Number		12
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Node      	j2c_reg_cmdreg_1_.Q 	1
Fanin Node      	j2c_reg_cmdreg_2_.Q 	1
Fanin Output    	LCKREFN.Q           	1
Fanin Output    	PRBSEN.Q            	1
Fanin Output    	SD2ANL.Q            	1
Fanin Output    	TX_ER.Q             	1
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
Fanin Node      	ID_1_3_.Q           	1
Fanin Node      	ID_1_2_.Q           	4
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
Fanin Node      	ID_3_3_.Q           	4
END

// Signal Name: ix1553.X1
// Type: Node
BEGIN ix1553.X1
Fanin Number		3
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_3_.Q            	3
Fanin Output    	TXD_2_.Q            	8
Fanin Output    	TXD_1_.Q            	5
END

// Signal Name: ix1553.X2
// Type: Node
BEGIN ix1553.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Output    	TXD_4_.Q            	5
END

// Signal Name: ni_nires_reg_old_cnt_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_old_cnt_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_old_cnt_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx601.BLIF          	4
END

// Signal Name: ni_nires_reg_old_cnt_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: nx601
// Type: Node
BEGIN nx601
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_new_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_new_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_old_cnt_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_old_cnt_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_old_cnt_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx601.BLIF          	4
END

// Signal Name: ni_nires_reg_old_cnt_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_old_cnt_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ID_3_1_.D
// Type: Node_reg
BEGIN ID_3_1_.D
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
END

// Signal Name: ID_3_1_.C
// Type: Node_reg
BEGIN ID_3_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_1_.CE
// Type: Node_reg
BEGIN ID_3_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_pos.Q	4
END

// Signal Name: ID_3_1_.AR
// Type: Node_reg
BEGIN ID_3_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ID_3_0_.D
// Type: Node_reg
BEGIN ID_3_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_0_.Q           	1
END

// Signal Name: ID_3_0_.C
// Type: Node_reg
BEGIN ID_3_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_0_.CE
// Type: Node_reg
BEGIN ID_3_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_pos.Q	4
END

// Signal Name: ID_3_0_.AR
// Type: Node_reg
BEGIN ID_3_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ni_nires_reg_new_cnt_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_new_cnt_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_new_cnt_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_new_cnt_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_new_cnt_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_new_cnt_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ni_nires_reg_data_out_11_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_11_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2pos_1_.Q	1
Fanin Node      	ni_nires_reg_data3pos_1_.Q	1
Fanin Node      	ni_nires_reg_data0pos_1_.Q	1
Fanin Node      	ni_nires_reg_data1pos_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_11_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_11_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_11_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_11_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2pos_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data2pos_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_1_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ID_1_3_.D.X1
// Type: Node_reg
BEGIN ID_1_3_.D.X1
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_1_3_.Q           	1
END

// Signal Name: ID_1_3_.D.X2
// Type: Node_reg
BEGIN ID_1_3_.D.X2
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_1_2_.Q           	4
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
Fanin Node      	nx1578.BLIF         	1
END

// Signal Name: ID_1_3_.C
// Type: Node_reg
BEGIN ID_1_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_3_.CE
// Type: Node_reg
BEGIN ID_1_3_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_1_3_.AR
// Type: Node_reg
BEGIN ID_1_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ni_nires_reg_gray_cnt_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_gray_cnt_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_gray_cnt_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_gray_cnt_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_gray_cnt_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_gray_cnt_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ID_1_2_.D
// Type: Node_reg
BEGIN ID_1_2_.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx1387.BLIF         	1
Fanin Node      	ID_1_2_.Q           	4
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
END

// Signal Name: ID_1_2_.C
// Type: Node_reg
BEGIN ID_1_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_2_.CE
// Type: Node_reg
BEGIN ID_1_2_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_1_2_.AR
// Type: Node_reg
BEGIN ID_1_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ni_nires_reg_gray_cnt_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_gray_cnt_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
END

// Signal Name: ni_nires_reg_gray_cnt_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_gray_cnt_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_gray_cnt_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_gray_cnt_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_clear_n_i.Q	1
END

// Signal Name: ID_1_1_.D
// Type: Node_reg
BEGIN ID_1_1_.D
Fanin Number		3
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	nx1387.BLIF         	1
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
END

// Signal Name: ID_1_1_.C
// Type: Node_reg
BEGIN ID_1_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_1_.CE
// Type: Node_reg
BEGIN ID_1_1_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_1_1_.AR
// Type: Node_reg
BEGIN ID_1_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ID_1_0_.D
// Type: Node_reg
BEGIN ID_1_0_.D
Fanin Number		2
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_1_0_.Q           	2
Fanin Node      	nx1578.BLIF         	1
END

// Signal Name: ID_1_0_.C
// Type: Node_reg
BEGIN ID_1_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_0_.CE
// Type: Node_reg
BEGIN ID_1_0_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_1_0_.AR
// Type: Node_reg
BEGIN ID_1_0_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: nx1578
// Type: Node
BEGIN nx1578
Fanin Number		8
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_0_2_.Q           	3
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	ID_0_0_.Q           	1
Fanin Node      	ID_0_7_.Q           	1
Fanin Node      	ID_0_6_.Q           	1
Fanin Node      	ID_0_5_.Q           	1
Fanin Node      	ID_0_4_.Q           	1
END

// Signal Name: ni_nires_reg_data3pos_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_1_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0pos_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_1_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1pos_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_1_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_creg0i_4_.D
// Type: Node_reg
BEGIN j2c_reg_creg0i_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_4_.Q  	1
END

// Signal Name: j2c_reg_creg0i_4_.C
// Type: Node_reg
BEGIN j2c_reg_creg0i_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_creg0i_4_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0i_4_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: j2c_reg_creg0i_4_.AR
// Type: Node_reg
BEGIN j2c_reg_creg0i_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ID_3_3_.D
// Type: Node_reg
BEGIN ID_3_3_.D
Fanin Number		4
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
Fanin Node      	ID_3_3_.Q           	4
END

// Signal Name: ID_3_3_.C
// Type: Node_reg
BEGIN ID_3_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_3_.CE
// Type: Node_reg
BEGIN ID_3_3_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_pos.Q	4
END

// Signal Name: ID_3_3_.AR
// Type: Node_reg
BEGIN ID_3_3_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: j2c_reg_creg0i_5_.D
// Type: Node_reg
BEGIN j2c_reg_creg0i_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_5_.Q  	1
END

// Signal Name: j2c_reg_creg0i_5_.C
// Type: Node_reg
BEGIN j2c_reg_creg0i_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_creg0i_5_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0i_5_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: j2c_reg_creg0i_5_.AR
// Type: Node_reg
BEGIN j2c_reg_creg0i_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: j2c_reg_creg0i_7_.D
// Type: Node_reg
BEGIN j2c_reg_creg0i_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_7_.Q  	1
END

// Signal Name: j2c_reg_creg0i_7_.C
// Type: Node_reg
BEGIN j2c_reg_creg0i_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_creg0i_7_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0i_7_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: j2c_reg_creg0i_7_.AR
// Type: Node_reg
BEGIN j2c_reg_creg0i_7_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_creg0i_7_.AP
// Type: Node_reg
BEGIN j2c_reg_creg0i_7_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: j2c_reg_creg0i_6_.D
// Type: Node_reg
BEGIN j2c_reg_creg0i_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_6_.Q  	1
END

// Signal Name: j2c_reg_creg0i_6_.C
// Type: Node_reg
BEGIN j2c_reg_creg0i_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_creg0i_6_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0i_6_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: j2c_reg_creg0i_6_.AR
// Type: Node_reg
BEGIN j2c_reg_creg0i_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ni_nires_reg_data_out_10_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_10_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2pos_0_.Q	1
Fanin Node      	ni_nires_reg_data3pos_0_.Q	1
Fanin Node      	ni_nires_reg_data0pos_0_.Q	1
Fanin Node      	ni_nires_reg_data1pos_0_.Q	1
END

// Signal Name: ni_nires_reg_data_out_10_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_10_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_10_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_10_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ID_1_4_.T
// Type: Node_reg
BEGIN ID_1_4_.T
Fanin Number		5
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_1_3_.Q           	1
Fanin Node      	ID_1_2_.Q           	4
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
Fanin Node      	nx1578.BLIF         	1
END

// Signal Name: ID_1_4_.C
// Type: Node_reg
BEGIN ID_1_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_4_.CE
// Type: Node_reg
BEGIN ID_1_4_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_1_4_.AR
// Type: Node_reg
BEGIN ID_1_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: ni_nires_reg_data2pos_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data2pos_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3pos_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0pos_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ID_1_6_.T
// Type: Node_reg
BEGIN ID_1_6_.T
Fanin Number		7
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_1_3_.Q           	1
Fanin Node      	ID_1_2_.Q           	4
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
Fanin Node      	nx1578.BLIF         	1
Fanin Node      	ID_1_4_.Q           	1
Fanin Node      	ID_1_5_.Q           	1
END

// Signal Name: ID_1_6_.C
// Type: Node_reg
BEGIN ID_1_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_6_.CE
// Type: Node_reg
BEGIN ID_1_6_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_1_6_.AR
// Type: Node_reg
BEGIN ID_1_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: nx1519
// Type: Node
BEGIN nx1519
Fanin Number		5
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_data_out_11_.Q	4
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_12_.Q	4
END

// Signal Name: ni_nires_reg_data1pos_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ID_1_5_.T
// Type: Node_reg
BEGIN ID_1_5_.T
Fanin Number		6
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		2
Fanin Node      	ID_1_3_.Q           	1
Fanin Node      	ID_1_2_.Q           	4
Fanin Node      	ID_1_1_.Q           	3
Fanin Node      	ID_1_0_.Q           	2
Fanin Node      	nx1578.BLIF         	1
Fanin Node      	ID_1_4_.Q           	1
END

// Signal Name: ID_1_5_.C
// Type: Node_reg
BEGIN ID_1_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_1_5_.CE
// Type: Node_reg
BEGIN ID_1_5_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Output    	TX_EN.Q             	1
END

// Signal Name: ID_1_5_.AR
// Type: Node_reg
BEGIN ID_1_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: j2c_reg_creg0i_1_.D
// Type: Node_reg
BEGIN j2c_reg_creg0i_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_1_.Q  	1
END

// Signal Name: j2c_reg_creg0i_1_.C
// Type: Node_reg
BEGIN j2c_reg_creg0i_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_creg0i_1_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0i_1_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: j2c_reg_creg0i_1_.AR
// Type: Node_reg
BEGIN j2c_reg_creg0i_1_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: j2c_reg_shreg_1_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_2_.Q  	1
END

// Signal Name: j2c_reg_shreg_1_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_shreg_1_.AR
// Type: Node_reg
BEGIN j2c_reg_shreg_1_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_shreg_2_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_3_.Q  	1
END

// Signal Name: j2c_reg_shreg_2_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_shreg_2_.AR
// Type: Node_reg
BEGIN j2c_reg_shreg_2_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_shreg_3_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_4_.Q  	1
END

// Signal Name: j2c_reg_shreg_3_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_shreg_3_.AR
// Type: Node_reg
BEGIN j2c_reg_shreg_3_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ID_3_6_.T
// Type: Node_reg
BEGIN ID_3_6_.T
Fanin Number		6
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
Fanin Node      	ID_3_3_.Q           	4
Fanin Node      	ID_3_5_.Q           	1
Fanin Node      	ID_3_4_.Q           	1
END

// Signal Name: ID_3_6_.C
// Type: Node_reg
BEGIN ID_3_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_6_.CE
// Type: Node_reg
BEGIN ID_3_6_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_pos.Q	4
END

// Signal Name: ID_3_6_.AR
// Type: Node_reg
BEGIN ID_3_6_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: j2c_reg_creg0i_0_.D
// Type: Node_reg
BEGIN j2c_reg_creg0i_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_0_.Q  	1
END

// Signal Name: j2c_reg_creg0i_0_.C
// Type: Node_reg
BEGIN j2c_reg_creg0i_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_creg0i_0_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0i_0_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: j2c_reg_creg0i_0_.AR
// Type: Node_reg
BEGIN j2c_reg_creg0i_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_creg0i_0_.AP
// Type: Node_reg
BEGIN j2c_reg_creg0i_0_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ID_3_5_.T
// Type: Node_reg
BEGIN ID_3_5_.T
Fanin Number		5
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
Fanin Node      	ID_3_3_.Q           	4
Fanin Node      	ID_3_4_.Q           	1
END

// Signal Name: ID_3_5_.C
// Type: Node_reg
BEGIN ID_3_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_5_.CE
// Type: Node_reg
BEGIN ID_3_5_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_pos.Q	4
END

// Signal Name: ID_3_5_.AR
// Type: Node_reg
BEGIN ID_3_5_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: j2c_reg_shreg_0_.D
// Type: Node_reg
BEGIN j2c_reg_shreg_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_1_.Q  	1
END

// Signal Name: j2c_reg_shreg_0_.C
// Type: Node_reg
BEGIN j2c_reg_shreg_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	jTCK.BLIF           	0
END

// Signal Name: j2c_reg_shreg_0_.AR
// Type: Node_reg
BEGIN j2c_reg_shreg_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ID_3_4_.D.X1
// Type: Node_reg
BEGIN ID_3_4_.D.X1
Fanin Number		4
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_2_.Q           	3
Fanin Node      	ID_3_1_.Q           	2
Fanin Node      	ID_3_0_.Q           	1
Fanin Node      	ID_3_3_.Q           	4
END

// Signal Name: ID_3_4_.D.X2
// Type: Node_reg
BEGIN ID_3_4_.D.X2
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ID_3_4_.Q           	1
END

// Signal Name: ID_3_4_.C
// Type: Node_reg
BEGIN ID_3_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ID_3_4_.CE
// Type: Node_reg
BEGIN ID_3_4_.CE
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_reg_ce_prty_bit_pos.Q	4
END

// Signal Name: ID_3_4_.AR
// Type: Node_reg
BEGIN ID_3_4_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ID_2_2__0.BLIF      	1
END

// Signal Name: j2c_reg_creg0i_3_.D
// Type: Node_reg
BEGIN j2c_reg_creg0i_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_3_.Q  	1
END

// Signal Name: j2c_reg_creg0i_3_.C
// Type: Node_reg
BEGIN j2c_reg_creg0i_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_creg0i_3_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0i_3_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: j2c_reg_creg0i_3_.AR
// Type: Node_reg
BEGIN j2c_reg_creg0i_3_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: j2c_reg_creg0i_3_.AP
// Type: Node_reg
BEGIN j2c_reg_creg0i_3_.AP
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: j2c_reg_creg0i_2_.D
// Type: Node_reg
BEGIN j2c_reg_creg0i_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	j2c_reg_shreg_2_.Q  	1
END

// Signal Name: j2c_reg_creg0i_2_.C
// Type: Node_reg
BEGIN j2c_reg_creg0i_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	nx599.BLIF          	1
END

// Signal Name: j2c_reg_creg0i_2_.CE
// Type: Node_reg
BEGIN j2c_reg_creg0i_2_.CE
Fanin Number		3
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Input     	jTDI.BLIF           	0
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Signal Name: j2c_reg_creg0i_2_.AR
// Type: Node_reg
BEGIN j2c_reg_creg0i_2_.AR
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
END

// Signal Name: ni_nires_reg_data_out_12_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_12_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2pos_2_.Q	1
Fanin Node      	ni_nires_reg_data3pos_2_.Q	1
Fanin Node      	ni_nires_reg_data0pos_2_.Q	1
Fanin Node      	ni_nires_reg_data1pos_2_.Q	1
END

// Signal Name: ni_nires_reg_data_out_12_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_12_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_12_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_12_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2pos_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data2pos_2_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_2_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3pos_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_2_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_2_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0pos_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_2_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_2_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1738
// Type: Node
BEGIN nx1738
Fanin Number		14
Pterm Number		9
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Node      	j2c_reg_cmdreg_1_.Q 	1
Fanin Node      	j2c_reg_cmdreg_2_.Q 	1
Fanin Node      	j2c_reg_creg1i_6_reg.Q	1
Fanin Output    	LOOPEN.Q            	1
Fanin Output    	ENABLE.Q            	1
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
Fanin Node      	ID_1_4_.Q           	1
Fanin Node      	ID_1_6_.Q           	1
Fanin Node      	ID_1_5_.Q           	1
Fanin Node      	ID_3_6_.Q           	1
Fanin Node      	ID_3_5_.Q           	1
Fanin Node      	ID_3_4_.Q           	1
END

// Signal Name: ni_nires_reg_data1pos_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_2_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_2_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1601
// Type: Node
BEGIN nx1601
Fanin Number		5
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_data_out_11_.Q	4
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
END

// Signal Name: ni_nires_reg_data_out_13_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_13_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2pos_3_.Q	1
Fanin Node      	ni_nires_reg_data3pos_3_.Q	1
Fanin Node      	ni_nires_reg_data0pos_3_.Q	1
Fanin Node      	ni_nires_reg_data1pos_3_.Q	1
END

// Signal Name: ni_nires_reg_data_out_13_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_13_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_13_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_13_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2pos_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data2pos_3_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_3_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1613.X1
// Type: Node
BEGIN nx1613.X1
Fanin Number		6
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_18_.Q	4
Fanin Node      	ni_nires_reg_data_out_19_.Q	4
END

// Signal Name: nx1613.X2
// Type: Node
BEGIN nx1613.X2
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	ni_nires_reg_data_out_18_.Q	4
END

// Signal Name: ni_nires_reg_data3pos_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_3_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_3_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0pos_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_3_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_3_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1pos_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_3_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_3_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data_out_14_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_14_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2pos_4_.Q	1
Fanin Node      	ni_nires_reg_data3pos_4_.Q	1
Fanin Node      	ni_nires_reg_data0pos_4_.Q	1
Fanin Node      	ni_nires_reg_data1pos_4_.Q	1
END

// Signal Name: ni_nires_reg_data_out_14_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_14_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_14_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_14_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2pos_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data2pos_4_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_4_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3pos_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_4_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_4_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0pos_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_4_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_4_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1pos_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_4_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_4_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data_out_15_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_15_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2pos_5_.Q	1
Fanin Node      	ni_nires_reg_data3pos_5_.Q	1
Fanin Node      	ni_nires_reg_data0pos_5_.Q	1
Fanin Node      	ni_nires_reg_data1pos_5_.Q	1
END

// Signal Name: ni_nires_reg_data_out_15_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_15_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_15_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_15_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2pos_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data2pos_5_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_5_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3pos_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_5_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_5_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0pos_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_5_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_5_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1pos_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_5_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_5_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data_out_16_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_16_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2pos_6_.Q	1
Fanin Node      	ni_nires_reg_data3pos_6_.Q	1
Fanin Node      	ni_nires_reg_data0pos_6_.Q	1
Fanin Node      	ni_nires_reg_data1pos_6_.Q	1
END

// Signal Name: ni_nires_reg_data_out_16_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_16_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_16_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_16_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2pos_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data2pos_6_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_6_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3pos_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_6_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_6_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0pos_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_6_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_6_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1pos_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_6_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_6_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1719
// Type: Node
BEGIN nx1719
Fanin Number		5
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_15_.Q	4
END

// Signal Name: ni_nires_reg_data_out_17_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_17_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2pos_7_.Q	1
Fanin Node      	ni_nires_reg_data3pos_7_.Q	1
Fanin Node      	ni_nires_reg_data0pos_7_.Q	1
Fanin Node      	ni_nires_reg_data1pos_7_.Q	1
END

// Signal Name: ni_nires_reg_data_out_17_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_17_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_17_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_17_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2pos_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data2pos_7_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_7_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3pos_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_7_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_7_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1743.X1
// Type: Node
BEGIN nx1743.X1
Fanin Number		6
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_16_.Q	4
Fanin Node      	ni_nires_reg_data_out_17_.Q	4
END

// Signal Name: nx1743.X2
// Type: Node
BEGIN nx1743.X2
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	ni_nires_reg_data_out_17_.Q	4
END

// Signal Name: ni_nires_reg_data0pos_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_7_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_7_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1pos_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_7_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_7_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1770
// Type: Node
BEGIN nx1770
Fanin Number		5
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_15_.Q	4
Fanin Node      	ni_nires_reg_data_out_16_.Q	4
END

// Signal Name: ni_nires_reg_data_out_18_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_18_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2pos_8_.Q	1
Fanin Node      	ni_nires_reg_data3pos_8_.Q	1
Fanin Node      	ni_nires_reg_data0pos_8_.Q	1
Fanin Node      	ni_nires_reg_data1pos_8_.Q	1
END

// Signal Name: ni_nires_reg_data_out_18_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_18_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_18_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_18_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2pos_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data2pos_8_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_8_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3pos_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_8_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_8_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0pos_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_8_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_8_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1pos_8_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_8_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_8_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_8_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_8_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_8_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_8_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_8_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_8_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1782
// Type: Node
BEGIN nx1782
Fanin Number		4
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_13_.Q	4
Fanin Node      	ni_nires_reg_data_out_14_.Q	4
END

// Signal Name: ni_nires_reg_data_out_19_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_19_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2pos_9_.Q	1
Fanin Node      	ni_nires_reg_data3pos_9_.Q	1
Fanin Node      	ni_nires_reg_data0pos_9_.Q	1
Fanin Node      	ni_nires_reg_data1pos_9_.Q	1
END

// Signal Name: ni_nires_reg_data_out_19_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_19_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_19_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_19_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2pos_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2pos_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2pos_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data2pos_9_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2pos_9_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3pos_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3pos_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3pos_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data3pos_9_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3pos_9_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0pos_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0pos_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0pos_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data0pos_9_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0pos_9_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1pos_9_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_9_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_9_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1pos_9_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_9_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1pos_9_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_9_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_gray_cnt_0_.Q	1
END

// Signal Name: ni_nires_reg_data1pos_9_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1pos_9_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx815
// Type: Node
BEGIN nx815
Fanin Number		5
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_1_.Q	4
Fanin Node      	ni_nires_reg_data_out_2_.Q	4
END

// Signal Name: nx1808
// Type: Node
BEGIN nx1808
Fanin Number		5
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_13_.Q	4
END

// Signal Name: ni_nires_reg_data_out_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_1_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_1_.Q	1
Fanin Node      	ni_nires_reg_data3neg_1_.Q	1
Fanin Node      	ni_nires_reg_data0neg_1_.Q	1
Fanin Node      	ni_nires_reg_data1neg_1_.Q	1
END

// Signal Name: ni_nires_reg_data_out_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_1_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2neg_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data2neg_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_1_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3neg_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_1_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0neg_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_1_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1neg_1_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_1_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_1_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_1_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_1_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_1_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_1_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_1_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_1_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data_out_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_0_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_0_.Q	1
Fanin Node      	ni_nires_reg_data3neg_0_.Q	1
Fanin Node      	ni_nires_reg_data0neg_0_.Q	1
Fanin Node      	ni_nires_reg_data1neg_0_.Q	1
END

// Signal Name: ni_nires_reg_data_out_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2neg_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data2neg_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3neg_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0neg_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1neg_0_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_0_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_0_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_0_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_0_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_0_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_0_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_0_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_0_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data_out_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_2_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_2_.Q	1
Fanin Node      	ni_nires_reg_data3neg_2_.Q	1
Fanin Node      	ni_nires_reg_data0neg_2_.Q	1
Fanin Node      	ni_nires_reg_data1neg_2_.Q	1
END

// Signal Name: ni_nires_reg_data_out_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_2_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_2_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2neg_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data2neg_2_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_2_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3neg_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_2_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_2_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx923
// Type: Node
BEGIN nx923
Fanin Number		5
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_1_.Q	4
END

// Signal Name: ni_nires_reg_data0neg_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_2_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_2_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1neg_2_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_2_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_2_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_2_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_2_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_2_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_2_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_2_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_2_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx939.X1
// Type: Node
BEGIN nx939.X1
Fanin Number		6
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_data_out_8_.Q	4
Fanin Node      	ni_nires_reg_data_out_9_.Q	4
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
END

// Signal Name: nx939.X2
// Type: Node
BEGIN nx939.X2
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	ni_nires_reg_data_out_8_.Q	4
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
END

// Signal Name: ni_nires_reg_data_out_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_3_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_3_.Q	1
Fanin Node      	ni_nires_reg_data3neg_3_.Q	1
Fanin Node      	ni_nires_reg_data0neg_3_.Q	1
Fanin Node      	ni_nires_reg_data1neg_3_.Q	1
END

// Signal Name: ni_nires_reg_data_out_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_3_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_3_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2neg_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data2neg_3_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_3_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3neg_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_3_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_3_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0neg_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_3_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_3_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1neg_3_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_3_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_3_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_3_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_3_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_3_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_3_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_3_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_3_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data_out_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_4_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_4_.Q	1
Fanin Node      	ni_nires_reg_data3neg_4_.Q	1
Fanin Node      	ni_nires_reg_data0neg_4_.Q	1
Fanin Node      	ni_nires_reg_data1neg_4_.Q	1
END

// Signal Name: ni_nires_reg_data_out_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_4_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_4_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2neg_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data2neg_4_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_4_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3neg_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_4_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_4_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0neg_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_4_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_4_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1neg_4_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_4_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_4_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_4_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_4_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_4_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_4_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_4_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_4_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1922
// Type: Node
BEGIN nx1922
Fanin Number		10
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Node      	j2c_reg_cmdreg_1_.Q 	1
Fanin Node      	j2c_reg_cmdreg_2_.Q 	1
Fanin Node      	ID_2_0_.Q           	1
Fanin Node      	ID_0_1_.Q           	2
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
Fanin Node      	j2c_reg_creg0i_1_.Q 	1
Fanin Node      	j2c_reg_creg0i_0_.Q 	1
Fanin Node      	j2c_reg_creg0i_2_.Q 	1
END

// Signal Name: ni_nires_reg_data_out_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_5_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_5_.Q	1
Fanin Node      	ni_nires_reg_data3neg_5_.Q	1
Fanin Node      	ni_nires_reg_data0neg_5_.Q	1
Fanin Node      	ni_nires_reg_data1neg_5_.Q	1
END

// Signal Name: ni_nires_reg_data_out_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_5_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_5_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2neg_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data2neg_5_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_5_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3neg_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_5_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_5_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0neg_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_5_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_5_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1neg_5_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_5_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_5_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_5_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_5_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_5_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_5_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_5_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_5_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data_out_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_6_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_6_.Q	1
Fanin Node      	ni_nires_reg_data3neg_6_.Q	1
Fanin Node      	ni_nires_reg_data0neg_6_.Q	1
Fanin Node      	ni_nires_reg_data1neg_6_.Q	1
END

// Signal Name: ni_nires_reg_data_out_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_6_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_6_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2neg_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data2neg_6_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_6_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3neg_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_6_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_6_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0neg_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_6_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_6_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1946
// Type: Node
BEGIN nx1946
Fanin Number		8
Pterm Number		3
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	DIS_JTG.BLIF        	0
Fanin Node      	j2c_reg_cmdreg_1_.Q 	1
Fanin Node      	j2c_reg_cmdreg_2_.Q 	1
Fanin Node      	ID_0_3_.Q           	4
Fanin Node      	ID_2_3_.Q           	4
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
Fanin Node      	j2c_reg_creg0i_3_.Q 	1
END

// Signal Name: ni_nires_reg_data1neg_6_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_6_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_6_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_6_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_6_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_6_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_6_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_6_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_6_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: nx1033
// Type: Node
BEGIN nx1033
Fanin Number		6
Pterm Number		5
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_reg_creg0i_4_.Q 	1
Fanin Node      	j2c_reg_creg0i_5_.Q 	1
Fanin Node      	j2c_reg_creg0i_7_.Q 	1
Fanin Node      	j2c_reg_creg0i_6_.Q 	1
Fanin Node      	ni_nires_reg_data_out_4_.Q	4
Fanin Node      	ni_nires_reg_data_out_5_.Q	4
END

// Signal Name: ni_nires_reg_data_out_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data_out_7_.D
Fanin Number		6
Pterm Number		4
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_old_cnt_0_.Q	1
Fanin Node      	ni_nires_reg_old_cnt_1_.Q	1
Fanin Node      	ni_nires_reg_data2neg_7_.Q	1
Fanin Node      	ni_nires_reg_data3neg_7_.Q	1
Fanin Node      	ni_nires_reg_data0neg_7_.Q	1
Fanin Node      	ni_nires_reg_data1neg_7_.Q	1
END

// Signal Name: ni_nires_reg_data_out_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data_out_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	clk.BLIF            	0
END

// Signal Name: ni_nires_reg_data_out_7_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data_out_7_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data2neg_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data2neg_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data2neg_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data2neg_7_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data2neg_7_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data3neg_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data3neg_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data3neg_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data3neg_7_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data3neg_7_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data0neg_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data0neg_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data0neg_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data0neg_7_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data0neg_7_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ni_nires_reg_data1neg_7_.D
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_7_.D
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_D_7_.BLIF        	0
END

// Signal Name: ni_nires_reg_data1neg_7_.C
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_7_.C
Fanin Number		1
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	NI_STR.BLIF         	0
END

// Signal Name: ni_nires_reg_data1neg_7_.CE
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_7_.CE
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		1
Fanin Node      	ni_nires_reg_gray_cntf_0_.Q	1
Fanin Node      	ni_nires_reg_gray_cntf_1_.Q	1
END

// Signal Name: ni_nires_reg_data1neg_7_.AR
// Type: Node_reg
BEGIN ni_nires_reg_data1neg_7_.AR
Fanin Number		0
Pterm Number		0
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
END

// Signal Name: ID_2_2__0
// Type: Node
BEGIN ID_2_2__0
Fanin Number		2
Pterm Number		1
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Input     	reset_n.BLIF        	0
Fanin Node      	j2c_reg_rstout_n_i.Q	1
END

// Signal Name: j2c_reg_rstout_n_i_0
// Type: Node
BEGIN j2c_reg_rstout_n_i_0
Fanin Number		5
Pterm Number		2
Fanin per Macrocell	N/A
Cluster PT		N/A
Logic Levels		N/A
Fanin Node      	j2c_bitcnt_2_.Q     	3
Fanin Node      	j2c_bitcnt_1_.Q     	2
Fanin Node      	j2c_bitcnt_0_.Q     	1
Fanin Node      	j2c_reg_cmdreg_3_.Q 	1
Fanin Node      	j2c_reg_cmdreg_0_.Q 	1
END

// Design 'top_ni' used clock signal list:
CLOCK	clk
CLOCK	NI_STR
CLOCK	jTCK