LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

-- top_ni

entity top_ni is
generic(
        Ntrackl       : Integer :=     8+0*2; -- 16 bit words tracklet data
        Ndata         : Integer := 28000+0*2; -- 16 bit words raw data
        IdlePeriod    : Integer :=        25; --
        Nt            : Integer :=        15; -- bits in the timer
        TimeT2D       : integer :=       250; -- clocks delay from tracklet to raw data (in 125MHz)
        PatternId     : Integer :=       1+0  -- from 0 to 15
        );
    port (
           -- pin 3, SD2x
           reset_n              : in    std_logic;
           start                : in    std_logic;
           -- pin 89 the serializer clock, must be not slower than NI_STR
           clk                  : in    std_logic; -- is the clock
           -- to/from TLK2501
           -- pin 44
           TESTEN               : out   std_logic; -- must be low
           -- pin 47
           PRBSEN               : out std_logic;
           -- pin 48
           LCKREFN              : out std_logic; -- must be low for transmitter only
           -- pin 49
           ENABLE               : out std_logic;
           -- pin 53
           LOOPEN               : out std_logic;
           -- pin 50
           TX_ER                : out std_logic;
           -- pin 54
           TX_EN                : out   std_logic;
           -- pins 55, 56, 58, 59, 60, 61, 64, 65, 67, 69, 70, 71, 72, 78, 79, 80
           -- bit  15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0
           TXD                  : out   std_logic_vector(15 downto 0);

           -- pin 84
           EN                   : out std_logic;
           -- pin 3
           SD2ANL               : out   std_logic;
           -- I2C
           SCL                  : out   std_logic;
           SDA                  : inout std_logic;

           jTDO                 : out   std_logic
           );
end top_ni;

--------------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------------
architecture a of top_ni is

type sm_type is (idle, send_t, send_emt, wait_r, send_d, send_emd);

signal sm : sm_type;

constant endm_tr : std_logic_vector(15 downto 0) := "1010101010101010"; -- 0xAAAA
constant endm_rr : std_logic_vector(15 downto 0) := "0000000000000000"; -- 0x0000

signal s_data    : std_logic_vector(11 downto 0);
signal p_data    : std_logic_vector( 3 downto 0);

signal t_data_ini: std_logic_vector(11 downto 0);
signal r_data_ini: std_logic_vector(11 downto 0);

signal timer     : std_logic_vector(Nt-1 downto 0);
signal cdata     : std_logic_vector(Nt-1 downto 0);
signal i_data    : std_logic_vector(   4 downto 0);
signal start_s   : std_logic;
signal dis_next  : std_logic;

begin

    t_data_ini <= "1010" & "00000000";
    r_data_ini <= "0000" & "00000000";


    SCL     <= 'Z';
    SDA     <= 'Z';
    jTDO    <= 'Z';

    SD2ANL  <= '1';
    TX_ER   <= '0';
    TESTEN  <= '0';
    PRBSEN  <= '0';
    LCKREFN <= '0';
    ENABLE  <= '1';
    LOOPEN  <= '0';
    EN      <= '1';

    process(clk, reset_n)
    begin
        if reset_n = '0' then
            sm      <= idle;
            timer   <= (others => '0');
            TX_EN   <= '0';
            s_data  <= (others => '0');
            p_data  <= (others => '0');
            cdata   <= (others => '0');
            i_data  <= (others => '0');
            start_s <= '0';
            dis_next <= '0';
        elsif clk'event and clk='1' then
            timer   <= timer + 1;
            start_s <= start;
            p_data  <= conv_std_logic_vector(PatternId,4);
            i_data  <= conv_std_logic_vector(IdlePeriod-1, i_data'length);
            if i_data=0 then dis_next <= '1'; else dis_next <= '0'; end if;
            case sm is
            when idle =>
                TX_EN <= '0';
                timer  <= (others => '0');
                s_data <= t_data_ini;
                cdata <= (others => '0');
                if start_s = '1' then sm <= send_t; end if;
            when send_t =>
                TX_EN <= '1';
                s_data <= s_data + 1;
                cdata  <= cdata  + 1;
--                i_data <= i_data - 1;
                if cdata = conv_std_logic_vector(Ntrackl, cdata'length) then
                    TX_EN  <= '0';
                    sm     <= send_emt;
                    cdata  <= (others => '0');
                end if;
            when send_emt =>
                TX_EN  <= '1';
                s_data <= endm_tr(11 downto  0);
                p_data <= endm_tr(15 downto 12);
                if cdata = 3 then sm <= wait_r; end if;
                cdata  <= cdata  + 1;
            when wait_r =>
                TX_EN <= '0';
                s_data <= r_data_ini;
                cdata  <= (others => '0');
                if timer = conv_std_logic_vector(TimeT2D+Ntrackl, timer'length) then
                    if start_s = '1' then sm <= send_d; else sm <= idle; end if;
                end if;
            when send_d =>
                i_data <= i_data - 1;
                if dis_next = '1' then
                    TX_EN  <= '0';
                    i_data <= conv_std_logic_vector(IdlePeriod-1, i_data'length);
                else
                    TX_EN  <= '1';
                    s_data <= s_data + 1;
                    cdata  <= cdata  + 1;
                    if cdata = conv_std_logic_vector(Ndata, cdata'length) then
                        TX_EN  <= '0';
                        sm     <= send_emd;
                        cdata  <= (others => '0');
                    end if;
                end if;
            when send_emd =>
                TX_EN <= '1';
                s_data <= endm_rr(11 downto  0);
                p_data <= endm_rr(15 downto 12);
                if cdata = 3 then sm <= idle; end if;
                cdata  <= cdata  + 1;
            when others => sm <= idle;
            end case;
        end if;
    end process;

    TXD   <=  p_data & s_data;

end;