LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;


entity patt_reg is
generic (dir : Integer := 0);
port (  clk   : in  std_logic;
        ce    : in  std_logic;
        tge   : in  std_logic;
        tgm   : in  std_logic; -- test generator mode
        rst_n : in  std_logic;
        d     : in  std_logic_vector(7 downto 0);
        q     : out std_logic_vector(7 downto 0)
    );
end patt_reg;

architecture a of patt_reg is

signal d_L  : std_logic_vector(3 downto 0);
signal d_H  : std_logic_vector(3 downto 0);

signal q_L  : std_logic_vector(3 downto 0);
signal q_H  : std_logic_vector(3 downto 0);

begin

sw:    if dir = 1 generate
    d_L <= d(7 downto 4);
    d_H <= d(3 downto 0);
    end generate;
swn:   if dir /= 1 generate
    d_L <= d(3 downto 0);
    d_H <= d(7 downto 4);
    end generate;

    process(clk, rst_n)
    begin
    if rst_n = '0' then
         q_L <= "0000";
         q_H <= "1111";
    elsif clk'event and clk= '1' then
        if tgm='1' then
            if tge = '1' then
                q_L <= q_L + 1;
                q_H <= q_H - 1;
            end if;
        else
            if ce = '1' then
                q_L <= d_L;
                q_H <= d_H;
            end if;
        end if;
    end if;
    end process;

swo: if dir = 1 generate
    q(3 downto 0) <= q_H;
    q(7 downto 4) <= q_L;
    end generate;

swon: if dir /= 1 generate
    q(3 downto 0) <= q_L;
    q(7 downto 4) <= q_H;
    end generate;

end;