LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;


entity patt_reg is
generic (dir : Integer := 0);
port (  clk   : in  std_logic;
        ce    : in  std_logic;
        tge   : in  std_logic;
        tgm   : in  std_logic; -- test generator mode
        rst_n : in  std_logic;
        d     : in  std_logic_vector(7 downto 0);
        q     : out std_logic_vector(7 downto 0)
    );
end patt_reg;

architecture a of patt_reg is

signal q_i  : std_logic_vector(7 downto 0);

begin

up:    if dir = 1 generate

    process(clk, rst_n)
    begin
    if rst_n = '0' then
         q_i <= (others => '0');
    elsif clk'event and clk= '1' then
        if tgm='1' then
            if tge = '1' then
                q_i <= q_i + 1;
            end if;
        else
            if ce = '1' then
                q_i <= d;
            end if;
        end if;
    end if;
    end process;
end generate;

dn:    if dir /= 1 generate

    process(clk, rst_n)
    begin
    if rst_n = '0' then
         q_i <= (others => '0');
    elsif clk'event and clk= '1' then
        if tgm='1' then
            if tge = '1' then
                q_i <= q_i - 1;
            end if;
        else
            if ce = '1' then
                q_i <= d;
            end if;
        end if;
    end if;
    end process;
end generate;

    q <= q_i;

end;